Change in ...coreboot[master]: soc/intel/braswell/southcluster.c: Correct typo in comment

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32453

Change subject: soc/intel/braswell/southcluster.c: Correct typo in comment
......................................................................

soc/intel/braswell/southcluster.c: Correct typo in comment

BUG=N/A
TEST=build

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/southcluster.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32453/1

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 000790d..bf9f689 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -347,7 +347,7 @@
  * Common code for the south cluster devices.
  */

-/* Set bit in function disble register to hide this device. */
+/* Set bit in function disable register to hide this device. */
 static void sc_disable_devfn(struct device *dev)
 {
    void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: soc/intel/braswell/southcluster.c: Correct typo in comment
......................................................................

Patch Set 1: Code-Review+2

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: soc/intel/braswell/southcluster.c: Correct typo in comment
......................................................................

Patch Set 1:

$ git grep -in disble
src/soc/intel/braswell/southcluster.c:350:/* Set bit in function disble register to hide this device. */
src/southbridge/intel/bd82x6x/pch.c:147:/* Set bit in Function Disble register to hide this device */
src/southbridge/intel/lynxpoint/pch.c:103:/* Set bit in Function Disble register to hide this device */

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: soc/intel/braswell/southcluster.c: Correct typo in comment
......................................................................

Patch Set 1:
> Patch Set 1:
>
> $ git grep -in disble
> src/soc/intel/braswell/southcluster.c:350:/* Set bit in function disble register to hide this device. */
> src/southbridge/intel/bd82x6x/pch.c:147:/* Set bit in Function Disble register to hide this device */
> src/southbridge/intel/lynxpoint/pch.c:103:/* Set bit in Function Disble register to hide this device */

Will add test files to this comment.

Change in ...coreboot[master]: {soc, southbridge} : Correct typo in comment

[Frans Hendriks (Code Review)]

Hello Patrick Rudolph, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32453

to look at the new patch set (#2).

Change subject: {soc, southbridge} : Correct typo in comment
......................................................................

{soc, southbridge} : Correct typo in comment

BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/southcluster.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/lynxpoint/pch.c
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32453/2

Change in ...coreboot[master]: {soc, southbridge} : Correct typo in comment

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: {soc, southbridge} : Correct typo in comment
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/32453/2/src/southbridge/intel/bd82x6x/pch.c 
File src/southbridge/intel/bd82x6x/pch.c:

https://review.coreboot.org/#/c/32453/2/src/southbridge/intel/bd82x6x/pch.c@... 
PS2, Line 147: Function Disable
please use lower case letters:
"function disable"

Change in ...coreboot[master]: {soc, southbridge} : Correct typo in comment

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: {soc, southbridge} : Correct typo in comment
......................................................................

Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/#/c/32453/2/src/southbridge/intel/lynxpoint/pch.... 
File src/southbridge/intel/lynxpoint/pch.c:

https://review.coreboot.org/#/c/32453/2/src/southbridge/intel/lynxpoint/pch.... 
PS2, Line 103: Function Disable
same here

Change in ...coreboot[master]: {soc, southbridge} : Correct typo in comment

[Frans Hendriks (Code Review)]

Hello Patrick Rudolph, HAOUAS Elyes, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32453

to look at the new patch set (#3).

Change subject: {soc, southbridge} : Correct typo in comment
......................................................................

{soc, southbridge} : Correct typo in comment

BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/southcluster.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/lynxpoint/pch.c
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32453/3

Change in ...coreboot[master]: {soc, southbridge} : Correct typo in comment

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: {soc, southbridge} : Correct typo in comment
......................................................................

Patch Set 3: Code-Review+2

Change in ...coreboot[master]: {soc, southbridge} : Correct typo in comment

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32453 )

Change subject: {soc, southbridge} : Correct typo in comment
......................................................................

{soc, southbridge} : Correct typo in comment

BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453
Reviewed-by: HAOUAS Elyes 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/braswell/southcluster.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/lynxpoint/pch.c
3 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 000790d..bf9f689 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -347,7 +347,7 @@
  * Common code for the south cluster devices.
  */

-/* Set bit in function disble register to hide this device. */
+/* Set bit in function disable register to hide this device. */
 static void sc_disable_devfn(struct device *dev)
 {
    void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 746c11a..f8540af 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -144,7 +144,7 @@
 }

#ifndef __SMM__
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in function disable register to hide this device */
 static void pch_hide_devfn(unsigned devfn)
 {
    switch (devfn) {
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 5cf67aa..a57bae3 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -100,7 +100,7 @@
    pci_write_config32(dev, PCH_PCS, reg32);
 }

-/* Set bit in Function Disble register to hide this device */
+/* Set bit in function disable register to hide this device */
 void pch_disable_devfn(struct device *dev)
 {
    switch (dev->path.pci.devfn) {