Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32518
Change subject: nb/intel/haswell: correct a typo in Kconfig ......................................................................
nb/intel/haswell: correct a typo in Kconfig
Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Signed-off-by: Joel Kitching kitching@google.com --- M src/northbridge/intel/haswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32518/1
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 8c1e0b1..e1067c5 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -37,7 +37,7 @@ Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Haswell however uses a mrc.bin to initialse memory which + Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32518
to look at the new patch set (#2).
Change subject: nb/intel/haswell: correct a typo in Kconfig ......................................................................
nb/intel/haswell: correct a typo in Kconfig
Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Signed-off-by: Joel Kitching kitching@google.com --- M src/northbridge/intel/haswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32518/2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32518 )
Change subject: nb/intel/haswell: correct a typo in Kconfig ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32518 )
Change subject: nb/intel/haswell: correct a typo in Kconfig ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32518 )
Change subject: nb/intel/haswell: correct a typo in Kconfig ......................................................................
nb/intel/haswell: correct a typo in Kconfig
Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Signed-off-by: Joel Kitching kitching@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32518 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 8c1e0b1..e1067c5 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -37,7 +37,7 @@ Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Haswell however uses a mrc.bin to initialse memory which + Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region
-
Angel Pons (Code Review) -
Joel Kitching (Code Review)
-
Julius Werner (Code Review)
-
Nico Huber (Code Review)