Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32668
Change subject: CML: Enable UPDs for PCH SLP_S0 for S0ix entry ......................................................................
CML: Enable UPDs for PCH SLP_S0 for S0ix entry
Enable PCH SLP S0 UPDs for S0ix entry.
BUG=None BRANCH=None TEST=Built and tested on Hatch
Change-Id: I57a15746705a726b402431321a45b3257d837faa --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/1
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..796b717 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,9 +177,9 @@ params->PchLanEnable = dev->enabled; if (config->s0ix_enable) { params->SlpS0WithGbeSupport = 1; - params->PchPmSlpS0VmRuntimeControl = 0; - params->PchPmSlpS0Vm070VSupport = 0; - params->PchPmSlpS0Vm075VSupport = 0; + params->PchPmSlpS0VmRuntimeControl = 1; + params->PchPmSlpS0Vm070VSupport = 1; + params->PchPmSlpS0Vm075VSupport = 1; ignore_gbe_ltr(); } }
Hello Patrick Rudolph, Subrata Banik, Rizwan Qureshi, Furquan Shaikh, Lakshmi G Prasad,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32668
to look at the new patch set (#2).
Change subject: [WIP] CML: Enable UPDs for PCH SLP_S0 for S0ix entry ......................................................................
[WIP] CML: Enable UPDs for PCH SLP_S0 for S0ix entry
Enable PCH SLP S0 UPDs for S0ix entry.
BUG=None BRANCH=None TEST=Built and tested on Hatch
Change-Id: I57a15746705a726b402431321a45b3257d837faa --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/2
Hello Patrick Rudolph, Subrata Banik, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Lakshmi G Prasad,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32668
to look at the new patch set (#3).
Change subject: [WIP] CML: Enable UPDs for PCH SLP_S0 for S0ix entry ......................................................................
[WIP] CML: Enable UPDs for PCH SLP_S0 for S0ix entry
Enable PCH SLP S0 UPDs for S0ix entry.
BUG=None BRANCH=None TEST=Built and tested on Hatch
Change-Id: I57a15746705a726b402431321a45b3257d837faa Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/3
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32668?usp=email )
Change subject: [WIP] CML: Enable UPDs for PCH SLP_S0 for S0ix entry ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Martin L Roth (Code Review) -
Sumeet R Pawnikar (Code Review)