Sumeet R Pawnikar uploaded patch set #2 to this change.

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[WIP] CML: Enable UPDs for PCH SLP_S0 for S0ix entry

Enable PCH SLP S0 UPDs for S0ix entry.

BUG=None
BRANCH=None
TEST=Built and tested on Hatch

Change-Id: I57a15746705a726b402431321a45b3257d837faa
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/2

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