Sumeet R Pawnikar has uploaded this change for review.

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CML: Enable UPDs for PCH SLP_S0 for S0ix entry

Enable PCH SLP S0 UPDs for S0ix entry.

BUG=None
BRANCH=None
TEST=Built and tested on Hatch

Change-Id: I57a15746705a726b402431321a45b3257d837faa
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index cc01d10..796b717 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -177,9 +177,9 @@
 		params->PchLanEnable = dev->enabled;
 		if (config->s0ix_enable) {
 			params->SlpS0WithGbeSupport = 1;
-			params->PchPmSlpS0VmRuntimeControl = 0;
-			params->PchPmSlpS0Vm070VSupport = 0;
-			params->PchPmSlpS0Vm075VSupport = 0;
+			params->PchPmSlpS0VmRuntimeControl = 1;
+			params->PchPmSlpS0Vm070VSupport = 1;
+			params->PchPmSlpS0Vm075VSupport = 1;
 			ignore_gbe_ltr();
 		}
 	}

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