Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mb/asus/p8z77-m: New board
......................................................................
mb/asus/p8z77-m: New board
Constructed out of a mix of autoport results, p8z77-m_pro, and
inteltool/superiotool dumps.
Does not yet boot. Submitting for eyeballs and help.
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
A src/mainboard/asus/p8z77-m/Kconfig
A src/mainboard/asus/p8z77-m/Kconfig.name
A src/mainboard/asus/p8z77-m/Makefile.inc
A src/mainboard/asus/p8z77-m/acpi/ec.asl
A src/mainboard/asus/p8z77-m/acpi/platform.asl
A src/mainboard/asus/p8z77-m/acpi/superio.asl
A src/mainboard/asus/p8z77-m/acpi_tables.c
A src/mainboard/asus/p8z77-m/cmos.default
A src/mainboard/asus/p8z77-m/cmos.layout
A src/mainboard/asus/p8z77-m/data.vbt
A src/mainboard/asus/p8z77-m/devicetree.cb
A src/mainboard/asus/p8z77-m/dsdt.asl
A src/mainboard/asus/p8z77-m/early_init.c
A src/mainboard/asus/p8z77-m/gma-mainboard.ads
A src/mainboard/asus/p8z77-m/gpio.c
A src/mainboard/asus/p8z77-m/hda_verb.c
A src/mainboard/asus/p8z77-m/mainboard.c
17 files changed, 969 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/1
diff --git a/src/mainboard/asus/p8z77-m/Kconfig b/src/mainboard/asus/p8z77-m/Kconfig
new file mode 100644
index 0000000..260597d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8Z77_M
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+ select SUPERIO_NUVOTON_NCT6779D
+
+config MAINBOARD_DIR
+ string
+ default "asus/p8z77-m"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P8Z77-M"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif
diff --git a/src/mainboard/asus/p8z77-m/Kconfig.name b/src/mainboard/asus/p8z77-m/Kconfig.name
new file mode 100644
index 0000000..a797a5b
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig.name
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_ASUS_P8Z77_M
+ bool "P8Z77-M"
diff --git a/src/mainboard/asus/p8z77-m/Makefile.inc b/src/mainboard/asus/p8z77-m/Makefile.inc
new file mode 100644
index 0000000..a12efbb
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/asus/p8z77-m/acpi/ec.asl b/src/mainboard/asus/p8z77-m/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/ec.asl
diff --git a/src/mainboard/asus/p8z77-m/acpi/platform.asl b/src/mainboard/asus/p8z77-m/acpi/platform.asl
new file mode 100644
index 0000000..d2cad26
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/platform.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asus/p8z77-m/acpi/superio.asl b/src/mainboard/asus/p8z77-m/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asus/p8z77-m/acpi_tables.c b/src/mainboard/asus/p8z77-m/acpi_tables.c
new file mode 100644
index 0000000..9c22f19
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi_tables.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* critical temp that will shutdown the pc == 95C degrees */
+ gnvs->tcrt = 95;
+
+ /* temp to start throttling the cpu == 85C */
+ gnvs->tpsv = 85;
+}
diff --git a/src/mainboard/asus/p8z77-m/cmos.default b/src/mainboard/asus/p8z77-m/cmos.default
new file mode 100644
index 0000000..725ab98
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.default
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=224M
+nmi=Enable
+sata_mode=AHCI
+#usb3_xxxx options are only used with MRC blob, ignored else
+usb3_mode=Enable
+usb3_drv=Enable
+usb3_streams=Enable
diff --git a/src/mainboard/asus/p8z77-m/cmos.layout b/src/mainboard/asus/p8z77-m/cmos.layout
new file mode 100644
index 0000000..da29d1c
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.layout
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+#400 8 r 0 reserved for century byte
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408 1 e 1 nmi
+
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# -----------------------------------------------------------------
+# coreboot config options: northbridge
+
+# gfx_uma_size
+# Quantity of shared video memory the IGP can use
+#
+416 5 e 7 gfx_uma_size
+
+# -----------------------------------------------------------------
+# coreboot config options: usb3
+
+# usb3_mode
+# Controls how the motherboard's USB3 ports act at boot time
+421 2 e 8 usb3_mode
+
+# usb3_drv
+# Load (or not) pre-OS xHCI USB3 bios driver
+#
+423 1 e 1 usb3_drv
+
+# usb3_streams
+# Streams can provide more speed (as they can use 64Kb packets),
+# but they might cause incompatibilities with some devices.
+#
+424 1 e 1 usb3_streams
+
+# -----------------------------------------------------------------
+# Sandy/Ivy Bridge MRC Scrambler Seed values
+# note: MUST NOT be covered by checksum!
+464 32 r 0 mrc_scrambler_seed
+496 32 r 0 mrc_scrambler_seed_s3
+528 16 r 0 mrc_scrambler_seed_chk
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+544 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+3 0 Fallback
+3 1 Normal
+
+# debug_level
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+# power_on_after_fail
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# sata_mode
+6 0 AHCI
+6 1 Compatible
+
+# gfx_uma_size (Intel IGP Video RAM size)
+7 0 32M
+7 1 64M
+7 2 96M
+7 3 128M
+7 4 160M
+7 5 192M
+7 6 224M
+7 7 256M
+7 8 288M
+7 9 320M
+7 10 352M
+7 11 384M
+7 12 416M
+7 13 448M
+7 14 480M
+7 15 512M
+7 16 544M
+7 17 576M
+7 18 608M
+7 19 640M
+7 20 672M
+7 21 704M
+7 22 736M
+7 23 768M
+7 24 800M
+7 25 832M
+7 26 864M
+7 27 896M
+7 28 928M
+7 29 960M
+7 30 992M
+
+# usb3_mode
+# Disable = Use the port always as USB 2.0 for compatibility
+# Enable = Use the port always as USB 3.0 for speed
+# Auto = Initialize the port as USB 2.0, until the OS loads
+# xHCI USB 3.0 driver
+# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
+# and the computer is reset, keep the USB 3.0 mode.
+#
+8 0 Disable
+8 1 Enable
+8 2 Auto
+8 3 SmartAuto
+
+# -----------------------------------------------------------------
+# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
+# <bit where to start storing checksum[must be 16bits-aligned]>
+checksums
+
+checksum 392 431 544
diff --git a/src/mainboard/asus/p8z77-m/data.vbt b/src/mainboard/asus/p8z77-m/data.vbt
new file mode 100644
index 0000000..26ab42d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8z77-m/devicetree.cb b/src/mainboard/asus/p8z77-m/devicetree.cb
new file mode 100644
index 0000000..03a20b9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/devicetree.cb
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.ndid" = "3"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1043 0x84ca inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "gen4_dec" = "0x00000000"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x3f8 # COM2 address
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # PS2 KBC
+ io 0x60 = 0x0060 # KBC1 base
+ io 0x62 = 0x0064 # KBC2 base
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+
+ # KBC 12Mhz/A20 speed/sw KBRST
+ drq 0xf0 = 0x82
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on end # GPIOs 6-8
+ device pnp 2e.8 off end # WDT1 GPIO 0-1
+ device pnp 2e.9 off end # GPIO 1-8
+ device pnp 2e.a on # ACPI
+ drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
+ drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
+ end
+ device pnp 2e.b off end # HWM, LED
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f on # GPIO PP/OD
+ drq 0xe6 = 0x7f # GP7 PP
+ end
+ device pnp 2e.14 on end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
+ end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-m/dsdt.asl b/src/mainboard/asus/p8z77-m/dsdt.asl
new file mode 100644
index 0000000..62d44ea
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asus/p8z77-m/early_init.c b/src/mainboard/asus/p8z77-m/early_init.c
new file mode 100644
index 0000000..52c0e03
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/early_init.c
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#include <option.h>
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/pei_data.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* {enable, current, oc_pin} */
+ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
+ { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
+ { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
+ { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
+ { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
+ { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
+ { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
+ { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
+ { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
+ { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
+ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
+ { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
+ { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */
+ { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */
+};
+
+/* Global config register values. */
+static const u8 register_values[] = {
+ /*
+ * Before accessing CR10, CR11, CR13 and CR14, CR26 [Bit4] must be set to logic 1.
+ * - NCT6779D datasheet, page 293
+ */
+ /* reg, value */
+ 0x26, (1 << 4),
+ 0x13, 0xff, /* IRQs 0-15 active low */
+ 0x14, 0xff,
+ 0x1b, 0x60,
+ 0x22, 0xdf, /* Power down UART B */
+ 0x2a, 0x48, /* UART A instead of GPIO8x */
+ 0x2c, 0x00, /* PECI */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ int max = ARRAY_SIZE(register_values);
+ int i;
+
+ nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+
+ /* Set registers as specified in the register_values[] array. */
+ for (i = 0; i < max; i += 2)
+ pnp_write_config(SERIAL_DEV, register_values[i], register_values[i + 1]);
+
+ pnp_set_logical_device(SERIAL_DEV);
+ pnp_set_enable(SERIAL_DEV, 0);
+ pnp_set_iobase(SERIAL_DEV, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+ pnp_set_enable(SERIAL_DEV, 1);
+ nuvoton_pnp_exit_conf_state(SERIAL_DEV);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /*
+ * USB3 mode:
+ * 0 = Disable: work always as USB 2.0(ehci)
+ * 1 = Enable: work always as USB 3.0(xhci)
+ * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
+ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
+ * and reboots, it will keep the USB3.0 speed
+ */
+ int usb3_mode = 1;
+ get_option(&usb3_mode, "usb3_mode");
+ usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
+
+ /* Load USB3 pre-OS xHCI driver */
+ int usb3_drv = 1;
+ get_option(&usb3_drv, "usb3_drv");
+ usb3_drv &= 0x1; /* ensure it's 0/1 only */
+
+ /* Use USB3 xHCI streams */
+ int usb3_streams = 1;
+ get_option(&usb3_streams, "usb3_streams");
+ usb3_streams &= 0x1; /* ensure it's 0/1 only */
+
+ struct pei_data pd = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 1, /* 0=Mobile, 1=Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
+ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
+ .dimm_channel0_disabled = 0, /* Both DIMM enabled */
+ .dimm_channel1_disabled = 0, /* Both DIMM enabled */
+ .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
+ .usb_port_config = {
+ /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 1, 0x0080 }, /* USB3 ETH top connector */
+ { 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
+ { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */
+ },
+ .usb3 = {
+ /* 0=Disable; 1=Enable (start at USB3 speed)
+ * 2=Auto (start as USB2 speed until OS loads)
+ * 3=Smart Auto (like Auto but keep speed on reboot)
+ */
+ usb3_mode,
+ /* 4 bit switch mask. 0=not switchable, 1=switchable
+ * Means once it's loaded the OS, it can swap ports
+ * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+ */
+ 0xf,
+ usb3_drv, /* 1=Load xHCI pre-OS drv */
+ /* 0=Don't use xHCI streams for better compatibility
+ * 1=use xHCI streams for better speed
+ */
+ usb3_streams
+ },
+ /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */
+ .ddr3lv_support = 1,
+ /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
+ * but might cause some system instability !
+ */
+ .pcie_init = 1,
+ /* Command Rate. 0=Auto; 1=1N; 2=2N.
+ * Leave it always at Auto for compatibility & stability
+ */
+ .nmode = 0,
+ /* DDR refresh rate. 0=Auto based on DRAM's temperature;
+ * 1=Normal rate for speed; 2=Double rate for stability
+ */
+ .ddr_refresh_rate_config = 0
+ };
+
+ /* copy the data to output PEI */
+ *pei_data = pd;
+}
diff --git a/src/mainboard/asus/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
new file mode 100644
index 0000000..d7afe73
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-m/gpio.c b/src/mainboard/asus/p8z77-m/gpio.c
new file mode 100644
index 0000000..03e1507
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gpio.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-m/hda_verb.c b/src/mainboard/asus/p8z77-m/hda_verb.c
new file mode 100644
index 0000000..f240025
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/hda_verb.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x104384a8, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x104384a8),
+ AZALIA_PIN_CFG(0, 0x11, 0x90430130),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8z77-m/mainboard.c b/src/mainboard/asus/p8z77-m/mainboard.c
new file mode 100644
index 0000000..b97b648
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/mainboard.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/38988
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Gerrit-Change-Number: 38988
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-MessageType: newchange
Hello Kyösti Mälkki, Patrick Rudolph, Michael Niewöhner,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35516
to review the following change.
Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding
......................................................................
device/pci: Ensure full 16-bit VGA port i/o decoding
So, the PCI to PCI bridge specification had a pitfall for us:
Originally, when decoding i/o ports for legacy VGA cycles, bridges
should only consider the 10 least significant bits of the port address.
This means all VGA registers were aliased every 1024 ports!
e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
However, it seems, we never reserved the aliased ports, resulting in
random conflicts. We neither use much external VGA nor many i/o ports
these days, so nobody noticed.
To avoid this mess, a bridge control bit (VGA16) was introduced in
2003 to enable decoding of 16-bit port addresses. As we don't want
to clutter our i/o port space, we'll now simply fail for VGA behind
bridges that don't support it. Famous last words: I assume there
can't be many bridges left that don't support this bit ;)
Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/device.c
M src/device/pci_device.c
M src/include/device/device.h
M src/include/device/pci_def.h
4 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35516/1
diff --git a/src/device/device.c b/src/device/device.c
index 44d1f95..523bd1c 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -757,6 +757,12 @@
while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) {
if (!dev->enabled)
continue;
+ if (dev->bus->no_vga) {
+ printk(BIOS_WARNING, "Ignoring VGA at %s"
+ ", a bridge on the path isn't supported",
+ dev_path(dev));
+ continue;
+ }
printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev));
@@ -797,7 +803,7 @@
while (bus) {
printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
dev_path(bus->dev));
- bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
+ bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16;
bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
}
}
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 7ecb652..2fadb55 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -788,6 +788,43 @@
};
/**
+ * Check for compatibility to route legacy VGA cycles through a bridge.
+ *
+ * Originally, when decoding i/o ports for legacy VGA cycles, bridges
+ * should only consider the 10 least significant bits of the port address.
+ * This means all VGA registers were aliased every 1024 ports!
+ * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
+ *
+ * To avoid this mess, a bridge control bit (VGA16) was introduced in
+ * 2003 to enable decoding of 16-bit port addresses. As we don't want
+ * to clutter our i/o port space, we simply fail for VGA behind bridges
+ * that don't support it (set .no_vga = 1).
+ */
+static void pci_bridge_vga_compat(struct bus *const bus)
+{
+ uint16_t bridge_ctrl;
+
+ bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
+
+ /* Ensure VGA decoding is disabled during probing (it should
+ be by default, but we run blobs nowadays) */
+ bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA;
+ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
+
+ /* If the upstream bridge doesn't support VGA, we don't have to check */
+ bus->no_vga |= bus->dev->bus->no_vga;
+ if (bus->no_vga)
+ return;
+
+ /* Test if we can enable 16-bit decoding */
+ bridge_ctrl |= PCI_BRIDGE_CTL_VGA16;
+ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
+ bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
+
+ bus->no_vga = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16);
+}
+
+/**
* Detect the type of downstream bridge.
*
* This function is a heuristic to detect which type of bus is downstream
@@ -1288,6 +1325,8 @@
bus = dev->link_list;
+ pci_bridge_vga_compat(bus);
+
pci_bridge_route(bus, PCI_ROUTE_SCAN);
do_scan_bus(bus, 0x00, 0xff);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index b2221cc..78e234e 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -94,6 +94,7 @@
unsigned int reset_needed : 1;
unsigned int disable_relaxed_ordering : 1;
unsigned int ht_link_up : 1;
+ unsigned int no_vga : 1; /* We can't support VGA behind this bridge */
};
/*
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index bc5bc79..c8b86d5 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -138,6 +138,7 @@
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
+#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
/* Fast Back2Back enabled on secondary interface */
--
To view, visit https://review.coreboot.org/c/coreboot/+/35516
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Gerrit-Change-Number: 35516
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33663
Change subject: Documentation: Convert cbfs.txt to markdown
......................................................................
Documentation: Convert cbfs.txt to markdown
Convert the document to markdown.
Needs to be fixed in a separate commit as it doesn't reflect coreboot v4.
Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
A Documentation/lib/cbfs.md
M Documentation/lib/index.md
2 files changed, 372 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33663/1
diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md
new file mode 100644
index 0000000..83d8b44
--- /dev/null
+++ b/Documentation/lib/cbfs.md
@@ -0,0 +1,371 @@
+# coreboot CBFS Specification
+by Jordan Crouse <jordan(a)cosmicpenguin.net>
+
+**WARNING: This documentation is written against coreboot v1.**
+
+**TODO: Update this document ASAP**
+
+## Introduction
+
+This document describes the coreboot CBFS specification (from here
+referred to as CBFS). CBFS is a scheme for managing independent chunks
+of data in a system ROM. Though not a true filesystem, the style and
+concepts are similar.
+
+
+## Architecture
+
+The CBFS architecture looks like the following:
+
+```
+/---------------\ <-- Start of ROM
+| /-----------\ | --|
+| | Header | | |
+| |-----------| | |
+| | Name | | |-- Component
+| |-----------| | |
+| |Data | | |
+| |.. | | |
+| \-----------/ | --|
+| |
+| /-----------\ |
+| | Header | |
+| |-----------| |
+| | Name | |
+| |-----------| |
+| |Data | |
+| |.. | |
+| \-----------/ |
+| |
+| ... |
+| /-----------\ |
+| | | |
+| | Bootblock | |
+| | --------- | |
+| | Reset | | <- 0xFFFFFFF0
+| \-----------/ |
+\---------------/
+```
+
+The CBFS architecture consists of a binary associated with a physical
+ROM disk referred hereafter as the ROM. A number of independent of
+components, each with a header prepended on to data are located within
+the ROM. The components are nominally arranged sequentially, though they
+are aligned along a pre-defined boundary.
+
+The bootblock occupies the last 20k of the ROM. Within
+the bootblock is a master header containing information about the ROM
+including the size, alignment of the components, and the offset of the
+start of the first CBFS component within the ROM.
+
+## Master Header
+
+The master header contains essential information about the ROM that is
+used by both the CBFS implementation within coreboot at runtime as well
+as host based utilities to create and manage the ROM. The master header
+will be located somewhere within the bootblock (last 20k of the ROM). A
+pointer to the location of the header will be located at offset
+-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a
+normal x86 system. The pointer will be to physical memory somewhere
+between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot
+to locate the header at run time. Build time utilities will
+need to read the pointer and do the appropriate math to locate the header.
+
+The following is the structure of the master header:
+
+```c
+struct cbfs_header {
+ u32 magic;
+ u32 version;
+ u32 romsize;
+ u32 bootblocksize;
+ u32 align;
+ u32 offset;
+ u32 architecture;
+ u32 pad[1];
+} __packed;
+```
+
+The meaning of each member is as follows:
+
+`magic` is a 32 bit number that identifies the ROM as a CBFS type. The
+magic
+number is 0x4F524243, which is 'ORBC' in ASCII.
+
+`version` is a version number for CBFS header. cbfs_header structure may be
+different if version is not matched.
+
+`romsize` is the size of the ROM in bytes. coreboot will subtract 'size' from
+0xFFFFFFFF to locate the beginning of the ROM in memory.
+
+`bootblocksize` is the size of bootblock reserved in firmware image.
+
+`align` is the number of bytes that each component is aligned to within the
+ROM. This is used to make sure that each component is aligned correctly
+with
+regards to the erase block sizes on the ROM - allowing one to replace a
+component at runtime without disturbing the others.
+
+`offset` is the offset of the first CBFS component (from the start of
+the ROM). This is to allow for arbitrary space to be left at the beginning
+of the ROM for things like embedded controller firmware.
+
+`architecture` describes which architecture (x86, arm, ...) this CBFS is created
+for.
+
+## Bootblock
+The bootblock is a mandatory component in the ROM. It is located in the
+last 20k of the ROM space, and contains, among other things, the location of the
+master header and the entry point for the loader firmware. The bootblock
+does not have a component header attached to it.
+
+## Components
+
+CBFS components are placed in the ROM starting at 'offset' specified in
+the master header and ending at the bootblock. Thus the total size
+available for components in the ROM is (ROM size - 20k - 'offset').
+Each CBFS component is to be aligned according to the 'align' value in the
+header.
+Thus, if a component of size 1052 is located at offset 0 with an 'align'
+value of 1024, the next component will be located at offset 2048.
+
+Each CBFS component will be indexed with a unique ASCII string name of
+unlimited size.
+
+Each CBFS component starts with a header:
+
+```c
+struct cbfs_file {
+ char magic[8];
+ unsigned int len;
+ unsigned int type;
+ unsigned int checksum;
+ unsigned int offset;
+};
+```
+
+`magic` is a magic value used to identify the header. During runtime,
+coreboot will scan the ROM looking for this value. The default magic is
+the string 'LARCHIVE'.
+
+`len` is the length of the data, not including the size of the header and
+the size of the name.
+
+`type` is a 32 bit number indicating the type of data that is attached.
+The data type is used in a number of ways, as detailed in the section
+below.
+
+`checksum` is a 32bit checksum of the entire component, including the
+header and name.
+
+`offset` is the start of the component data, based off the start of the
+header.
+The difference between the size of the header and offset is the size of the
+component name.
+
+Immediately following the header will be the name of the component,
+which will null terminated and 16 byte aligned. The following picture shows the
+structure of the header:
+
+```
+/--------\ <- start
+| Header |
+|--------| <- sizeof(struct cbfs_file)
+| Name |
+|--------| <- 'offset'
+| Data |
+| ... |
+\--------/ <- start + 'offset' + 'len'
+```
+
+### Searching Algorithm
+
+To locate a specific component in the ROM, one starts at the 'offset'
+specified in the CBFS master header. For this example, the offset will
+be 0.
+
+From that offset, the code should search for the magic string on the
+component, jumping 'align' bytes each time. So, assuming that 'align' is
+16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc.
+If the offset ever exceeds the allowable range for CBFS components, then no
+component was found.
+
+Upon recognizing a component, the software then has to search for the
+specific name of the component. This is accomplished by comparing the
+desired name with the string on the component located at
+`offset + sizeof(struct cbfs_file)`. If the string matches, then the
+component has been located, otherwise the software should add
+`'offset' + 'len'` to the offset and resume the search for the magic value.
+
+### Data Types
+
+The 'type' member of struct cbfs_file is used to identify the content
+of the component data, and is used by coreboot and other
+run-time entities to make decisions about how to handle the data.
+
+There are three component types that are essential to coreboot, and so
+are defined here.
+
+#### Stages
+
+Stages are code loaded by coreboot during the boot process. They are
+essential to a successful boot. Stages are comprised of a single blob
+of binary data that is to be loaded into a particular location in memory
+and executed. The uncompressed header contains information about how
+large the data is, and where it should be placed, and what additional memory
+needs to be cleared.
+
+Stages are assigned a component value of 0x10. When coreboot sees this
+component type, it knows that it should pass the data to a sub-function
+that will process the stage.
+
+The following is the format of a stage component:
+
+```
+/--------\
+| Header |
+|--------|
+| Binary |
+| .. |
+\--------/
+```
+
+The header is defined as:
+
+```c
+struct cbfs_stage {
+ unsigned int compression;
+ unsigned long long entry;
+ unsigned long long load;
+ unsigned int len;
+ unsigned int memlen;
+};
+```
+
+`compression` is an integer defining how the data is compressed. There
+are three compression types defined by this version of the standard:
+none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional
+types may be added assuming that coreboot understands how to handle the scheme.
+
+`entry` is a 64 bit value indicating the location where the program
+counter should jump following the loading of the stage. This should be
+an absolute physical memory address.
+
+`load` is a 64 bit value indicating where the subsequent data should be
+loaded. This should be an absolute physical memory address.
+
+`len` is the length of the compressed data in the component.
+
+`memlen` is the amount of memory that will be used by the component when
+it is loaded.
+
+The component data will start immediately following the header.
+
+When coreboot loads a stage, it will first zero the memory from 'load' to
+'memlen'. It will then decompress the component data according to the
+specified scheme and place it in memory starting at 'load'. Following that,
+it will jump execution to the address specified by 'entry'.
+Some components are designed to execute directly from the ROM - coreboot
+knows which components must do that and will act accordingly.
+
+#### Payloads
+
+Payloads are loaded by coreboot following the boot process.
+
+Stages are assigned a component value of 0x20. When coreboot sees this
+component type, it knows that it should pass the data to a sub-function
+that will process the payload. Furthermore, other run time applications such
+as 'bayou' may easily index all available payloads
+on the system by searching for the payload type.
+
+
+The following is the format of a stage component:
+
+```
+/-----------\
+| Header |
+| Segment 1 |
+| Segment 2 |
+| ... |
+|-----------|
+| Binary |
+| .. |
+\-----------/
+```
+
+The header is as follows:
+
+```c
+struct cbfs_payload {
+ struct cbfs_payload_segment segments;
+}
+```
+
+The header contains a number of segments corresponding to the segments
+that need to be loaded for the payload.
+
+The following is the structure of each segment header:
+
+```c
+struct cbfs_payload_segment {
+ unsigned int type;
+ unsigned int compression;
+ unsigned int offset;
+ unsigned long long load_addr;
+ unsigned int len;
+ unsigned int mem_len;
+};
+```
+
+`type` is the type of segment, one of the following:
+
+```eval_rst
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_CODE | 0x45444F43 | The segment contains executable code |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_DATA | 0x41544144 | The segment contains data |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_BSS | 0x20535342 | The memory specified by the segment |
+| | | should be zeroed |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_PARAMS| 0x41524150 | The segment contains information for |
+| | | the payload |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_ENTRY | 0x52544E45 | The segment contains the entry point |
+| | | for the payload |
++----------------------+-------------+---------------------------------------+
+```
+
+`compression` is the compression scheme for the segment. Each segment can
+be independently compressed. There are three compression types defined by
+this version of the standard: none (0x0), lzma (0x1), and nrv2b
+(0x02, deprecated), though additional types may be added assuming that
+coreboot understands how to handle the scheme.
+
+`offset` is the address of the data within the component, starting from
+the component header.
+
+`load_addr` is a 64 bit value indicating where the segment should be placed
+in memory.
+
+`len` is a 32 bit value indicating the size of the segment within the
+component.
+
+`mem_len` is the size of the data when it is placed into memory.
+
+The data will located immediately following the last segment.
+
+#### Option ROMS
+
+The third specified component type will be Option ROMs. Option ROMS will
+have component type '0x30'. They will have no additional header, the
+uncompressed binary data will be located in the data portion of the
+component.
+
+#### NULL
+
+There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is
+the "don't care" component type. This can be used when the component
+type is not necessary (such as when the name of the component is unique.
+i.e. option_table). It is recommended that all components be assigned a
+unique type, but NULL can be used when the type does not matter.
diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md
index 99b8061..808bac8 100644
--- a/Documentation/lib/index.md
+++ b/Documentation/lib/index.md
@@ -6,4 +6,5 @@
## Structure and layout
- [Flashmap and Flashmap Descriptor](flashmap.md)
- [ABI data consumption](abi-data-consumption.md)
+- [CBFS](cbfs.md)
- [Timestamps](timestamp.md)
--
To view, visit https://review.coreboot.org/c/coreboot/+/33663
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe
Gerrit-Change-Number: 33663
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39664 )
Change subject: util/bincfg: Add MAC address example to gbe-ich9m.set
......................................................................
util/bincfg: Add MAC address example to gbe-ich9m.set
It's not obvious how to set specific byte of a multi-byte field in the
set file. Add an example (and a template) for setting MAC address.
Change-Id: Iea983071682ffebd61757497d43c70cc8214043d
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M util/bincfg/gbe-ich9m.set
1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39664/1
diff --git a/util/bincfg/gbe-ich9m.set b/util/bincfg/gbe-ich9m.set
index 01f85ab..9c5515e 100644
--- a/util/bincfg/gbe-ich9m.set
+++ b/util/bincfg/gbe-ich9m.set
@@ -84,5 +84,13 @@
"ssdid" = 0x20ee,
"ssvid" = 0x17aa,
"did" = 0x10f5,
- "vid" = 0x8086
+ "vid" = 0x8086,
+
+ # MAC address
+ "macaddress0" = 0,
+ "macaddress1" = 0,
+ "macaddress2" = 0,
+ "macaddress3" = 0,
+ "macaddress4" = 0,
+ "macaddress5" = 0
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/39664
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iea983071682ffebd61757497d43c70cc8214043d
Gerrit-Change-Number: 39664
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io>
Gerrit-MessageType: newchange