March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: mb/asus/p8z77-m: New board

by Keith Hui (Code Review)

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38988 ) Change subject: mb/asus/p8z77-m: New board ...................................................................... mb/asus/p8z77-m: New board Constructed out of a mix of autoport results, p8z77-m_pro, and inteltool/superiotool dumps. Does not yet boot. Submitting for eyeballs and help. Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c A src/mainboard/asus/p8z77-m/mainboard.c 17 files changed, 969 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/1 diff --git a/src/mainboard/asus/p8z77-m/Kconfig b/src/mainboard/asus/p8z77-m/Kconfig new file mode 100644 index 0000000..260597d --- /dev/null +++ b/src/mainboard/asus/p8z77-m/Kconfig @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select SUPERIO_NUVOTON_NCT6779D + +config MAINBOARD_DIR + string + default "asus/p8z77-m" + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-M" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8z77-m/Kconfig.name b/src/mainboard/asus/p8z77-m/Kconfig.name new file mode 100644 index 0000000..a797a5b --- /dev/null +++ b/src/mainboard/asus/p8z77-m/Kconfig.name @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_ASUS_P8Z77_M + bool "P8Z77-M" diff --git a/src/mainboard/asus/p8z77-m/Makefile.inc b/src/mainboard/asus/p8z77-m/Makefile.inc new file mode 100644 index 0000000..a12efbb --- /dev/null +++ b/src/mainboard/asus/p8z77-m/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8z77-m/acpi/ec.asl b/src/mainboard/asus/p8z77-m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-m/acpi/platform.asl b/src/mainboard/asus/p8z77-m/acpi/platform.asl new file mode 100644 index 0000000..d2cad26 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/p8z77-m/acpi/superio.asl b/src/mainboard/asus/p8z77-m/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8z77-m/acpi_tables.c b/src/mainboard/asus/p8z77-m/acpi_tables.c new file mode 100644 index 0000000..9c22f19 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi_tables.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* critical temp that will shutdown the pc == 95C degrees */ + gnvs->tcrt = 95; + + /* temp to start throttling the cpu == 85C */ + gnvs->tpsv = 85; +} diff --git a/src/mainboard/asus/p8z77-m/cmos.default b/src/mainboard/asus/p8z77-m/cmos.default new file mode 100644 index 0000000..725ab98 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/cmos.default @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=224M +nmi=Enable +sata_mode=AHCI +#usb3_xxxx options are only used with MRC blob, ignored else +usb3_mode=Enable +usb3_drv=Enable +usb3_streams=Enable diff --git a/src/mainboard/asus/p8z77-m/cmos.layout b/src/mainboard/asus/p8z77-m/cmos.layout new file mode 100644 index 0000000..da29d1c --- /dev/null +++ b/src/mainboard/asus/p8z77-m/cmos.layout @@ -0,0 +1,185 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# ----------------------------------------------------------------- +# coreboot config options: northbridge + +# gfx_uma_size +# Quantity of shared video memory the IGP can use +# +416 5 e 7 gfx_uma_size + +# ----------------------------------------------------------------- +# coreboot config options: usb3 + +# usb3_mode +# Controls how the motherboard's USB3 ports act at boot time +421 2 e 8 usb3_mode + +# usb3_drv +# Load (or not) pre-OS xHCI USB3 bios driver +# +423 1 e 1 usb3_drv + +# usb3_streams +# Streams can provide more speed (as they can use 64Kb packets), +# but they might cause incompatibilities with some devices. +# +424 1 e 1 usb3_streams + +# ----------------------------------------------------------------- +# Sandy/Ivy Bridge MRC Scrambler Seed values +# note: MUST NOT be covered by checksum! +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk + +# ----------------------------------------------------------------- +# coreboot config options: check sums +544 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +5 0 Disable +5 1 Enable +5 2 Keep + +# sata_mode +6 0 AHCI +6 1 Compatible + +# gfx_uma_size (Intel IGP Video RAM size) +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 544M +7 17 576M +7 18 608M +7 19 640M +7 20 672M +7 21 704M +7 22 736M +7 23 768M +7 24 800M +7 25 832M +7 26 864M +7 27 896M +7 28 928M +7 29 960M +7 30 992M + +# usb3_mode +# Disable = Use the port always as USB 2.0 for compatibility +# Enable = Use the port always as USB 3.0 for speed +# Auto = Initialize the port as USB 2.0, until the OS loads +# xHCI USB 3.0 driver +# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver +# and the computer is reset, keep the USB 3.0 mode. +# +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto + +# ----------------------------------------------------------------- +# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> +# <bit where to start storing checksum[must be 16bits-aligned]> +checksums + +checksum 392 431 544 diff --git a/src/mainboard/asus/p8z77-m/data.vbt b/src/mainboard/asus/p8z77-m/data.vbt new file mode 100644 index 0000000..26ab42d --- /dev/null +++ b/src/mainboard/asus/p8z77-m/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8z77-m/devicetree.cb b/src/mainboard/asus/p8z77-m/devicetree.cb new file mode 100644 index 0000000..03a20b9 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/devicetree.cb @@ -0,0 +1,108 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1043 0x84ca inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "gen4_dec" = "0x00000000" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" # the 4 ports + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 # COM2 address + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.9 off end # GPIO 1-8 + device pnp 2e.a on # ACPI + drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 + drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility + end + device pnp 2e.b off end # HWM, LED + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # GPIO PP/OD + drq 0xe6 = 0x7f # GP7 PP + end + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-m/dsdt.asl b/src/mainboard/asus/p8z77-m/dsdt.asl new file mode 100644 index 0000000..62d44ea --- /dev/null +++ b/src/mainboard/asus/p8z77-m/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8z77-m/early_init.c b/src/mainboard/asus/p8z77-m/early_init.c new file mode 100644 index 0000000..52c0e03 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/early_init.c @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#include <option.h> + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/pei_data.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* {enable, current, oc_pin} */ + { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ + { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ + { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ + { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ + { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ + { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ + { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ + { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ + { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ + { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ + { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ + { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ + { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ + { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ +}; + +/* Global config register values. */ +static const u8 register_values[] = { + /* + * Before accessing CR10, CR11, CR13 and CR14, CR26 [Bit4] must be set to logic 1. + * - NCT6779D datasheet, page 293 + */ + /* reg, value */ + 0x26, (1 << 4), + 0x13, 0xff, /* IRQs 0-15 active low */ + 0x14, 0xff, + 0x1b, 0x60, + 0x22, 0xdf, /* Power down UART B */ + 0x2a, 0x48, /* UART A instead of GPIO8x */ + 0x2c, 0x00, /* PECI */ +}; + +void bootblock_mainboard_early_init(void) +{ + int max = ARRAY_SIZE(register_values); + int i; + + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + + /* Set registers as specified in the register_values[] array. */ + for (i = 0; i < max; i += 2) + pnp_write_config(SERIAL_DEV, register_values[i], register_values[i + 1]); + + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 0); + pnp_set_iobase(SERIAL_DEV, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_enable(SERIAL_DEV, 1); + nuvoton_pnp_exit_conf_state(SERIAL_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* + * USB3 mode: + * 0 = Disable: work always as USB 2.0(ehci) + * 1 = Enable: work always as USB 3.0(xhci) + * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver + * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver + * and reboots, it will keep the USB3.0 speed + */ + int usb3_mode = 1; + get_option(&usb3_mode, "usb3_mode"); + usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ + + /* Load USB3 pre-OS xHCI driver */ + int usb3_drv = 1; + get_option(&usb3_drv, "usb3_drv"); + usb3_drv &= 0x1; /* ensure it's 0/1 only */ + + /* Use USB3 xHCI streams */ + int usb3_streams = 1; + get_option(&usb3_streams, "usb3_streams"); + usb3_streams &= 0x1; /* ensure it's 0/1 only */ + + struct pei_data pd = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ + .dimm_channel0_disabled = 0, /* Both DIMM enabled */ + .dimm_channel1_disabled = 0, /* Both DIMM enabled */ + .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ + .usb_port_config = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 1, 0x0080 }, /* USB3 ETH top connector */ + { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ + { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ + { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ + { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ + }, + .usb3 = { + /* 0=Disable; 1=Enable (start at USB3 speed) + * 2=Auto (start as USB2 speed until OS loads) + * 3=Smart Auto (like Auto but keep speed on reboot) + */ + usb3_mode, + /* 4 bit switch mask. 0=not switchable, 1=switchable + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf + */ + 0xf, + usb3_drv, /* 1=Load xHCI pre-OS drv */ + /* 0=Don't use xHCI streams for better compatibility + * 1=use xHCI streams for better speed + */ + usb3_streams + }, + /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */ + .ddr3lv_support = 1, + /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability ! + */ + .pcie_init = 1, + /* Command Rate. 0=Auto; 1=1N; 2=2N. + * Leave it always at Auto for compatibility & stability + */ + .nmode = 0, + /* DDR refresh rate. 0=Auto based on DRAM's temperature; + * 1=Normal rate for speed; 2=Double rate for stability + */ + .ddr_refresh_rate_config = 0 + }; + + /* copy the data to output PEI */ + *pei_data = pd; +} diff --git a/src/mainboard/asus/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8z77-m/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-m/gpio.c b/src/mainboard/asus/p8z77-m/gpio.c new file mode 100644 index 0000000..03e1507 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/gpio.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-m/hda_verb.c b/src/mainboard/asus/p8z77-m/hda_verb.c new file mode 100644 index 0000000..f240025 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/hda_verb.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x104384a8, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, 0x90430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), + AZALIA_PIN_CFG(0, 0x1e, 0x01446140), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8z77-m/mainboard.c b/src/mainboard/asus/p8z77-m/mainboard.c new file mode 100644 index 0000000..b97b648 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Gerrit-Change-Number: 38988 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

1 month, 2 weeks

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Change in coreboot[master]: inteltool: gemini lake gpio support + UHD 605 graphics detection

by Name of user not set (Code Review)

coreboot(a)s.paape.io has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36033 ) Change subject: inteltool: gemini lake gpio support + UHD 605 graphics detection ...................................................................... inteltool: gemini lake gpio support + UHD 605 graphics detection Signed-off-by: lead4good <coreboot(a)s.paape.io> Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 5 files changed, 317 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36033/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..da4eadd 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1035,6 +1035,7 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_GLK: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..cc1d99e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -45,6 +45,310 @@ * (if it's the first column, GPIO is the default, no matter the name) */ +static const char *const glk_group_northwest_names[] = { + "GPIO_0", "JTAG_TCK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_1", "JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_2", "JTAG_TMS", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_3", "JTAG_TDI", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_4", "JTAG_TDO", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_5", "JTAGX", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_6", "JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_7", "JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_8", "n/a", "n/a", "CNV_DEBUG_09", "CNV_DEBUG_00", "n/a", "n/a", + "GPIO_9", "n/a", "n/a", "CNV_DEBUG_10", "CNV_DEBUG_01", "n/a", "n/a", + "GPIO_10", "n/a", "n/a", "CNV_DEBUG_11", "CNV_DEBUG_02", "n/a", "n/a", + "GPIO_11", "n/a", "n/a", "CNV_DEBUG_12", "CNV_DEBUG_03", "n/a", "n/a", + "GPIO_12", "n/a", "n/a", "CNV_DEBUG_13", "CNV_DEBUG_04", "n/a", "n/a", + "GPIO_13", "n/a", "n/a", "CNV_DEBUG_14", "CNV_DEBUG_05", "n/a", "n/a", + "GPIO_14", "n/a", "n/a", "CNV_DEBUG_15", "CNV_DEBUG_06", "n/a", "n/a", + "GPIO_15", "n/a", "n/a", "CNV_DEBUG_16", "CNV_DEBUG_07", "n/a", "n/a", + "GPIO_16", "n/a", "n/a", "CNV_DEBUG_17", "CNV_DEBUG_08", "n/a", "n/a", + "GPIO_17", "n/a", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "n/a", "n/a", "n/a", + "GPIO_18", "n/a", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "n/a", "n/a", "n/a", + "GPIO_19", "n/a", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "n/a", "n/a", "n/a", + "GPIO_20", "n/a", "CNV_MFUART0_CTS_N", "CNV_DEBUG_03", "n/a", "n/a", "n/a", + "GPIO_21", "n/a", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "n/a", "n/a", "n/a", + "GPIO_22", "n/a", "CNV_MFUART2_TXD", "CNV_DEBUG_05", "n/a", "n/a", "n/a", + "GPIO_23", "n/a", "CNV_GNSS_PA_BLANKING", "CNV_DEBUG_06", "PMIC_STDBY", "n/a", "n/a", + "GPIO_24", "n/a", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "n/a", "n/a", + "GPIO_25", "n/a", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "n/a", "n/a", + "GPIO_26", "n/a", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "n/a", "n/a", + "GPIO_27", "n/a", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "n/a", "n/a", + "GPIO_28", "n/a", "SIO_UART1_RTS_N", "ISH_UART1_RTS_N", "CNV_BT_UART_RTS_N", "n/a", "n/a", + "GPIO_29", "n/a", "SIO_UART1_CTS_N", "ISH_UART1_CTS_N", "CNV_BT_UART_CTS_N", "n/a", "n/a", + "GPIO_30", "n/a", "SATA_GP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_31", "n/a", "SATA_GP1", "n/a", "n/a", "n/a", "n/a", + "GPIO_32", "n/a", "SATA_DE_VSLP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_33", "n/a", "SATA_DE_VSLP1", "SUSCLK1", "n/a", "n/a", "n/a", + "GPIO_34", "n/a", "SATA_LEDN", "SUSCLK2", "n/a", "n/a", "n/a", + "GPIO_35", "n/a", "n/a", "n/a", "SPKR", "n/a", "BSSB_CLK", + "GPIO_36", "n/a", "n/a", "CNV_BTEN", "n/a", "n/a", "BSSB_DI", + "GPIO_37", "n/a", "n/a", "CNV_GNEN", "n/a", "n/a", "n/a", + "GPIO_38", "n/a", "n/a", "CNV_WFEN", "n/a", "n/a", "n/a", + "GPIO_39", "n/a", "n/a", "CNV_WCEN", "n/a", "n/a", "n/a", + "GPIO_40", "n/a", "n/a", "CNVBT_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_41", "n/a", "n/a", "CNV_GNSS_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_42", "MDSI_A_TE", "PWM0", "n/a", "n/a", "n/a", "n/a", + "GPIO_43", "MDSI_C_TE", "PWM1", "n/a", "n/a", "n/a", "n/a", + "GPIO_44", "USB2_OC0_N", "PWM2", "n/a", "n/a", "n/a", "n/a", + "GPIO_45", "USB2_OC1_N", "PWM3", "n/a", "n/a", "n/a", "n/a", + "GPIO_46", "MIPI_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_47", "MIPI_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_48", "PMC_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_49", "PMC_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_50", "SIO_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_51", "SIO_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_52", "SIO_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_53", "SIO_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_54", "SIO_I2C2_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_55", "SIO_I2C2_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_56", "SIO_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_57", "SIO_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_58", "SIO_I2C4_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_59", "SIO_I2C4_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "n/a", "n/a", "n/a", + "GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GNSS_UART_CTS_N", "n/a", "n/a", "n/a", + "GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUART1_RXD", "n/a", "n/a", "n/a", + "GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUART1_TXD", "n/a", "n/a", "n/a", + "GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUART1_RTS_N", "n/a", "n/a", "n/a", + "GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUART1_CTS_N", "n/a", "n/a", "n/a", + "GPIO_68", "PMC_SPI_FS0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_69", "PMC_SPI_FS1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_70", "PMC_SPI_FS2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_71", "PMC_SPI_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_72", "PMC_SPI_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_73", "PMC_SPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_74", "THERMTRIP_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_75", "PROCHOT_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_211","EMMC_RST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_212", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_213", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_214", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_northwest = { + .display = "------- GPIO Group NorthWest -------", + .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7, + .func_count = 7, + .pad_names = glk_group_northwest_names, +}; + +static const struct gpio_group *const glk_community_northwest_groups[] = { + &glk_group_northwest, +}; + +static const struct gpio_community glk_community_northwest = { + .name = "----- GPIO Community NorthWest -----", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(glk_community_northwest_groups), + .groups = glk_community_northwest_groups, +}; + +static const char *const glk_group_north_names[] = { + "GPIO_76", "SVID0_ALERT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_77", "SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "GPIO_78", "SVID0_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "n/a", "n/a", "n/a", + "GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "n/a", "n/a", "n/a", + "GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "n/a", "n/a", + "GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "n/a", "n/a", "n/a", + "GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "n/a", "n/a", "n/a", + "GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "n/a", "n/a", + "GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "n/a", "n/a", + "GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "n/a", "n/a", + "GPIO_87", "SIO_SPI_2_FS2", "n/a", "TOUCH_SPI_D1", "n/a", "n/a", + "GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "n/a", "n/a", + "GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_0_TXD", "TOUCH_SPI_D3", "n/a", "n/a", + "GPIO_90", "FST_SPI_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_91", "FST_SPI_CS1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_92", "FST_SPI_MOSI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPIO_93", "FST_SPI_MISO_IO1", "n/a", "n/a", "n/a", "n/a", + "GPIO_94", "FST_SPI_IO2", "n/a", "n/a", "n/a", "n/a", + "GPIO_95", "FST_SPI_IO3", "n/a", "n/a", "n/a", "n/a", + "GPIO_96", "FST_SPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_97", "FST_SPI_CLK_FB", "n/a", "n/a", "n/a", "n/a", + "GPIO_98", "PMU_PLTRST_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_99", "PMU_PWRBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_100", "PMU_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_101", "PMU_SLP_S3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_102", "PMU_SLP_S4_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_103", "SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a", + "GPIO_104", "EMMC_PWR_EN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_105", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_106", "PMU_BATLOW_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_107", "PMU_RSTBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_108", "PMU_SUSCLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_109", "SUS_STAT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_110", "SIO_I2C5_SDA", "ISH_I2C0_SDA", "n/a", "n/a", "n/a", + "GPIO_111", "SIO_I2C5_SCL", "ISH_I2C0_SCL", "n/a", "n/a", "n/a", + "GPIO_112", "SIO_I2C6_SDA", "ISH_I2C1_SDA", "n/a", "n/a", "n/a", + "GPIO_113", "SIO_I2C6_SCL", "ISH_I2C1_ScL", "n/a", "n/a", "n/a", + "GPIO_114", "SIO_I2C7_SDA", "ISH_I2C2_SDA", "SUSCLK1", "n/a", "n/a", + "GPIO_115", "SIO_I2C7_SCL", "ISH_I2C2_SCL", "SUSCLK2", "n/a", "n/a", + "GPIO_116", "PCIE_WAKE0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_117", "PCIE_WAKE1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_118", "PCIE_WAKE2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_119", "PCIE_WAKE3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_120", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_121", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_122", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_123", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_124", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "n/a", + "GPIO_125", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "n/a", + "GPIO_126", "DDI1_DDC_SDA", "SIO_I2C5_SDA", "n/a", "n/a", "n/a", + "GPIO_127", "DDI1_DDC_SCL", "SIO_I2C5_SCL", "n/a", "n/a", "n/a", + "GPIO_128", "PNL0_VDDEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_129", "PNL0_BKLTEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_130", "PNL0_BKLCTL", "n/a", "n/a", "n/a", "n/a", + "GPIO_131", "DDI0_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_132", "DDI1_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_133", "DDI2_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_134", "n/a", "n/a", "n/a", "ISH_GPIO_10", "n/a", + "GPIO_135", "n/a", "n/a", "n/a", "ISH_GPIO_11", "n/a", + "GPIO_136", "n/a", "n/a", "n/a", "ISH_GPIO_12", "n/a", + "GPIO_137", "n/a", "n/a", "n/a", "ISH_GPIO_13", "n/a", + "GPIO_138", "n/a", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0", + "GPIO_139", "n/a", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1", + "GPIO_140", "n/a", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "n/a", "SATA_DEVSLP0", + "GPIO_141", "n/a", "SIO_UART3_CTS_N", "ISH_UART0_CTS_N", "n/a", "SATA_DEVSLP1", + "GPIO_142", "n/a", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "n/a", "SATA_LEDN", + "GPIO_143", "n/a", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "n/a", + "GPIO_144", "n/a", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "PNL1_VDDEN", "n/a", + "GPIO_145", "n/a", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "PNL1_BKLTEN", "n/a", + "GPIO_146", "n/a", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "PNL1_BKLTCTL", "n/a", + "GPIO_147", "LPC_SERIRQ", "ESPI_RESET_N", "n/a", "n/a", "n/a", + "GPIO_148", "LPC_CLKOUT0", "ESPI_CLK", "n/a", "n/a", "n/a", + "GPIO_149", "LPC_CLKOUT1", "n/a", "n/a", "n/a", "n/a", + "GPIO_150", "LPC_AD0", "ESPI_IO_0", "n/a", "n/a", "n/a", + "GPIO_151", "LPC_AD1", "ESPI_IO_1", "n/a", "n/a", "n/a", + "GPIO_152", "LPC_AD2", "ESPI_IO_2", "n/a", "n/a", "n/a", + "GPIO_153", "LPC_AD3", "ESPI_IO_3", "n/a", "n/a", "n/a", + "GPIO_154", "LPC_CLKRUN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_155", "LPC_FRAME_N", "ESPI_CS_N", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_north = { + .display = "----- GPIO Group North -----", + .pad_count = ARRAY_SIZE(glk_group_north_names) / 6, + .func_count = 6, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_north_groups[] = { + &glk_group_north, +}; + +static const struct gpio_community glk_community_north = { + .name = "--- GPIO Community North ---", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(glk_community_north_groups), + .groups = glk_community_north_groups, +}; + +static const char *const glk_group_audio_names[] = { + "GPIO_156", "AVS_I2S0_MCLK", "n/a", "n/a", + "GPIO_157", "AVS_I2S0_BCLK", "n/a", "n/a", + "GPIO_158", "AVS_I2S0_WS_SYNC", "n/a", "n/a", + "GPIO_159", "AVS_I2S0_SDI", "n/a", "n/a", + "GPIO_160", "AVS_I2S0_SDO", "n/a", "n/a", + "GPIO_161", "AVS_I2S1_MCLK", "n/a", "n/a", + "GPIO_162", "AVS_I2S1_BCLK", "n/a", "CNV_BT_I2S_BCLK", + "GPIO_163", "AVS_I2S1_WS_SYNC", "n/a", "CNV_BT_I2S_WS_SYNC", + "GPIO_164", "AVS_I2S1_SDI", "n/a", "CNV_BT_I2S_SDI", + "GPIO_165", "AVS_I2S1_SDO", "n/a", "CNV_BT_I2S_SDO", + "GPIO_166", "AVS_HDA_BCLK", "AVS_I2S2_BCLK", "n/a", + "GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "n/a", + "GPIO_168", "AVS_HDA_SDI", "AVS_I2S2_SDI", "n/a", + "GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "n/a", + "GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "n/a", + "GPIO_171", "AVS_DMIC_CLK_A1", "n/a", "n/a", + "GPIO_172", "AVS_DMIC_CLK_B1", "n/a", "n/a", + "GPIO_173", "AVS_DMIC_DATA_1", "n/a", "n/a", + "GPIO_174", "AVS_DMIC_CLK_AB2", "n/a", "n/a", + "GPIO_175", "AVS_DMIC_DATA_2", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_audio = { + .display = "----- GPIO Group Audio -----", + .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4, + .func_count = 4, + .pad_names = glk_group_audio_names, +}; + +static const struct gpio_group *const glk_community_audio_groups[] = { + &glk_group_audio, +}; + +static const struct gpio_community glk_community_audio = { + .name = "--- GPIO Community Audio ---", + .pcr_port_id = 0xc9, + .group_count = ARRAY_SIZE(glk_community_audio_groups), + .groups = glk_community_audio_groups, +}; + +static const char *const glk_group_scc_names[] = { + "GPIO_176", "SMB_ALERT_N", "n/a", "n/a", + "GPIO_177", "SMB_CLK", "SIO_I2C7_SCL", "n/a", + "GPIO_178", "SMB_DATA", "SIO_I2C7_SDA", "n/a", + "GPIO_187", "SDCARD_LVL_WP", "n/a", "n/a", + "GPIO_179", "SDCARD_CLK", "n/a", "n/a", + "GPIO_180", "SDCARD_CLK_FB", "n/a", "n/a", + "GPIO_181", "SDCARD_D0", "n/a", "n/a", + "GPIO_182", "SDCARD_D1", "n/a", "n/a", + "GPIO_183", "SDCARD_D2", "n/a", "n/a", + "GPIO_184", "SDCARD_D3", "n/a", "n/a", + "GPIO_185", "SDCARD_CMD", "n/a", "n/a", + "GPIO_186", "SDCARD_CD_N", "n/a", "n/a", + "GPIO_188", "SDCARD_PWR_DWN_N", "n/a", "n/a", + "GPIO_210", "n/a", "n/a", "n/a", + "GPIO_189", "OSC_CLK_OUT_0", "n/a", "n/a", + "GPIO_190", "OSC_CLK_OUT_1", "n/a", "n/a", + "GPIO_191", "CNV_BRI_DT", "n/a", "SIO_UART1_RTS_N", + "GPIO_192", "CNV_BRI_RST", "n/a", "SIO_UART1_RXD", + "GPIO_193", "CNV_RGI_DT", "n/a", "SIO_UART1_TXD", + "GPIO_194", "CNV_RGI_RST", "n/a", "SIO_UART1_CTS_N", + "GPIO_195", "CNV_RF_RESET_N", "n/a", "AVS_I2S1_WS_SYNC", + "GPIO_196", "XTAL_CLKREQ", "n/a", "AVS_I2S1_SDO", + "GPIO_197", "SDIO_CLK_FB", "n/a", "n/a", + "GPIO_198", "EMMC_CLK", "n/a", "n/a", + "GPIO_199", "EMMC_D0", "n/a", "n/a", + "GPIO_200", "EMMC_D1", "n/a", "n/a", + "GPIO_201", "EMMC_D2", "n/a", "n/a", + "GPIO_202", "EMMC_D3", "n/a", "n/a", + "GPIO_203", "EMMC_D4", "n/a", "n/a", + "GPIO_204", "EMMC_D5", "n/a", "n/a", + "GPIO_205", "EMMC_D6", "n/a", "n/a", + "GPIO_206", "EMMC_D7", "n/a", "n/a", + "GPIO_207", "EMMC_CMD", "n/a", "n/a", + "GPIO_208", "EMMC_RCLK", "n/a", "n/a", + "GPIO_209", "EMMC_RST_N", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_scc = { + .display = "----- GPIO Group SCC -----", + .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4, + .func_count = 4, + .pad_names = glk_group_scc_names, +}; + +static const struct gpio_group *const glk_community_scc_groups[] = { + &glk_group_scc, +}; + +static const struct gpio_community glk_community_scc = { + .name = "--- GPIO Community SCC ---", + .pcr_port_id = 0xc8, + .group_count = ARRAY_SIZE(glk_community_scc_groups), + .groups = glk_community_scc_groups, +}; + +static const struct gpio_community *const glk_communities[] = { + &glk_community_northwest, &glk_community_north, + &glk_community_audio, &glk_community_scc, +}; + static const char *const apl_group_north_names[] = { "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -2284,6 +2588,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_GLK: + community_count = ARRAY_SIZE(glk_communities); + communities = glk_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..5aa4592 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -300,6 +300,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ @@ -395,6 +396,8 @@ "Intel(R) HD Graphics 530" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2, "Intel(R) HD Graphics 530" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_605, + "Intel(R) UHD Graphics 605" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1, "Intel(R) UHD Graphics 615" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..9ad1a5f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -264,6 +264,7 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_GLK 0x31e8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc @@ -340,6 +341,7 @@ #define PCI_DEVICE_ID_INTEL_HD_520 0x1916 #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912 +#define PCI_DEVICE_ID_INTEL_UHD_605 0x3185 #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..fec7457 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -120,6 +120,7 @@ p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: + case PCI_DEVICE_ID_INTEL_GLK: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; case PCI_DEVICE_ID_INTEL_H310: -- To view, visit https://review.coreboot.org/c/coreboot/+/36033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401 Gerrit-Change-Number: 36033 Gerrit-PatchSet: 1 Gerrit-Owner: coreboot(a)s.paape.io Gerrit-MessageType: newchange

1 month, 2 weeks

5
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Change in coreboot[master]: soc/intel/xeon_sp: add ACPI to control GPIO [WIP]

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39979 ) Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ...................................................................... soc/intel/xeon_sp: add ACPI to control GPIO [WIP] Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/soc/intel/xeon_sp/acpi/gpio.asl 1 file changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/1 diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl new file mode 100644 index 0000000..4a981b7 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include <soc/gpio.h> + +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 + +Device (GPIO) +{ + Name (_HID, "INT3536") + Name (_UID, 1) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { 0 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + Store (^^PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + Store (^^PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + + CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) + And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG), + GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) + + /* TODO: Check this! + If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { + Store (GPIO_IRQ14, IRQN) + } Else { + Store (GPIO_IRQ15, IRQN) + } + */ + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_F23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 3 */ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_I0, Local1) + } + /* GPIO Community 4 */ + If (LAnd (LGreaterEqual (Arg0, GPP_J0), LLessEqual (Arg0, GPP_K10))) + { + Store (PID_GPIOCOM4, Local0) + Subtract (Arg0, GPP_J0, Local1) + } + /* GPIO Community 5 */ + If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_L19))) + { + Store (PID_GPIOCOM5, Local0) + Subtract (Arg0, GPP_G0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 8))) +} + +/* + * Get GPIO Rx Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Gerrit-Change-Number: 39979 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 month, 3 weeks

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Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib

by Patrick Georgi (Code Review)

Hello Julien Viard de Galbert, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31072 to review the following change. Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib ...................................................................... soc/intel/denverton_ns: Rewrite pmutil using pmclib Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c 4 files changed, 33 insertions(+), 184 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1 diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 09ce158..0aab0e2 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -47,18 +47,6 @@ struct chipset_power_state *fill_power_state(void); /* Power Management Utility Functions. */ -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index ccf0d95..344f8b9 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -19,29 +19,12 @@ #include <arch/io.h> #include <console/console.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static uint32_t print_smi_status(uint32_t smi_sts) +const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { [2] = "BIOS", @@ -67,93 +50,11 @@ [31] = "LEGACY_USB3", }; - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; } -static uint32_t reset_smi_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS)); - outl(smi_sts, (uint16_t)(pmbase + SMI_STS)); - return smi_sts; -} - -uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); } - -void enable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en |= mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void disable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en &= ~mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void enable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt |= mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -void disable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt &= ~mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS)); - outw(pm1_sts, (uint16_t)(pmbase + PM1_STS)); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char *const pm1_sts_bits[] = { - [0] = "TMROF", [4] = "BM", [5] = "GBL", - [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); } - -void enable_pm1(uint16_t events) -{ - uint16_t pmbase = get_pmbase(); - outw(events, (uint16_t)(pmbase + PM1_EN)); -} - -static uint32_t print_tco_status(uint32_t tco_sts) +const char *const *soc_tco_sts_array(size_t *a) { static const char *const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "OS_TCO_SMI", @@ -164,17 +65,11 @@ [17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI", }; - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; } -static uint32_t reset_tco_status(void) +uint32_t soc_reset_tco_status(void) { uint16_t tcobase = get_tcobase(); uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); @@ -184,35 +79,7 @@ return tco_sts & tco_en; } -uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); } - -void enable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_all_gpe(void) { disable_gpe(~0); } - -static uint32_t reset_gpe_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); - return gpe_sts; -} - -static uint32_t print_gpe_sts(uint32_t gpe_sts) +const char *const *soc_std_gpe_sts_array(size_t *a) { static const char *const gpe_sts_bits[] = { [0] = "GPIO_0", [1] = "GPIO_1", @@ -233,16 +100,8 @@ [30] = "GPIO_30", [31] = "GPIO_31", }; - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; } -uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } - void clear_pmc_status(void) { /* TODO */ } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 85f99d7..e1e7bc4 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/pmclib.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -52,7 +53,7 @@ return 0; } -void southbridge_smi_set_eos(void) { enable_smi(EOS); } +void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); } global_nvs_t *smm_get_gnvs(void) { return gnvs; } @@ -98,7 +99,7 @@ uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); + pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); @@ -131,7 +132,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ - disable_all_gpe(); + pmc_disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -145,7 +146,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - enable_pm1_control(SLP_EN); + pmc_enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) @@ -158,7 +159,7 @@ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); + pmc_disable_pm1_control(SLP_EN | SLP_TYP); } } @@ -237,11 +238,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); + pmc_disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); + pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: @@ -268,23 +269,23 @@ static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = clear_pm1_status(); + uint16_t pm1_sts = pmc_clear_pm1_status(); /* While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { // power button pressed - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + pmc_disable_pm1_control(-1UL); + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -static void southbridge_smi_gpe0(void) { clear_gpe_status(); } +static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); } static void southbridge_smi_tco(void) { - uint32_t tco_sts = clear_tco_status(); + uint32_t tco_sts = pmc_clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -354,7 +355,7 @@ /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = clear_smi_status(); + smi_sts = pmc_clear_smi_status(); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 9d3fa75..65d2499 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <string.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -48,10 +49,10 @@ } /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_all_gpe_status(); clear_pmc_status(); } @@ -60,8 +61,8 @@ printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); + pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + pmc_disable_std_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -71,7 +72,7 @@ * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -- To view, visit https://review.coreboot.org/c/coreboot/+/31072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751 Gerrit-Change-Number: 31072 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-MessageType: newchange

1 month, 3 weeks

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Change in coreboot[master]: device/pci: Ensure full 16-bit VGA port i/o decoding

by Nico Huber (Code Review)

Hello Kyösti Mälkki, Patrick Rudolph, Michael Niewöhner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35516 to review the following change. Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding ...................................................................... device/pci: Ensure full 16-bit VGA port i/o decoding So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in random conflicts. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As we don't want to clutter our i/o port space, we'll now simply fail for VGA behind bridges that don't support it. Famous last words: I assume there can't be many bridges left that don't support this bit ;) Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/device.c M src/device/pci_device.c M src/include/device/device.h M src/include/device/pci_def.h 4 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35516/1 diff --git a/src/device/device.c b/src/device/device.c index 44d1f95..523bd1c 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -757,6 +757,12 @@ while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { if (!dev->enabled) continue; + if (dev->bus->no_vga) { + printk(BIOS_WARNING, "Ignoring VGA at %s" + ", a bridge on the path isn't supported", + dev_path(dev)); + continue; + } printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); @@ -797,7 +803,7 @@ while (bus) { printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", dev_path(bus->dev)); - bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; + bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16; bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ecb652..2fadb55 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -788,6 +788,43 @@ }; /** + * Check for compatibility to route legacy VGA cycles through a bridge. + * + * Originally, when decoding i/o ports for legacy VGA cycles, bridges + * should only consider the 10 least significant bits of the port address. + * This means all VGA registers were aliased every 1024 ports! + * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. + * + * To avoid this mess, a bridge control bit (VGA16) was introduced in + * 2003 to enable decoding of 16-bit port addresses. As we don't want + * to clutter our i/o port space, we simply fail for VGA behind bridges + * that don't support it (set .no_vga = 1). + */ +static void pci_bridge_vga_compat(struct bus *const bus) +{ + uint16_t bridge_ctrl; + + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + /* Ensure VGA decoding is disabled during probing (it should + be by default, but we run blobs nowadays) */ + bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + + /* If the upstream bridge doesn't support VGA, we don't have to check */ + bus->no_vga |= bus->dev->bus->no_vga; + if (bus->no_vga) + return; + + /* Test if we can enable 16-bit decoding */ + bridge_ctrl |= PCI_BRIDGE_CTL_VGA16; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + bus->no_vga = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16); +} + +/** * Detect the type of downstream bridge. * * This function is a heuristic to detect which type of bus is downstream @@ -1288,6 +1325,8 @@ bus = dev->link_list; + pci_bridge_vga_compat(bus); + pci_bridge_route(bus, PCI_ROUTE_SCAN); do_scan_bus(bus, 0x00, 0xff); diff --git a/src/include/device/device.h b/src/include/device/device.h index b2221cc..78e234e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -94,6 +94,7 @@ unsigned int reset_needed : 1; unsigned int disable_relaxed_ordering : 1; unsigned int ht_link_up : 1; + unsigned int no_vga : 1; /* We can't support VGA behind this bridge */ }; /* diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..c8b86d5 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -138,6 +138,7 @@ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ /* Fast Back2Back enabled on secondary interface */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Gerrit-Change-Number: 35516 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 month, 3 weeks

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Change in coreboot[master]: soc/intel/apollolake: Make SMI_STS offset macro definition consistent

by Subrata Banik (Code Review)

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39022 ) Change subject: soc/intel/apollolake: Make SMI_STS offset macro definition consistent ...................................................................... soc/intel/apollolake: Make SMI_STS offset macro definition consistent This patch makes all bit field macro definition for SMI_STS register (offset 0x44) be consistent i.e. ending with "_STS_BIT". Also modified relevant files where those macros are getting used. Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/smihandler.c 3 files changed, 52 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39022/1 diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 22e414c..0cf06b2 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -105,29 +105,30 @@ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) #define SMI_STS 0x44 +#define SMI_STS_BITS 32 /* Bits for SMI status */ #define ESPI_SMI_STS_BIT 28 -#define PMC_OCP_SMI_STS 27 -#define SPI_SMI_STS 26 -#define SPI_SSMI_STS 25 -#define SCC2_SMI_STS 21 -#define PCIE_SMI_STS 20 -#define SCS_SMI_STS 19 -#define HSMBUS_SMI_STS 18 -#define XHCI_SMI_STS 17 -#define SMBUS_SMI_STS 16 -#define SERIRQ_SMI_STS 15 -#define PERIODIC_SMI_STS 14 -#define TCO_SMI_STS 13 -#define MC_SMI_STS 12 -#define GPIO_UNLOCK_SMI_STS 11 -#define GPIO_SMI_STS 10 -#define FAKE_PM1_SMI_STS 8 -#define SWSMI_TMR_SMI_STS 6 -#define APM_SMI_STS 5 -#define SLP_SMI_STS 4 -#define LEGACY_USB_SMI_STS 3 -#define BIOS_SMI_STS 2 +#define PMC_OCP_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SPI_SSMI_STS_BIT 25 +#define SCC2_SMI_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SCS_SMI_STS_BIT 19 +#define HSMBUS_SMI_STS_BIT 18 +#define XHCI_SMI_STS_BIT 17 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define MC_SMI_STS_BIT 12 +#define GPIO_UNLOCK_SMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 8151afc..4a08827 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -57,27 +57,27 @@ const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { - [BIOS_SMI_STS] = "BIOS", - [LEGACY_USB_SMI_STS] = "LEGACY USB", - [SLP_SMI_STS] = "SLP_SMI", - [APM_SMI_STS] = "APM", - [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", - [FAKE_PM1_SMI_STS] = "PM1", - [GPIO_SMI_STS] = "GPIO_SMI", - [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI", - [MC_SMI_STS] = "MCSMI", - [TCO_SMI_STS] = "TCO", - [PERIODIC_SMI_STS] = "PERIODIC", - [SERIRQ_SMI_STS] = "SERIRQ", - [SMBUS_SMI_STS] = "SMBUS_SMI", - [XHCI_SMI_STS] = "XHCI", - [HSMBUS_SMI_STS] = "HOST_SMBUS", - [SCS_SMI_STS] = "SCS", - [PCIE_SMI_STS] = "PCI_EXP_SMI", - [SCC2_SMI_STS] = "SCC2", - [SPI_SSMI_STS] = "SPI_SSMI", - [SPI_SMI_STS] = "SPI", - [PMC_OCP_SMI_STS] = "OCP_CSE", + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPIO_STS_BIT] = "GPIO_SMI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", + [MC_SMI_STS_BIT] = "MCSMI", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [XHCI_SMI_STS_BIT] = "XHCI", + [SCS_SMI_STS_BIT] = "HOST_SMBUS", + [SCS_SMI_STS_BIT] = "SCS", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [SCC2_SMI_STS_BIT] = "SCC2", + [SPI_SSMI_STS_BIT] = "SPI_SSMI", + [SPI_SMI_STS_BIT] = "SPI", + [PMC_OCP_SMI_STS_BIT] = "OCP_CSE", }; *a = ARRAY_SIZE(smi_sts_bits); @@ -98,7 +98,7 @@ /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) - generic_sts |= (1 << FAKE_PM1_SMI_STS); + generic_sts |= (1 << PM1_STS_BIT); } return generic_sts; diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..424d66f 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -38,19 +38,19 @@ uint32_t smihandler_soc_get_sci_mask(void) { uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_SMI_STS) | - SMI_HANDLER_SCI_EN(SLP_SMI_STS); + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; } const smi_handler_t southbridge_smi[32] = { - [SLP_SMI_STS] = smihandler_southbridge_sleep, - [APM_SMI_STS] = smihandler_southbridge_apmc, - [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1, - [GPIO_SMI_STS] = smihandler_southbridge_gpi, - [TCO_SMI_STS] = smihandler_southbridge_tco, - [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [TCO_STS_BIT] = smihandler_southbridge_tco, + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Gerrit-Change-Number: 39022 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Convert cbfs.txt to markdown

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33663 Change subject: Documentation: Convert cbfs.txt to markdown ...................................................................... Documentation: Convert cbfs.txt to markdown Convert the document to markdown. Needs to be fixed in a separate commit as it doesn't reflect coreboot v4. Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/lib/cbfs.md M Documentation/lib/index.md 2 files changed, 372 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33663/1 diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md new file mode 100644 index 0000000..83d8b44 --- /dev/null +++ b/Documentation/lib/cbfs.md @@ -0,0 +1,371 @@ +# coreboot CBFS Specification +by Jordan Crouse <jordan(a)cosmicpenguin.net> + +**WARNING: This documentation is written against coreboot v1.** + +**TODO: Update this document ASAP** + +## Introduction + +This document describes the coreboot CBFS specification (from here +referred to as CBFS). CBFS is a scheme for managing independent chunks +of data in a system ROM. Though not a true filesystem, the style and +concepts are similar. + + +## Architecture + +The CBFS architecture looks like the following: + +``` +/---------------\ <-- Start of ROM +| /-----------\ | --| +| | Header | | | +| |-----------| | | +| | Name | | |-- Component +| |-----------| | | +| |Data | | | +| |.. | | | +| \-----------/ | --| +| | +| /-----------\ | +| | Header | | +| |-----------| | +| | Name | | +| |-----------| | +| |Data | | +| |.. | | +| \-----------/ | +| | +| ... | +| /-----------\ | +| | | | +| | Bootblock | | +| | --------- | | +| | Reset | | <- 0xFFFFFFF0 +| \-----------/ | +\---------------/ +``` + +The CBFS architecture consists of a binary associated with a physical +ROM disk referred hereafter as the ROM. A number of independent of +components, each with a header prepended on to data are located within +the ROM. The components are nominally arranged sequentially, though they +are aligned along a pre-defined boundary. + +The bootblock occupies the last 20k of the ROM. Within +the bootblock is a master header containing information about the ROM +including the size, alignment of the components, and the offset of the +start of the first CBFS component within the ROM. + +## Master Header + +The master header contains essential information about the ROM that is +used by both the CBFS implementation within coreboot at runtime as well +as host based utilities to create and manage the ROM. The master header +will be located somewhere within the bootblock (last 20k of the ROM). A +pointer to the location of the header will be located at offset +-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a +normal x86 system. The pointer will be to physical memory somewhere +between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot +to locate the header at run time. Build time utilities will +need to read the pointer and do the appropriate math to locate the header. + +The following is the structure of the master header: + +```c +struct cbfs_header { + u32 magic; + u32 version; + u32 romsize; + u32 bootblocksize; + u32 align; + u32 offset; + u32 architecture; + u32 pad[1]; +} __packed; +``` + +The meaning of each member is as follows: + +`magic` is a 32 bit number that identifies the ROM as a CBFS type. The +magic +number is 0x4F524243, which is 'ORBC' in ASCII. + +`version` is a version number for CBFS header. cbfs_header structure may be +different if version is not matched. + +`romsize` is the size of the ROM in bytes. coreboot will subtract 'size' from +0xFFFFFFFF to locate the beginning of the ROM in memory. + +`bootblocksize` is the size of bootblock reserved in firmware image. + +`align` is the number of bytes that each component is aligned to within the +ROM. This is used to make sure that each component is aligned correctly +with +regards to the erase block sizes on the ROM - allowing one to replace a +component at runtime without disturbing the others. + +`offset` is the offset of the first CBFS component (from the start of +the ROM). This is to allow for arbitrary space to be left at the beginning +of the ROM for things like embedded controller firmware. + +`architecture` describes which architecture (x86, arm, ...) this CBFS is created +for. + +## Bootblock +The bootblock is a mandatory component in the ROM. It is located in the +last 20k of the ROM space, and contains, among other things, the location of the +master header and the entry point for the loader firmware. The bootblock +does not have a component header attached to it. + +## Components + +CBFS components are placed in the ROM starting at 'offset' specified in +the master header and ending at the bootblock. Thus the total size +available for components in the ROM is (ROM size - 20k - 'offset'). +Each CBFS component is to be aligned according to the 'align' value in the +header. +Thus, if a component of size 1052 is located at offset 0 with an 'align' +value of 1024, the next component will be located at offset 2048. + +Each CBFS component will be indexed with a unique ASCII string name of +unlimited size. + +Each CBFS component starts with a header: + +```c +struct cbfs_file { + char magic[8]; + unsigned int len; + unsigned int type; + unsigned int checksum; + unsigned int offset; +}; +``` + +`magic` is a magic value used to identify the header. During runtime, +coreboot will scan the ROM looking for this value. The default magic is +the string 'LARCHIVE'. + +`len` is the length of the data, not including the size of the header and +the size of the name. + +`type` is a 32 bit number indicating the type of data that is attached. +The data type is used in a number of ways, as detailed in the section +below. + +`checksum` is a 32bit checksum of the entire component, including the +header and name. + +`offset` is the start of the component data, based off the start of the +header. +The difference between the size of the header and offset is the size of the +component name. + +Immediately following the header will be the name of the component, +which will null terminated and 16 byte aligned. The following picture shows the +structure of the header: + +``` +/--------\ <- start +| Header | +|--------| <- sizeof(struct cbfs_file) +| Name | +|--------| <- 'offset' +| Data | +| ... | +\--------/ <- start + 'offset' + 'len' +``` + +### Searching Algorithm + +To locate a specific component in the ROM, one starts at the 'offset' +specified in the CBFS master header. For this example, the offset will +be 0. + +From that offset, the code should search for the magic string on the +component, jumping 'align' bytes each time. So, assuming that 'align' is +16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc. +If the offset ever exceeds the allowable range for CBFS components, then no +component was found. + +Upon recognizing a component, the software then has to search for the +specific name of the component. This is accomplished by comparing the +desired name with the string on the component located at +`offset + sizeof(struct cbfs_file)`. If the string matches, then the +component has been located, otherwise the software should add +`'offset' + 'len'` to the offset and resume the search for the magic value. + +### Data Types + +The 'type' member of struct cbfs_file is used to identify the content +of the component data, and is used by coreboot and other +run-time entities to make decisions about how to handle the data. + +There are three component types that are essential to coreboot, and so +are defined here. + +#### Stages + +Stages are code loaded by coreboot during the boot process. They are +essential to a successful boot. Stages are comprised of a single blob +of binary data that is to be loaded into a particular location in memory +and executed. The uncompressed header contains information about how +large the data is, and where it should be placed, and what additional memory +needs to be cleared. + +Stages are assigned a component value of 0x10. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the stage. + +The following is the format of a stage component: + +``` +/--------\ +| Header | +|--------| +| Binary | +| .. | +\--------/ +``` + +The header is defined as: + +```c +struct cbfs_stage { + unsigned int compression; + unsigned long long entry; + unsigned long long load; + unsigned int len; + unsigned int memlen; +}; +``` + +`compression` is an integer defining how the data is compressed. There +are three compression types defined by this version of the standard: +none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional +types may be added assuming that coreboot understands how to handle the scheme. + +`entry` is a 64 bit value indicating the location where the program +counter should jump following the loading of the stage. This should be +an absolute physical memory address. + +`load` is a 64 bit value indicating where the subsequent data should be +loaded. This should be an absolute physical memory address. + +`len` is the length of the compressed data in the component. + +`memlen` is the amount of memory that will be used by the component when +it is loaded. + +The component data will start immediately following the header. + +When coreboot loads a stage, it will first zero the memory from 'load' to +'memlen'. It will then decompress the component data according to the +specified scheme and place it in memory starting at 'load'. Following that, +it will jump execution to the address specified by 'entry'. +Some components are designed to execute directly from the ROM - coreboot +knows which components must do that and will act accordingly. + +#### Payloads + +Payloads are loaded by coreboot following the boot process. + +Stages are assigned a component value of 0x20. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the payload. Furthermore, other run time applications such +as 'bayou' may easily index all available payloads +on the system by searching for the payload type. + + +The following is the format of a stage component: + +``` +/-----------\ +| Header | +| Segment 1 | +| Segment 2 | +| ... | +|-----------| +| Binary | +| .. | +\-----------/ +``` + +The header is as follows: + +```c +struct cbfs_payload { + struct cbfs_payload_segment segments; +} +``` + +The header contains a number of segments corresponding to the segments +that need to be loaded for the payload. + +The following is the structure of each segment header: + +```c +struct cbfs_payload_segment { + unsigned int type; + unsigned int compression; + unsigned int offset; + unsigned long long load_addr; + unsigned int len; + unsigned int mem_len; +}; +``` + +`type` is the type of segment, one of the following: + +```eval_rst ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_CODE | 0x45444F43 | The segment contains executable code | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_DATA | 0x41544144 | The segment contains data | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_BSS | 0x20535342 | The memory specified by the segment | +| | | should be zeroed | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_PARAMS| 0x41524150 | The segment contains information for | +| | | the payload | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_ENTRY | 0x52544E45 | The segment contains the entry point | +| | | for the payload | ++----------------------+-------------+---------------------------------------+ +``` + +`compression` is the compression scheme for the segment. Each segment can +be independently compressed. There are three compression types defined by +this version of the standard: none (0x0), lzma (0x1), and nrv2b +(0x02, deprecated), though additional types may be added assuming that +coreboot understands how to handle the scheme. + +`offset` is the address of the data within the component, starting from +the component header. + +`load_addr` is a 64 bit value indicating where the segment should be placed +in memory. + +`len` is a 32 bit value indicating the size of the segment within the +component. + +`mem_len` is the size of the data when it is placed into memory. + +The data will located immediately following the last segment. + +#### Option ROMS + +The third specified component type will be Option ROMs. Option ROMS will +have component type '0x30'. They will have no additional header, the +uncompressed binary data will be located in the data portion of the +component. + +#### NULL + +There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is +the "don't care" component type. This can be used when the component +type is not necessary (such as when the name of the component is unique. +i.e. option_table). It is recommended that all components be assigned a +unique type, but NULL can be used when the type does not matter. diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md index 99b8061..808bac8 100644 --- a/Documentation/lib/index.md +++ b/Documentation/lib/index.md @@ -6,4 +6,5 @@ ## Structure and layout - [Flashmap and Flashmap Descriptor](flashmap.md) - [ABI data consumption](abi-data-consumption.md) +- [CBFS](cbfs.md) - [Timestamps](timestamp.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/33663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe Gerrit-Change-Number: 33663 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support

by Evgeny Zinoviev (Code Review)

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

2 months

5
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Change in coreboot[master]: trogdor: fix EC/SPI communication after qclib

by mturney mturney (Code Review)

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37482 ) Change subject: trogdor: fix EC/SPI communication after qclib ...................................................................... trogdor: fix EC/SPI communication after qclib Change-Id: Id36ff5f81adb495ad762ce74e224add03520260d Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37482/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 8849911..6b79004 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -20,6 +20,8 @@ #include <timestamp.h> #include <soc/usb.h> #include <soc/qupv3_fw_config.h> +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, @@ -36,6 +38,9 @@ { setup_usb(); qupv3_fw_init(); + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */ + qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */ + } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36ff5f81adb495ad762ce74e224add03520260d Gerrit-Change-Number: 37482 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

2 months, 1 week

3
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Change in coreboot[master]: util/bincfg: Add MAC address example to gbe-ich9m.set

by Evgeny Zinoviev (Code Review)

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39664 ) Change subject: util/bincfg: Add MAC address example to gbe-ich9m.set ...................................................................... util/bincfg: Add MAC address example to gbe-ich9m.set It's not obvious how to set specific byte of a multi-byte field in the set file. Add an example (and a template) for setting MAC address. Change-Id: Iea983071682ffebd61757497d43c70cc8214043d Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M util/bincfg/gbe-ich9m.set 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39664/1 diff --git a/util/bincfg/gbe-ich9m.set b/util/bincfg/gbe-ich9m.set index 01f85ab..9c5515e 100644 --- a/util/bincfg/gbe-ich9m.set +++ b/util/bincfg/gbe-ich9m.set @@ -84,5 +84,13 @@ "ssdid" = 0x20ee, "ssvid" = 0x17aa, "did" = 0x10f5, - "vid" = 0x8086 + "vid" = 0x8086, + + # MAC address + "macaddress0" = 0, + "macaddress1" = 0, + "macaddress2" = 0, + "macaddress3" = 0, + "macaddress4" = 0, + "macaddress5" = 0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/39664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea983071682ffebd61757497d43c70cc8214043d Gerrit-Change-Number: 39664 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

2 months, 1 week

5
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coreboot-gerrit March 2020