Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )
Change subject: mainboard/ocp: Add support for OCP platform TiogaPass ......................................................................
Patch Set 25:
(4 comments)
Thanks for the review, Andrey,
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... File src/mainboard/ocp/tiogapass/board.fmd:
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... PS24, Line 8: MISC_RW
we do not have RO here, everything is RW. […]
We will have RO_VPD in future, to store stuffs like default configurations.
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... File src/mainboard/ocp/tiogapass/emmc.h:
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... PS24, Line 18: #ifndef _MAINBOARD_EMMC_H : #define _MAINBOARD_EMMC_H : : #include <fsp/util.h> : : /* : * eMMC DLL structure for EMMC DLL registers settings : */ : typedef struct { : UINT32 TxCmdCntl; : UINT32 TxDataCntl1; : UINT32 TxDataCntl2; : UINT32 RxCmdDataCntl1; : UINT32 RxStrobeCntl; : UINT32 RxCmdDataCntl2; : UINT32 MasterSwCntl; : } BL_EMMC_DLL_CONFIG; : : typedef struct { : UINT16 Signature; : BL_EMMC_DLL_CONFIG eMMCDLLConfig; : } BL_EMMC_INFORMATION; : : #define DEFAULT_EMMC_DLL_SIGN 0x55aa : : #ifndef __ACPI__ : BL_EMMC_INFORMATION tiogapass_emmc_config[] = { : /* : * Default eMMC DLL configuration. : */ : {DEFAULT_EMMC_DLL_SIGN, : {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a, : 0x00010013, 0x00000001} } }; : #endif : : #endif /* _MAINBOARD_EMMC_H */
there is no eMMC on Tioga Pass
Done
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... File src/mainboard/ocp/tiogapass/romstage.c:
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... PS24, Line 24: #define PCH_SERVER_BIOS_FLAG 1
again I do not think it make sense to have this flag
We can take care of this in future work.
https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... PS24, Line 37: mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table; : mupd->FspmConfig.GpioConfig.NumberOfEntries = : sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
So on this board we have C62x PCH. What are the SKL-H macros? […]
Those are GPIO configurations. We should discuss with Intel so that current generation Xeon-SP FSP does not do it.