SeaBIOS

seabios@seabios.org

3783 discussions

How CPU executes bios code before copying bios to shadow ram?
by Li Wang 26 Jul '16

26 Jul '16

Hi all, I am reading seaBios code, and I have a question about the shadow memory copy part. In fw/shadow.c:make_bios_writable_intel() reads pam0 to see if shadow memory is already readable (if pam0's fourth bit is set), if pam0 shows shadow memory is not readable running __make_bios_writable_intel from high-memory flash location (statements marked green below). But in my understanding the entry point of bios is 0xffff:fff0, then it jumps to 0xf000:e05b, which points to memory space in shadowing, but before __make_bios_writable_intel copying bios from high-memory flash to shadow memory, shadow memory is disabled, so these codes are forwarded to high-memory flash, including code to read pam0 before invoking __make_bios_writable_intel (statement marked red below). Why these codes are not relocate to high-memory flash, but only the invocation of __make_bios_writable_intel is need to be relocated? If shadow ram is present and readable, how cpu execute bios codes in 0xf000:xxxx before copying them to shadow ram? 60 static void 61 make_bios_writable_intel(u16 bdf, u32 pam0) 62 { 63 int reg = pci_config_readb(bdf, pam0); 64 if (!(reg & 0x10)) { 65 // QEMU doesn't fully implement the piix shadow capabilities - 66 // if ram isn't backing the bios segment when shadowing is 67 // disabled, the code itself won't be in memory. So, run the 68 // code from the high-memory flash location. 69 u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET; 70 void (*func)(u16 bdf, u32 pam0) = (void*)pos; 71 func(bdf, pam0); 72 return; 73 } 74 // Ram already present - just enable writes 75 __make_bios_writable_intel(bdf, pam0); 76 } Thanks

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[PATCH 0/3] tpm: Extend PCRs in all available PCR banks
by Stefan Berger 21 Jul '16

21 Jul '16

This series of patches extends the TPM2 code to extend the BIOS related PCRs 0-7 in all available banks. This prevents that these PCRs remain untouched and filled with bogus values by applications. For example, the SHA1 hash is extended into the SHA256 bank. The value that is extended into this bank is essentially a SHA1 with zero bytes used for filling it to the size of a sha256 hash. This is done for all PCR banks of the TPM2 where these PCRs are available. Regards, Stefan Stefan Berger (3): tpm: Retrieve the PCR Bank configuration tpm: Restructure tpm20_extend to use buffer and take hash as parameter tpm: Extend tpm20_extend to support extending to multiple PCR banks src/std/tcg.h | 45 +++++++++++++-- src/tcgbios.c | 175 +++++++++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 201 insertions(+), 19 deletions(-) -- 2.5.5

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[PATCH] restore MSRs on S3 resume
by Paolo Bonzini 13 Jul '16

13 Jul '16

Currently the MTRRs and MSR_IA32_FEATURE_CONTROL are not restored on S3 resume. Because these have to be applied to all processors, SMP setup has to be added to S3 resume. There are two differences between the boot and resume paths. First, romfile_* is not usable in the resume paths so we move the call out of smp_setup and into a new function smp_boot_setup. Second, smp_msr has to be walked on the BSP as well, so we extract that out of handle_smp and into a new function smp_write_msrs. Then, resume can call smp_write_msrs on the BSP followed by smp_setup to initialize the APs. Reported-by: Laszlo Ersek <lersek(a)redhat.com> Signed-off-by: Paolo Bonzini <pbonzini(a)redhat.com> --- src/fw/paravirt.c | 1 + src/fw/smp.c | 28 +++++++++++++++++++++++----- src/resume.c | 1 + src/util.h | 2 ++ 4 files changed, 27 insertions(+), 5 deletions(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index e8e419e..9189672 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -160,6 +160,7 @@ qemu_platform_setup(void) // Initialize mtrr, msr_feature_control and smp mtrr_setup(); msr_feature_control_setup(); + smp_boot_setup(); smp_setup(); // Create bios tables diff --git a/src/fw/smp.c b/src/fw/smp.c index 6e706e4..64e76b6 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -46,6 +46,15 @@ int apic_id_is_present(u8 apic_id) return !!(FoundAPICIDs[apic_id/32] & (1ul << (apic_id % 32))); } +static void +smp_write_msrs(void) +{ + // MTRR and MSR_IA32_FEATURE_CONTROL setup + int i; + for (i=0; i<smp_msr_count; i++) + wrmsr(smp_msr[i].index, smp_msr[i].val); +} + void VISIBLE32FLAT handle_smp(void) { @@ -58,10 +67,7 @@ handle_smp(void) u8 apic_id = ebx>>24; dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id); - // MTRR and MSR_IA32_FEATURE_CONTROL setup - int i; - for (i=0; i<smp_msr_count; i++) - wrmsr(smp_msr[i].index, smp_msr[i].val); + smp_write_msrs(); // Set bit on FoundAPICIDs FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32)); @@ -73,6 +79,12 @@ handle_smp(void) u32 SMPLock __VISIBLE; u32 SMPStack __VISIBLE; +void +smp_boot_setup(void) +{ + MaxCountCPUs = romfile_loadint("etc/max-cpus", 0); +} + // find and initialize the CPUs by launching a SIPI to them void smp_setup(void) @@ -141,10 +153,16 @@ smp_setup(void) // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; - MaxCountCPUs = romfile_loadint("etc/max-cpus", 0); if (!MaxCountCPUs || MaxCountCPUs < CountCPUs) MaxCountCPUs = CountCPUs; dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", CountCPUs, MaxCountCPUs); } + +void +smp_resume(void) +{ + smp_write_msrs(); + smp_setup(); +} diff --git a/src/resume.c b/src/resume.c index a5465d8..3a26f84 100644 --- a/src/resume.c +++ b/src/resume.c @@ -97,6 +97,7 @@ s3_resume(void) pic_setup(); smm_setup(); + smp_resume(); pci_resume(); diff --git a/src/util.h b/src/util.h index cba3359..510da73 100644 --- a/src/util.h +++ b/src/util.h @@ -131,7 +131,9 @@ void smm_setup(void); // fw/smp.c extern u32 MaxCountCPUs; void wrmsr_smp(u32 index, u64 val); +void smp_boot_setup(void); void smp_setup(void); +void smp_resume(void); int apic_id_is_present(u8 apic_id); // hw/dma.c -- 1.8.3.1

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Re: [SeaBIOS] GeodeVGA is not initialized during SeaBIOS execution
by Kevin O'Connor 13 Jul '16

13 Jul '16

On Mon, Jul 11, 2016 at 08:25:14PM +0300, Andrey Korolyov wrote: > Awesome suggestion, turns out that the PCI_COMMAND_IO is not set. > Removing the check entirely would lead to an incomplete PCI > initialization but placing VGA ROM to vgaroms/seavgabios.rom could do > the trick. So, out of curiosity, does Geode SeaVGABIOS work on this board if one of the above is done? I haven't seen a recent confirmation that Geode SeaVGABIOS still works. -Kevin

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Re: [SeaBIOS] GeodeVGA is not initialized during SeaBIOS execution
by Kevin O'Connor 12 Jul '16

12 Jul '16

On Mon, Jul 11, 2016 at 02:23:12AM +0300, Andrey Korolyov wrote: > Hi, > > as per Kevin`s suggestion, I am posting initialization log (mixed one) > from initialization of the GeodeLX board. As it could be clearly seen > from the log, VGA option ROM was never called and executed during the > initialization sequence, therefore issue with a lack of video output > during SeaBIOS stage on this board looks somehow logical. [1] suggests > that the problem existed long before, as most users of these boards > are Alix owners who do not care about existence of the video output :) Best guess is this check: u16 cmd = pci_config_readw(pci->bdf, PCI_COMMAND); if (!(cmd & PCI_COMMAND_IO && cmd & PCI_COMMAND_MEMORY)) return 0; in optionroms.c:is_pci_vga() is being triggered. You could see if coreboot is not enabling these PCI flags, temporarily disable the check in seabios, or use "vgaroms/seavgabios.rom" instead of "pci1022,2081.rom" for the seavgabios rom. -Kevin

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GeodeVGA is not initialized during SeaBIOS execution
by Andrey Korolyov 11 Jul '16

11 Jul '16

Hi, as per Kevin`s suggestion, I am posting initialization log (mixed one) from initialization of the GeodeLX board. As it could be clearly seen from the log, VGA option ROM was never called and executed during the initialization sequence, therefore issue with a lack of video output during SeaBIOS stage on this board looks somehow logical. [1] suggests that the problem existed long before, as most users of these boards are Alix owners who do not care about existence of the video output :) [1]. https://www.coreboot.org/pipermail/seabios/2012-February/003186.html

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[PATCH 1/3] vgabios: Remove special case of dh==0xff in handle_1013()
by Kevin O'Connor 08 Jul '16

08 Jul '16

The original "lgpl vgabios" had a special case for dh==0xff in its int1013 (write string) code. There does not appear to be any VGABIOS documentation supporting this as an externally available feature. It appears this was for its own internal use when writing its strings to the screen. SeaVGABIOS doesn't use this hack; this patch removes it from the code. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/vgabios.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index f07e85b..8b50192 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -1030,13 +1030,7 @@ handle_1012(struct bregs *regs) static void noinline handle_1013(struct bregs *regs) { - struct cursorpos cp; - if (regs->dh == 0xff) - // if row=0xff special case : use current cursor position - cp = get_cursor_pos(regs->bh); - else - cp = (struct cursorpos) {regs->dl, regs->dh, regs->bh}; - + struct cursorpos cp = {regs->dl, regs->dh, regs->bh}; u16 count = regs->cx; u8 *offset_far = (void*)(regs->bp + 0); u8 attr = regs->bl; -- 2.5.5

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[PATCH v3] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL
by Haozhong Zhang 07 Jul '16

07 Jul '16

OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file "etc/msr_feature_control" to advise bits that should be set in MSR_IA32_FEATURE_CONTROL. If this file exists, SeaBIOS will set the advised bits in that MSR. Signed-off-by: Haozhong Zhang <haozhong.zhang(a)intel.com> Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com> --- Changes in v3: * Move msr_feature_control_setup() to paravirt.c. Changes in v2: * Call msr_feature_control_setup() before smp_setup(). * Use wrmsr_smp() instead of wrmsr() on BSP. * Rename smp_mtrr and smp_mtrr_count to smp_msr and smp_msr_count as they are not only used for MTRR now. --- src/fw/paravirt.c | 12 +++++++++++- src/fw/smp.c | 20 ++++++++++---------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 8ed4380..73a08f0 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -131,6 +131,15 @@ qemu_preinit(void) dprintf(1, "RamSize: 0x%08x [cmos]\n", RamSize); } +#define MSR_IA32_FEATURE_CONTROL 0x0000003a + +static void msr_feature_control_setup(void) +{ + u64 feature_control_bits = romfile_loadint("etc/msr_feature_control", 0); + if (feature_control_bits) + wrmsr_smp(MSR_IA32_FEATURE_CONTROL, feature_control_bits); +} + void qemu_platform_setup(void) { @@ -149,8 +158,9 @@ qemu_platform_setup(void) smm_device_setup(); smm_setup(); - // Initialize mtrr and smp + // Initialize mtrr, msr_feature_control and smp mtrr_setup(); + msr_feature_control_setup(); smp_setup(); // Create bios tables diff --git a/src/fw/smp.c b/src/fw/smp.c index 579acdb..6e706e4 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -10,7 +10,7 @@ #include "output.h" // dprintf #include "romfile.h" // romfile_loadint #include "stacks.h" // yield -#include "util.h" // smp_setup +#include "util.h" // smp_setup, msr_feature_control_setup #include "x86.h" // wrmsr #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) @@ -20,20 +20,20 @@ #define APIC_ENABLED 0x0100 -static struct { u32 index; u64 val; } smp_mtrr[32]; -static u32 smp_mtrr_count; +static struct { u32 index; u64 val; } smp_msr[32]; +static u32 smp_msr_count; void wrmsr_smp(u32 index, u64 val) { wrmsr(index, val); - if (smp_mtrr_count >= ARRAY_SIZE(smp_mtrr)) { + if (smp_msr_count >= ARRAY_SIZE(smp_msr)) { warn_noalloc(); return; } - smp_mtrr[smp_mtrr_count].index = index; - smp_mtrr[smp_mtrr_count].val = val; - smp_mtrr_count++; + smp_msr[smp_msr_count].index = index; + smp_msr[smp_msr_count].val = val; + smp_msr_count++; } u32 MaxCountCPUs; @@ -58,10 +58,10 @@ handle_smp(void) u8 apic_id = ebx>>24; dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id); - // MTRR setup + // MTRR and MSR_IA32_FEATURE_CONTROL setup int i; - for (i=0; i<smp_mtrr_count; i++) - wrmsr(smp_mtrr[i].index, smp_mtrr[i].val); + for (i=0; i<smp_msr_count; i++) + wrmsr(smp_msr[i].index, smp_msr[i].val); // Set bit on FoundAPICIDs FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32)); -- 2.9.0

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Re: [SeaBIOS] Issues building SeaBIOS with gcc > 4.8
by Roger Pau Monné 07 Jul '16

07 Jul '16

On Tue, Jul 05, 2016 at 11:23:36PM +0200, Idwer Vollering wrote: > 2016-07-05 15:49 GMT+02:00 Roger Pau Monné <roger.pau(a)citrix.com>: > > Hello, > > > > I'm seeing the following issue when building SeaBIOS with gcc > 4.8: > > > > (..) > > > > > This works fine when using gcc 4.8, but fails in the same way with gcc 5.4. > > The assembler version used is: > > > > GNU assembler version 2.25.1 (x86_64-portbld-freebsd11.0) using BFD version (GNU Binutils) 2.25.1 > > > > What causes this issue seems to be the usage of the "-m16" gcc flag, which > > was introduced in gcc 4.9 AFAICT. The following workaround solves the issue, > > but I would like to know if anyone else has seen this with newer gcc > > versions, or if the gcc version from FreeBSD ports is broken. > > Are you experiencing issues on hardware too? As in: coreboot.rom for > the mainboard asus/f2a85-m built on FreeBSD 11.0-ALPHA5 r302302, > without gcc installed from 'pkg', with the coreboot crossgcc toolchain > will not boot. Oh, I'm sorry but I've never used coreboot (or SeaBIOS) on real hardware, I only use it for Xen, so I cannot provide much feedback. All I can say is that SeaBIOS compiled with gcc 4.8 from FreeBSD ports works fine inside of Xen VMs. Roger.

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Issues building SeaBIOS with gcc > 4.8
by Roger Pau Monné 07 Jul '16

07 Jul '16

Hello, I'm seeing the following issue when building SeaBIOS with gcc > 4.8: Compiling whole program out/ccode32flat.o Compiling whole program out/code32seg.o Compiling whole program out/ccode16.o /tmp//ccecsJuF.s: Assembler messages: /tmp//ccecsJuF.s:539: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:545: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:966: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:1484: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:1813: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:1922: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:2626: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:2632: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:2793: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:3050: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:3056: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:3387: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:3649: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:3829: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:4111: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:4620: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:4626: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:5538: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:5544: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:6140: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:6146: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7186: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7192: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7376: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7382: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7732: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7799: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:7805: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:8001: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:8007: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:8932: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:10170: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:10176: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:10919: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:10925: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:11315: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:11321: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:11824: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:11830: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:12337: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:12343: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:12523: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:12647: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:12653: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:13019: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:13535: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:13671: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:13677: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:14363: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:14369: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:14862: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:14962: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:14968: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:15297: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:15303: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:15854: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:15860: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:16243: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:16249: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:16445: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:16451: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:16814: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:16820: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:17392: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:17503: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:17613: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:17706: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:17712: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:18306: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:18312: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:18450: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:18456: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:18802: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:18808: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:19122: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:19128: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:19372: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:19378: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:19692: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:19698: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:20491: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:20497: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:20603: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:20609: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:21003: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:21009: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:21658: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:21958: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:22162: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:22633: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:22848: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:22854: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:24399: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:24405: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:25008: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:25014: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:25412: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:26448: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:26454: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:27363: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:27597: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:27686: Error: register save offset not a multiple of 8 /tmp//ccecsJuF.s:27692: Error: register save offset not a multiple of 8 Makefile:154: recipe for target 'out/ccode16.o' failed gmake: *** [out/ccode16.o] Error 1 This works fine when using gcc 4.8, but fails in the same way with gcc 5.4. The assembler version used is: GNU assembler version 2.25.1 (x86_64-portbld-freebsd11.0) using BFD version (GNU Binutils) 2.25.1 What causes this issue seems to be the usage of the "-m16" gcc flag, which was introduced in gcc 4.9 AFAICT. The following workaround solves the issue, but I would like to know if anyone else has seen this with newer gcc versions, or if the gcc version from FreeBSD ports is broken. Thanks, Roger. --- diff --git a/Makefile b/Makefile index 4930b3a..19a1e7d 100644 --- a/Makefile +++ b/Makefile @@ -73,8 +73,7 @@ CFLAGSSEG := $(COMMONCFLAGS) -DMODESEGMENT=1 -fno-defer-pop \ $(call cc-option,$(CC),-fno-jump-tables,-DMANUAL_NO_JUMP_TABLE) \ $(call cc-option,$(CC),-fno-tree-switch-conversion,) CFLAGS32SEG := $(CFLAGSSEG) -DMODE16=0 -CFLAGS16 := $(CFLAGSSEG) -DMODE16=1 \ - $(call cc-option,$(CC),-m16,-Wa$(COMMA)src/code16gcc.s) \ +CFLAGS16 := $(CFLAGSSEG) -DMODE16=1 -Wa$(COMMA)src/code16gcc.s \ $(call cc-option,$(CC),--param large-stack-frame=4,-fno-inline) # Run with "make V=1" to see the actual compile commands

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