QEMU provides two fw_cfg files to support IGD. The first holds the
OpRegion data which holds the Video BIOS Table (VBT). This needs to
be copied into reserved memory and the address stored in the ASL
Storage register of the device at 0xFC offset in PCI config space.
The OpRegion is generally 8KB. This file is named "etc/igd-opregion".
The second file tells us the required size of the stolen memory space
for the device. This is a dummy file, it has no backing so we only
allocate the space without copying anything into it. This space
requires 1MB alignment and is generally either 1MB or 2MB, depending
on the hardware config. If the user has opted in QEMU to expose
additional stolen memory beyond the GTT (GGMS), the GMS may add an
additional 32MB to 512MB. The base address of the reserved memory
allocated for this is written back to the Base Data of Stolen Memory
register (BDSM) at PCI config offset 0x5C on the device. This file is
named "etc/igd-bdsm".
Signed-off-by: Alex Williamson <alex.williamson(a)redhat.com>
---
v4: Back to a single patch thanks to Kevin's suggestion to use
memalign_tmphigh() for larger allocations. Now creating
reserved space for stolen memory and writing the value to
the BDSM register is queued off the existence of a fw_cfg
file, just like the OpRegion. The only difference is that
we don't copy the contents, just use the meta data.
src/fw/pciinit.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 0ed5dfb..dc2e433 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -269,6 +269,49 @@ static void ich9_smbus_setup(struct pci_device *dev, void *arg)
pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
}
+static void intel_igd_setup(struct pci_device *dev, void *arg)
+{
+ struct romfile_s *opregion = romfile_find("etc/igd-opregion");
+ struct romfile_s *bdsm = romfile_find("etc/igd-bdsm");
+ void *addr;
+ u16 bdf = dev->bdf;
+
+ if (opregion && opregion->size) {
+ addr = memalign_high(PAGE_SIZE, opregion->size);
+ if (!addr) {
+ warn_noalloc();
+ return;
+ }
+
+ if (opregion->copy(opregion, addr, opregion->size) < 0) {
+ free(addr);
+ return;
+ }
+
+ pci_config_writel(bdf, 0xFC, cpu_to_le32((u32)addr));
+
+ dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev "
+ "%02x:%02x.%x\n", (u32)addr, opregion->size >> 10,
+ pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
+ }
+
+ if (bdsm && bdsm->size) {
+ addr = memalign_tmphigh(1024 * 1024, bdsm->size);
+ if (!addr) {
+ warn_noalloc();
+ return;
+ }
+
+ e820_add((u32)addr, bdsm->size, E820_RESERVED);
+
+ pci_config_writel(bdf, 0x5C, cpu_to_le32((u32)addr));
+
+ dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %dMB, dev "
+ "%02x:%02x.%x\n", (u32)addr, bdsm->size >> 20,
+ pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
+ }
+}
+
static const struct pci_device_id pci_device_tbl[] = {
/* PIIX3/PIIX4 PCI to ISA bridge */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
@@ -302,6 +345,10 @@ static const struct pci_device_id pci_device_tbl[] = {
PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
+ /* Intel IGD OpRegion setup */
+ PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
+ intel_igd_setup),
+
PCI_DEVICE_END,
};
Hello,
I have a need to access 32 bit address space from within a 16 bit option ROM I'm writing. As a test I added code to load the gdt as required to set up 32 bit protected mode but I've encountered a problem. Below are my code and gdt structures. My issue is that when the ljmp is executed the model reboots (this is running on seabios under Qemu). I suspect a GP violation but can't seem to put my finger on it. I tried defining an idt containing a handler that hangs (i.e. jmp .) but was never successful in seeing that work.
Does anyone have ideas for why this won't work? Could the Qemu environment restrict this?
Thanks.
Bob
--------------------------------------------
go_to_32bit_protected_mode:
cli
cld
lgdtw %cs:opRom_gdt_32
movl %cr0, %eax
orl $1, %eax
movl %eax, %cr0
ljmp $MODE32_CS_SEL, $pmode
.code32
pmode:
movl $MODE32_DS_SEL, %eax
movl $16, %eax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %fs
movw %ax, %gs
sti
ret
// 32 bit protected mode GDT descriptors
opRom_gdt_32_descs_start:
.quad 0x0
.quad 0x00CF9B000000FFFF
.quad 0x00CF93000000FFFF
.quad 0x00CFFA000000FFFF
.quad 0x00CFF2000000FFFF
opRom_gdt_32_descs_end:
opRom_gdt_32:
.word (opRom_gdt_32_descs_end - opRom_gdt_32_descs_start) - 1
.long opRom_gdt_32_descs_start
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Hi Stefan,
What do you think about something like these two patches in place of
your last patch 10? Basically using 'struct tcg_pcr_event2_sha1'
instead of introducing a new 'struct log_entry'.
-Kevin
Kevin O'Connor (2):
tpm: Unify tpm_fill_hash()/tpm_log_extend_event() and use in BIOS
interface
tpm: Write logs in TPM 2 format
src/std/tcg.h | 35 ++++++++++++++
src/tcgbios.c | 145 +++++++++++++++++++++++++++++++++++++++-------------------
2 files changed, 133 insertions(+), 47 deletions(-)
--
2.5.0
On Thu, Feb 25, 2016 at 10:02:34AM -0800, Dustin Brazeau wrote:
> As far as I can tell SeaBIOS does not currently support keyboard input over
> serial. I was wondering if there is an unofficial patch that could add
> support for this before I start looking into implementing it myself. Thanks.
For traditional serial ports, sgabios generally fills that role. See
the SeaBIOS coreboot wiki for info on sgabios:
http://www.coreboot.org/SeaBIOS#Adding_sgabios_support
-Kevin
As far as I can tell SeaBIOS does not currently support keyboard input over
serial. I was wondering if there is an unofficial patch that could add
support for this before I start looking into implementing it myself. Thanks.
According to the output from readelf, the .text section should be aligned to
16:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] (null) NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 000de300 000300 021d00 00 AX 0 0 16
[...]
This however doesn't seem to be enforced when the relocations are generated.
The following patch tries to address this by making sure the space used for
the relocations it also aligned to the same value as the .text section.
Signed-off-by: Roger Pau Monné <roger.pau(a)citrix.com>
Reported by: Ed Maste <emaste(a)FreeBSD.org>
---
Cc: Kevin O'Connor <kevin(a)koconnor.net>
---
scripts/layoutrom.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/layoutrom.py b/scripts/layoutrom.py
index b976fb0..5534a9e 100755
--- a/scripts/layoutrom.py
+++ b/scripts/layoutrom.py
@@ -397,7 +397,7 @@ def writeLinkerScripts(li, out16, out32seg, out32flat):
+ strRelocs("_reloc_rel", "code32init_start", relrelocs)
+ strRelocs("_reloc_init", "code32flat_start", initrelocs))
numrelocs = len(absrelocs + relrelocs + initrelocs)
- sec32all_start -= numrelocs * 4
+ sec32all_start -= alignpos(numrelocs * 4, li.sec32low_align)
filesections32flat = getSectionsFileid(li.sections, '32flat')
out = outXRefs([], exportsyms=li.varlowsyms
, forcedelta=li.final_sec32low_start-li.sec32low_start)
--
2.5.4 (Apple Git-61)
On Mon, Feb 15, 2016 at 12:00:48PM +0000, Zeh, Werner wrote:
> Hi Kevin.
>
> We had some issues with some connected AHCI devices in SeaBIOS. We
> have connected some CF-Cards by using a simple SATA<->IDE bridge to
> the mainboard and in some cases, the drive (which is the CF-card)
> was not recognized correctly. After some deeper analysis we found
> that SeaBIOS does not set up the transfer rate which is used to
> communicate to the drive. The supported transfer rate can be found
> in the data structure which is delivered by IDENTIFY_DEVICE command.
>
> So in our error cases the default transfer rate was too high and
> therefore data error has occurred. I have attached a patch which
> will deal with this case on AHCI controllers. Maybe you can push
> this patch to mainline or at least have a look at it.
>
> Up to now I have verified the function of this patch with the latest
> master branch of SeaBIOS and a Broadwell-DE CPU. I have used PIO4,
> default PIO, Multiword-DMA2 and several Ultra-DMA CF-cards to ensure
> that all three paths work properly.
>
> BTW: I am not that familiar with code style in SeaBIOS. If I made
> some formal mistakes, feel free to correct them.
Thanks. I'm not that familiar with the AHCI internals. Gerd, would
you be able to review?
-Kevin
Greetings
I am currently trying to compile Seabios for Arch Linux ARM and I've
encountered an error during the compilation that appears to be caused by
a misconfiguration in the file downloaded from here:
http://code.coreboot.org/p/seabios/downloads/get/seabios-1.9.0.tar.gz
I have attached a log containing the entire stdout and stderr stream
output for Arch Linux's makepkg command but I think these might be the
only lines of interest:
Compile checking out/src/misc.o
cc -Iout/ -Isrc -Os -MD -g -Wall -Wno-strict-aliasing
-Wold-style-definition -Wtype-limits -m32 -march=i386 -mregparm=3
-mpreferred-stack-boundary=2 -minline-all-stringops -fomit-frame-pointer
-freg-struct-return -ffreestanding -fno-delete-null-pointer-checks
-ffunction-sections -fdata-sections -fno-common -fno-merge-constants
-fno-stack-protector -fstack-check=no -DMODE16=0 -DMODESEGMENT=0 -c
src/misc.c -o out/src/misc.o
cc: error: unrecognized argument in option '-march=i386'
cc: note: valid arguments to '-march=' are: armv2 armv2a armv3 armv3m
armv4 armv4t armv5 armv5e armv5t armv5te armv6 armv6-m armv6j armv6k
armv6s-m armv6t2 armv6z armv6zk armv7 armv7-a armv7-m armv7-r armv7e-m
armv7ve armv8-a armv8-a+crc iwmmxt iwmmxt2 native
cc: error: unrecognized command line option '-m32'
cc: error: unrecognized command line option '-mregparm=3'
cc: error: unrecognized command line option '-mpreferred-stack-boundary=2'
cc: error: unrecognized command line option '-minline-all-stringops'
Makefile:133: recipe for target 'out/src/misc.o' failed
The files Arch Linux uses to compile Seabios can be found here if
needed:
https://projects.archlinux.org/svntogit/packages.git/tree/trunk?h=packages/…
Can anyone help me get this error fixed? If a developer reads this and
there is a bug in the code, would it be possible to fix it? Help will be
greatly appreciated.
Kind regards
Xavier de Rauville
