This series enables seabios to run on some Baytrail CPU based
chromebooks. At least some of these machines do not support routing
of legacy interrupts and at least some have SDHCI controllers that do
not appear as regular PCI devices. This series is mainly a hack to
get some minimal support on the hardware.
This series is also available at:
https://github.com/KevinOConnor/seabios/tree/baytrail-testing
-Kevin
Kevin O'Connor (3):
Add minimal support for machines without hardware interrupts
ps2: Eliminate "etc/ps2-poll-only"; use CONFIG_HARDWARE_IRQ instead
sdcard: Allow sdcard addresses to be specified in CBFS files
docs/Runtime_config.md | 2 +-
src/Kconfig | 13 ++++++++++++-
src/clock.c | 31 +++++++++++++++++++++++++------
src/hw/pic.c | 14 ++++++++++++++
src/hw/pic.h | 4 ++++
src/hw/ps2port.c | 16 ++++++----------
src/hw/sdcard.c | 48 ++++++++++++++++++++++++++++++++++++------------
src/hw/timer.c | 2 ++
src/stacks.c | 5 ++++-
src/util.h | 1 +
10 files changed, 105 insertions(+), 31 deletions(-)
--
1.9.3
Document the existence of the EXTRAVERSION field and the information
expected to be present in it.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
docs/Build_overview.md | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/docs/Build_overview.md b/docs/Build_overview.md
index 26db226..ac38694 100644
--- a/docs/Build_overview.md
+++ b/docs/Build_overview.md
@@ -52,6 +52,21 @@ CSM_ENABLE'. The SeaBIOS binary will be included as a discrete file
within the 'Flash Volume' which is created, and there are tools which
will extract it and allow it to be replaced.
+Distribution builds
+===================
+
+If one is building a binary version of SeaBIOS as part of a package
+(such as an rpm) or for wide distribution, please provide the
+EXTRAVERSION field during the build. For example:
+
+`make EXTRAVERSION="-${RPM_PACKAGE_RELEASE}"`
+
+The EXTRAVERSION field should provide the package version (if
+applicable) and the name of the distribution (if that's not already
+obvious from the package version). This string will be appended to the
+main SeaBIOS version. The above information helps SeaBIOS developers
+correlate defect reports to the source code and build environment.
+
Overview of files in the repository
===================================
--
2.4.3
This patch series changes the SeaBIOS build to no longer permit one to
provide a custom version string via "make VERSION=xyz". In its place
the build will allow extra information to be added to the standard
version string via a new "EXTRAVERSION" variable. For example: "make
EXTRAVERSION=-coreboot"
In order to facilitate "reproducible" builds, this patch series also
changes the build to no longer include the system hostname nor build
time on default "clean" builds. Specifically, if git is available,
the git repo is not in a "dirty" state, and gcc/binutils versions are
successfully extracted, then the default version string will just
contain the git version information. However, should any of the
preceding tests not succeed, then the version will continue to include
the hostname and build time.
-Kevin
Kevin O'Connor (3):
build: Rework version generation; don't allow make version override
build: Report gcc and binutils versions in debug log
build: Generate "reproducible" version strings on "clean" builds
Makefile | 16 ++++----
scripts/buildversion.py | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
scripts/buildversion.sh | 31 --------------
src/output.c | 1 +
src/util.h | 2 +-
src/version.c | 5 +++
vgasrc/vgainit.c | 1 +
vgasrc/vgaversion.c | 6 +++
8 files changed, 130 insertions(+), 39 deletions(-)
create mode 100644 scripts/buildversion.py
delete mode 100755 scripts/buildversion.sh
create mode 100644 src/version.c
create mode 100644 vgasrc/vgaversion.c
--
2.4.3
Implementation of the FW CFG DMA interface.
When running a Linux guest on top of QEMU, using the -kernel option and with
fw_cfg DMA Linux boot support, this is the timing improvement for x86:
Original QEMU and SeaBIOS
QEMU startup time: .080
BIOS startup time: .060
Kernel setup time: .586
Total time: .726
QEMU and SeaBIOS with this patch series and fw_cfg DMA Linux boot support
QEMU startup time: .080
BIOS startup time: .039
Kernel setup time: .005
Total time: .126
QEMU startup time is the time between the start and the first kvm_entry.
BIOS startup time is the time between the first kvm_entry and the start of
function do_boot, in SeaBIOS.
Kernel setup time is the time between the start of the function do_boot in
SeaBIOS and the jump to the Linux kernel.
As you can see, both the BIOS (because of ACPI tables and other configurations)
and the Linux kernel boot (because of the copy to memory) are greatly
improved with this new interface.
Also, this new interface is an addon to the old interface. Both interfaces
are compatible and interchangeable.
Changes from v1:
- Take into account order of fields in the FWCfgDmaAccess structure
- Check and change endianness of FWCfgDmaAccess fields
- Change order of fields in the FWCfgDmaAccess structure
- Add FW_CFG_DMA_CTL_SKIP feature for control field
- Split FW_CFG_SIZE in QEMU
- Make FW_CFG_ID a bitmap of features
- Add 64 bit address support for the transfer. Trigger when writing the low
address, and address is 0 by default and at the end of each transfer.
- Align ports and addresses.
- Preserve old fw_cfg_comb_valid behaviour in QEMU
- Update documentation to reflect all these changes
Changes from v2:
- Make IOports fw_cfg DMA region a different IO region.
- Reuse everything for MMIO and IOport DMA regions
- Make transfer status only based on control field
- Use DMA helpers instead of direct map/unmap
- Change ARM fw_cfg DMA address space
- Change Linux boot process to match linuxboot.S
- Add select capabilities in the FWCfgDmaAccess struct
- Update documentation to reflect all these changes
Changes from v3:
- Set properly fw_cfg DMA fields in ARM
- Set fw_cfg DMA boot process properly (by Laszlo Ersek)
- Add signature to fw_cfg DMA address field (by Kevin O'Connor)
- Minor nitpicks
Changes from v4:
- Remove Linux fw_cfg boot from this series (will be sent separately)
- Minor nitpicks
Hi Bin,
On 10 October 2015 at 02:57, Bin Meng <bmeng.cn(a)gmail.com> wrote:
> Hi Simon,
>
> On Sat, Oct 3, 2015 at 10:29 PM, Simon Glass <sjg(a)chromium.org> wrote:
>> Hi Bin,
>>
>> On 29 September 2015 at 11:17, Bin Meng <bmeng.cn(a)gmail.com> wrote:
>>> SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
>>> It can run in an emulator or natively on X86 hardware with the
>>> use of coreboot. With SeaBIOS's help, we can boot some OSes
>>> that require 16-bit BIOS services like Windows/DOS.
>>>
>>> As U-Boot, we have to manually create a table where SeaBIOS gets
>>> system information (eg: E820) from. The table unfortunately has
>>> to follow the coreboot table format as SeaBIOS currently supports
>>> booting as a coreboot payload. No U-Boot native support there.
>>>
>>> Booting SeaBIOS is done via U-Boot's bootelf command.
>>>
>>> This is the initial attempt to support booting SeaBIOS from U-Boot.
>>> If the basic concept is good, I can spend time working on follow-on
>>> patches to enable BIOS tables as well as graphics support. One issue
>>> is that U-Boot x86 does not has a ROM file system like coreboot.
>>> This brings difficulities to pass PCI option ROM to SeaBIOS, if we
>>> don't modify SeaBIOS's source codes. Maybe we should promote CBFS
>>> in U-Boot x86?
>>>
>>> This is tested on an Intel Crown Bay board with VGA card, booting
>>> SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel
>>> finally.
>>
>> Looks good to me. I think it is OK to use CBFS if needed - are you
>> thinking of an option to build u-boot.rom as a CBFS filesystem?
>
> If using CBFS, that means we may have to abandon ifdtool? Or maybe
> mixed usage of both tools?
So far I'm not sure of the best approach. At present we have the ROM
offsets stored mostly in Kconfig, with the MRC area in the SPI flash
device tree node. The environment is also in Kconfig.
What sort of option ROMs do you want to support? What other options
does seabios provide?
What does SEA stand for?
[snip]
Regards,
Simon
I think it would be good to schedule the next SeaBIOS release
(v1.9.0). I think the first week of November (Nov 6th) would be a
good target date for a release.
There are a couple of pending features that I would like to see go
into the next release:
- the fw_cfg dma interface. (Hopefully the fw_cfg dma interface will
be accepted into QEMU in the next week or two so that it could make
the next SeaBIOS release.)
- remove the "make VERSION=xyz" version override, and replace it with
a standard version string that is more "reproducible" than the
current identifier. (I hope to send some patches that implement a
revised seabios version identifier later this week.)
Are there any other features or bug fixes that should be addressed
prior to the next release?
-Kevin
Hi Simon,
On Sat, Oct 3, 2015 at 10:29 PM, Simon Glass <sjg(a)chromium.org> wrote:
> Hi Bin,
>
> On 29 September 2015 at 11:17, Bin Meng <bmeng.cn(a)gmail.com> wrote:
>> SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
>> It can run in an emulator or natively on X86 hardware with the
>> use of coreboot. With SeaBIOS's help, we can boot some OSes
>> that require 16-bit BIOS services like Windows/DOS.
>>
>> As U-Boot, we have to manually create a table where SeaBIOS gets
>> system information (eg: E820) from. The table unfortunately has
>> to follow the coreboot table format as SeaBIOS currently supports
>> booting as a coreboot payload. No U-Boot native support there.
>>
>> Booting SeaBIOS is done via U-Boot's bootelf command.
>>
>> This is the initial attempt to support booting SeaBIOS from U-Boot.
>> If the basic concept is good, I can spend time working on follow-on
>> patches to enable BIOS tables as well as graphics support. One issue
>> is that U-Boot x86 does not has a ROM file system like coreboot.
>> This brings difficulities to pass PCI option ROM to SeaBIOS, if we
>> don't modify SeaBIOS's source codes. Maybe we should promote CBFS
>> in U-Boot x86?
>>
>> This is tested on an Intel Crown Bay board with VGA card, booting
>> SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel
>> finally.
>
> Looks good to me. I think it is OK to use CBFS if needed - are you
> thinking of an option to build u-boot.rom as a CBFS filesystem?
If using CBFS, that means we may have to abandon ifdtool? Or maybe
mixed usage of both tools?
>
>>
>> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com>
>>
>> ---
>>
>> arch/x86/Kconfig | 10 ++++++++++
>> arch/x86/include/asm/tables.h | 29 +++++++++++++++++++++++++++++
>> arch/x86/lib/tables.c | 39 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 78 insertions(+)
>>
>> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
>> index 5e42d7d..b432ff8 100644
>> --- a/arch/x86/Kconfig
>> +++ b/arch/x86/Kconfig
>> @@ -401,6 +401,16 @@ config PCIE_ECAM_SIZE
>> so a default 0x10000000 size covers all of the 256 buses which is the
>> maximum number of PCI buses as defined by the PCI specification.
>>
>> +config SEABIOS
>> + bool "Support booting SeaBIOS"
>> + help
>> + SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
>> + It can run in an emulator or natively on X86 hardware with the use
>> + of coreboot/U-Boot. By turning on this option, U-Boot prepares
>> + all the configuration tables that are necessary to boot SeaBIOS.
>> +
>> + Check http://www.seabios.org/SeaBIOS for details.
>> +
>> source "arch/x86/lib/efi/Kconfig"
>>
>> endmenu
>> diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
>> index 0aa6d9b..a083cac 100644
>> --- a/arch/x86/include/asm/tables.h
>> +++ b/arch/x86/include/asm/tables.h
>> @@ -7,6 +7,32 @@
>> #ifndef _X86_TABLES_H_
>> #define _X86_TABLES_H_
>>
>> +#ifdef CONFIG_SEABIOS
>> +
>> +#define CB_TAG_MEMORY 1
>> +
>> +struct cb_header {
>> + u8 signature[4];
>> + u32 header_bytes;
>> + u32 header_checksum;
>> + u32 table_bytes;
>> + u32 table_checksum;
>> + u32 table_entries;
>> +};
>> +
>> +struct cb_memory_range {
>> + u64 start;
>> + u64 size;
>> + u32 type;
>> +};
>> +
>> +struct cb_memory {
>> + u32 tag;
>> + u32 size;
>> + struct cb_memory_range map[0];
>> +};
>> +#endif
>> +
>> /*
>> * All x86 tables happen to like the address range from 0xf0000 to 0x100000.
>> * We use 0xf0000 as the starting address to store those tables, including
>> @@ -14,6 +40,9 @@
>> */
>> #define ROM_TABLE_ADDR 0xf0000
>>
>> +/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
>> +#define CB_TABLE_ADDR 0x800
>> +
>> /**
>> * table_compute_checksum() - Compute a table checksum
>> *
>> diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
>> index f15b2e2..5849b2f 100644
>> --- a/arch/x86/lib/tables.c
>> +++ b/arch/x86/lib/tables.c
>> @@ -9,6 +9,7 @@
>> #include <asm/mpspec.h>
>> #include <asm/tables.h>
>> #include <asm/acpi_table.h>
>> +#include <asm/e820.h>
>>
>> u8 table_compute_checksum(void *v, int len)
>> {
>> @@ -36,6 +37,41 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad)
>> dest[i] = pad;
>> }
>>
>> +#ifdef CONFIG_SEABIOS
>> +static u32 write_cb_tables(u32 addr)
>> +{
>> + struct cb_header *cbh = (struct cb_header *)addr;
>> + struct cb_memory *mem;
>> + struct cb_memory_range *map;
>> + struct e820entry entry[32];
>> + int num, i;
>> +
>> + memset(cbh, 0, sizeof(struct cb_header));
>> + strncpy((char *)cbh->signature, "LBIO", 4);
>
> memcpy()?
Yes.
>
>> + cbh->header_bytes = sizeof(struct cb_header);
>> +
>> + /* populate memory map table */
>> + mem = (struct cb_memory *)(cbh + 1);
>> + mem->tag = CB_TAG_MEMORY;
>> + map = mem->map;
>> + num = install_e820_map(32, entry);
>
> ARRAY_SIZE(entry)
Yes
>
>> + for (i = 0; i < num; i++) {
>> + map->start = entry[i].addr;
>> + map->size = entry[i].size;
>> + map->type = entry[i].type;
>> + map++;
>> + }
>> + mem->size = num * sizeof(struct cb_memory_range) + 8;
>
> What is 8?
It's sizeof(struct cb_memory) - sizeof(struct cb_memory_range)
>
>> +
>> + cbh->table_bytes = mem->size;
>> + cbh->table_checksum = compute_ip_checksum(mem, cbh->table_bytes);
>> + cbh->table_entries = 1;
>> + cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes);
>> +
>> + return (u32)map;
>> +}
>> +#endif
>> +
>> void write_tables(void)
>> {
>> u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR;
>> @@ -56,4 +92,7 @@ void write_tables(void)
>> rom_table_end = write_acpi_tables(rom_table_end);
>> rom_table_end = ALIGN(rom_table_end, 1024);
>> #endif
>> +#ifdef CONFIG_SEABIOS
>> + write_cb_tables(CB_TABLE_ADDR);
>> +#endif
>> }
>> --
Regards,
Bin
Signed-off-by: Stefan Weil <sw(a)weilnetz.de>
---
scripts/kconfig/lxdialog/util.c | 2 +-
src/Kconfig | 2 +-
src/biosvar.h | 2 +-
src/bmp.c | 2 +-
src/fw/shadow.c | 2 +-
src/hw/pci_regs.h | 2 +-
src/misc.c | 2 +-
src/sha1.c | 4 ++--
src/std/LegacyBios.h | 4 ++--
src/std/bda.h | 2 +-
src/string.c | 2 +-
src/types.h | 2 +-
src/vgahooks.c | 2 +-
vgasrc/geodevga.h | 2 +-
14 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/scripts/kconfig/lxdialog/util.c b/scripts/kconfig/lxdialog/util.c
index f7abdeb..2a0d182 100644
--- a/scripts/kconfig/lxdialog/util.c
+++ b/scripts/kconfig/lxdialog/util.c
@@ -376,7 +376,7 @@ void print_title(WINDOW *dialog, const char *title, int width)
/*
* Print a string of text in a window, automatically wrap around to the
* next line if the string is too long to fit on one line. Newline
- * characters '\n' are propperly processed. We start on a new line
+ * characters '\n' are properly processed. We start on a new line
* if there is no room for at least 4 nonblanks following a double-space.
*/
void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x)
diff --git a/src/Kconfig b/src/Kconfig
index b873cd3..95bf087 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -20,7 +20,7 @@ choice
Configure for an emulated machine (QEMU, Xen, KVM, or Bochs).
config CSM
- bool "Build as Compatibilty Support Module for EFI BIOS"
+ bool "Build as Compatibility Support Module for EFI BIOS"
help
Configure to be used by EFI firmware as Compatibility Support
module (CSM) to provide legacy BIOS services.
diff --git a/src/biosvar.h b/src/biosvar.h
index 58bcbce..3b40957 100644
--- a/src/biosvar.h
+++ b/src/biosvar.h
@@ -12,7 +12,7 @@
/****************************************************************
- * Interupt vector table
+ * Interrupt vector table
****************************************************************/
#define GET_IVT(vector) \
diff --git a/src/bmp.c b/src/bmp.c
index d8e76b7..96a2b3f 100644
--- a/src/bmp.c
+++ b/src/bmp.c
@@ -1,6 +1,6 @@
/*
* Basic BMP data process and Raw picture data handle functions.
-* Could be used to adjust pixel data format, get infomation, etc.
+* Could be used to adjust pixel data format, get information, etc.
*
* Copyright (C) 2011 Wayne Xia <xiawenc(a)cn.ibm.com>
*
diff --git a/src/fw/shadow.c b/src/fw/shadow.c
index 4f00006..936ae28 100644
--- a/src/fw/shadow.c
+++ b/src/fw/shadow.c
@@ -65,7 +65,7 @@ make_bios_writable_intel(u16 bdf, u32 pam0)
if (!(reg & 0x10)) {
// QEMU doesn't fully implement the piix shadow capabilities -
// if ram isn't backing the bios segment when shadowing is
- // disabled, the code itself wont be in memory. So, run the
+ // disabled, the code itself won't be in memory. So, run the
// code from the high-memory flash location.
u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET;
void (*func)(u16 bdf, u32 pam0) = (void*)pos;
diff --git a/src/hw/pci_regs.h b/src/hw/pci_regs.h
index e5effd4..f7a455d 100644
--- a/src/hw/pci_regs.h
+++ b/src/hw/pci_regs.h
@@ -221,7 +221,7 @@
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
-#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
+#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
diff --git a/src/misc.c b/src/misc.c
index 8caaf31..f02237c 100644
--- a/src/misc.c
+++ b/src/misc.c
@@ -56,7 +56,7 @@ void VISIBLE16
handle_10(struct bregs *regs)
{
debug_enter(regs, DEBUG_HDL_10);
- // dont do anything, since the VGA BIOS handles int10h requests
+ // don't do anything, since the VGA BIOS handles int10h requests
}
// NMI handler
diff --git a/src/sha1.c b/src/sha1.c
index 352114f..2ecb3cb 100644
--- a/src/sha1.c
+++ b/src/sha1.c
@@ -33,7 +33,7 @@ sha1_block(u32 *w, sha1_ctx *ctx)
static const u32 sha_ko[4] = {
0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 };
- /* change endianess of given data */
+ /* change endianness of given data */
for (i = 0; i < 16; i++)
w[i] = be32_to_cpu(w[i]);
@@ -120,7 +120,7 @@ sha1_do(sha1_ctx *ctx, const u8 *data32, u32 length)
sha1_block(w, ctx);
- /* need to switch result's endianess */
+ /* need to switch result's endianness */
for (num = 0; num < 5; num++)
ctx->h[num] = cpu_to_be32(ctx->h[num]);
}
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h
index 5170c37..e0c40d6 100644
--- a/src/std/LegacyBios.h
+++ b/src/std/LegacyBios.h
@@ -219,7 +219,7 @@ typedef struct {
/// value of the start of the PCI Express memory-mapped configuration registers and
/// must be filled in prior to EfiCompatibility code issuing the Compatibility16 function
/// Compatibility16InitializeYourself().
- /// Compatibility16InitializeYourself() is defined in Compatability16
+ /// Compatibility16InitializeYourself() is defined in Compatibility16
/// Functions.
///
UINT32 PciExpressBase;
@@ -252,7 +252,7 @@ typedef struct {
///
/// Functions provided by the CSM binary which communicate between the EfiCompatibility
-/// and Compatability16 code.
+/// and Compatibility16 code.
///
/// Inconsistent with the specification here:
/// The member's name started with "Compatibility16" [defined in Intel Framework
diff --git a/src/std/bda.h b/src/std/bda.h
index c321266..4ad6605 100644
--- a/src/std/bda.h
+++ b/src/std/bda.h
@@ -7,7 +7,7 @@
/****************************************************************
- * Interupt vector table
+ * Interrupt vector table
****************************************************************/
struct rmode_IVT {
diff --git a/src/string.c b/src/string.c
index 2e4e437..adb8198 100644
--- a/src/string.c
+++ b/src/string.c
@@ -227,7 +227,7 @@ strtcpy(char *dest, const char *src, size_t len)
return dest;
}
-// locate first occurance of character c in the string s
+// locate first occurrence of character c in the string s
char *
strchr(const char *s, int c)
{
diff --git a/src/types.h b/src/types.h
index 097372c..19d9f6c 100644
--- a/src/types.h
+++ b/src/types.h
@@ -70,7 +70,7 @@ extern void __force_link_error__only_in_16bit(void) __noreturn;
# define VARFSEG __section(".discard.varfseg." UNIQSEC) __VISIBLE __weak
// Designate a variable at a specific address in the f-segment.
# define VARFSEGFIXED(addr) __section(".discard.varfixed." UNIQSEC) __VISIBLE __weak
-// Verify a variable is only accessable via 32bit "init" functions
+// Verify a variable is only accessible via 32bit "init" functions
# define VARVERIFY32INIT __section(".discard.varinit." UNIQSEC)
// Designate top-level assembler as 16bit only.
# define ASM16(code) __ASM(code)
diff --git a/src/vgahooks.c b/src/vgahooks.c
index 6a4acfe..48efb08 100644
--- a/src/vgahooks.c
+++ b/src/vgahooks.c
@@ -124,7 +124,7 @@ getAMDRamSpeed(void)
/* int 0x15 - 5f18
- ECX = unknown/dont care
+ ECX = unknown/don't care
EBX[3..0] Frame Buffer Size 2^N MiB
EBX[7..4] Memory speed:
0: SDR 66Mhz
diff --git a/vgasrc/geodevga.h b/vgasrc/geodevga.h
index 61d7808..c99f54b 100644
--- a/vgasrc/geodevga.h
+++ b/vgasrc/geodevga.h
@@ -2,7 +2,7 @@
//
// Copyright (C) 2009 Chris Kindt
//
-// Writen for Google Summer of Code 2009 for the coreboot project
+// Written for Google Summer of Code 2009 for the coreboot project
//
// This file may be distributed under the terms of the GNU LGPLv3 license.
--
2.1.4
