[SEABIOS] Plans for either 1.9.1 or 1.10.0?
by Ian Campbell
Hello,
The xen.git development branch currently points to SeaBIOS rel-1.9.0, but
Roger has tripped over a build issue which is fixed by 3b8c5378dfe2 "build:
fix typo in buildversion.py".
Is there any plan for either a 1.9.1 or a 1.10.0 in the near future which
would include this, so I can roll forward to that?
Or if not a 1.9.1 release perhaps for now just a 1.9-stable branch could be
created?
No problem if not, we'll just track master for a bit until there is a
release.
Thanks,
Ian.
3 years, 3 months
[PATCH v2 00/10] Add TPM 2 support
by Stefan Berger
This series of patches adds TPM 2 support to SeaBIOS in the way previously
proposed.
v1->v2:
- Addressed most of Kevin's comments.
- Added patch for writing logs in TPM 2 format
Stefan
Stefan Berger (10):
tpm: Extend TPM TIS with TPM 2 support.
tpm: Factor out tpm_extend
tpm: Prepare code for TPM 2 functions
tpm: Implement tpm20_startup and tpm20_s3_resume
tpm: Implement tpm20_set_timeouts
tpm: Implement tpm20_prepboot
tpm: Implement tpm20_extend
tpm: Implement tpm20_menu
tpm: Implement TPM 2's set_failure
tpm: Write logs in TPM 2 format
src/hw/tpm_drivers.c | 38 ++-
src/hw/tpm_drivers.h | 26 +-
src/std/tcg.h | 145 +++++++++
src/tcgbios.c | 890 +++++++++++++++++++++++++++++++++++++++++++--------
4 files changed, 955 insertions(+), 144 deletions(-)
--
2.4.3
3 years, 3 months
[PATCH] Fix comment typo
by Cao jin
Signed-off-by: Cao jin <caoj.fnst(a)cn.fujitsu.com>
---
src/fw/pciinit.c | 2 +-
src/fw/pirtable.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index c31c2fa..6b1c902 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -274,7 +274,7 @@ static const struct pci_device_id pci_device_tbl[] = {
PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
storage_ide_setup),
- /* PIC, IBM, MIPC & MPIC2 */
+ /* PIC, IBM, MPIC & MPIC2 */
PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
pic_ibm_setup),
PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
diff --git a/src/fw/pirtable.c b/src/fw/pirtable.c
index a494408..bf8c047 100644
--- a/src/fw/pirtable.c
+++ b/src/fw/pirtable.c
@@ -66,7 +66,7 @@ static struct pir_table PIR_TABLE = {
},
.slot_nr = 3,
}, {
- // 5th slot entry: 4rd PCI slot
+ // 5th slot entry: 4th PCI slot
.dev = 5<<3,
.links = {
{.link = 0x60, .bitmap = 0xdef8}, // INTA#
@@ -76,7 +76,7 @@ static struct pir_table PIR_TABLE = {
},
.slot_nr = 4,
}, {
- // 6th slot entry: 5rd PCI slot
+ // 6th slot entry: 5th PCI slot
.dev = 6<<3,
.links = {
{.link = 0x61, .bitmap = 0xdef8}, // INTA#
--
2.1.0
3 years, 3 months
[PATCH] fix comment typo in __make_bios_writable_intel()
by Cao jin
Signed-off-by: Cao jin <caoj.fnst(a)cn.fujitsu.com>
---
src/fw/shadow.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/fw/shadow.c b/src/fw/shadow.c
index bdb5c5b..dcf1137 100644
--- a/src/fw/shadow.c
+++ b/src/fw/shadow.c
@@ -25,7 +25,7 @@
static void
__make_bios_writable_intel(u16 bdf, u32 pam0)
{
- // Make ram from 0xc0000-0xf0000 writable
+ // Make ram from 0xc0000-0xf0000 writable/readable
int clear = 0;
int i;
for (i=0; i<6; i++) {
@@ -45,7 +45,7 @@ __make_bios_writable_intel(u16 bdf, u32 pam0)
if (clear)
memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
- // Make ram from 0xf0000-0x100000 writable
+ // Make ram from 0xf0000-0xfffff writable
int reg = pci_config_readb(bdf, pam0);
pci_config_writeb(bdf, pam0, 0x30);
if (reg & 0x10)
--
2.1.0
3 years, 3 months
SeaBIOS NVMe support
by vladislav.vovchenko＠sk.com
Hi, guys!
I wanna try to add NVMe support for SeaBIOS. But I have a problem: all addresses passed to NVMe ctrl (for example: queue addresses in ACQ and ASQ registers) are treated by controller as IO (not RAM).
Qemu 2.5.0: file exec.c: address_space_rw(): function memory_access_is_direct() returns false, but should be true. Am I missing smth, or it's special behaviour of SeaBios?
Have a nice day!
Best Regards,
Vladislav.
3 years, 3 months
Re: [SeaBIOS] Repeat of Query
by Kevin O'Connor
On Wed, Jan 27, 2016 at 08:05:38PM +0000, Eli Duttman wrote:
> Nothing has come my way, regarding my initial query. I'd appreciate a response, even if it is in the negative.
>
>
> I'm sorry my skills rate to be of zero help with the project. I can read a little C and dabbled with x86 assembler years ago. Nothing of consequence there.
>
>
> I'm an IBM mainframe CICS system programmer, with over 40 years of experience. If, by some chance, solid mainframe assembler and decent COBOL skills can be of use, I'd be delighted to pitch in.
>
> ________________________________
> From: Eli Duttman <eduttman(a)hotmail.com>
> Sent: Sunday, January 17, 2016 2:00 PM
> To: seabios(a)seabios.org
> Subject: Very Old Machines
>
> SeaBIOS seems to be a possibility for the ancient ISA bus machine
> reactivation project I have begun. What's currently in ROM lacks
> INT 13H extension support and is not Y2K compliant. When last used
> in the early 2000s, entering a 2nnn year seemed to be OK. An EEPROM
> is not present and any "load" would have to burned into 1 or more
> EPROMs.
>
> TIA, for any replies.
I'm not sure I understand what your question is.
The SeaBIOS code should run on any machine with a 386 or later.
However, machines have specific initialization sequences (such as
configuring the memory controller) and SeaBIOS does not implement that
at all - that is the role of the coreboot project. Given the age of
the machines you are working with, I suspect it will be very difficult
to figure out the low level details of the machine initialization.
-Kevin
3 years, 3 months
Repeat of Query
by Eli Duttman
Nothing has come my way, regarding my initial query. I'd appreciate a response, even if it is in the negative.
I'm sorry my skills rate to be of zero help with the project. I can read a little C and dabbled with x86 assembler years ago. Nothing of consequence there.
I'm an IBM mainframe CICS system programmer, with over 40 years of experience. If, by some chance, solid mainframe assembler and decent COBOL skills can be of use, I'd be delighted to pitch in.
Eli D.
________________________________
From: Eli Duttman <eduttman(a)hotmail.com>
Sent: Sunday, January 17, 2016 2:00 PM
To: seabios(a)seabios.org
Subject: Very Old Machines
SeaBIOS seems to be a possibility for the ancient ISA bus machine reactivation project I have begun. What's currently in ROM lacks INT 13H extension support and is not Y2K compliant. When last used in the early 2000s, entering a 2nnn year seemed to be OK. An EEPROM is not present and any "load" would have to burned into 1 or more EPROMs.
TIA, for any replies.
Eli D.
3 years, 3 months
[PATCH] Support for booting from LSI Logic LSI53C1030, SAS1068, SAS1068e
by Paolo Bonzini
From: Don Slutz <Don.Slutz(a)Gmail.com>
Also known as Fusion MPT disk; this controller model is supported
by VirtualBox and VMware, and QEMU support patches have been
posted.
Signed-off-by: Don Slutz <Don.Slutz(a)Gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini(a)redhat.com>
---
Makefile | 2 +-
src/Kconfig | 6 ++
src/block.c | 3 +
src/block.h | 1 +
src/hw/mpt-scsi.c | 307 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
src/hw/mpt-scsi.h | 8 ++
src/post.c | 2 +
7 files changed, 328 insertions(+), 1 deletion(-)
create mode 100644 src/hw/mpt-scsi.c
create mode 100644 src/hw/mpt-scsi.h
diff --git a/Makefile b/Makefile
index 3a0d2e8..fcbd88a 100644
--- a/Makefile
+++ b/Makefile
@@ -34,7 +34,7 @@ SRCBOTH=misc.c stacks.c output.c string.c block.c cdrom.c disk.c mouse.c kbd.c \
hw/usb.c hw/usb-uhci.c hw/usb-ohci.c hw/usb-ehci.c \
hw/usb-hid.c hw/usb-msc.c hw/usb-uas.c \
hw/blockcmd.c hw/floppy.c hw/ata.c hw/ramdisk.c \
- hw/lsi-scsi.c hw/esp-scsi.c hw/megasas.c
+ hw/lsi-scsi.c hw/esp-scsi.c hw/megasas.c hw/mpt-scsi.c
SRC16=$(SRCBOTH)
SRC32FLAT=$(SRCBOTH) post.c memmap.c malloc.c romfile.c x86.c optionroms.c \
pmm.c font.c boot.c bootsplash.c jpeg.c bmp.c tcgbios.c sha1.c \
diff --git a/src/Kconfig b/src/Kconfig
index b873cd3..8250702 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -208,6 +208,12 @@ menu "Hardware support"
default y
help
Support boot from LSI MegaRAID SAS scsi storage.
+ config MPT_SCSI
+ depends on DRIVES
+ bool "LSI MPT Fusion controllers"
+ default y
+ help
+ Support boot from LSI MPT Fusion scsi storage.
config FLOPPY
depends on DRIVES && HARDWARE_IRQ
bool "Floppy controller"
diff --git a/src/block.c b/src/block.c
index 97e05fa..ef1cd9f 100644
--- a/src/block.c
+++ b/src/block.c
@@ -13,6 +13,7 @@
#include "hw/esp-scsi.h" // esp_scsi_process_op
#include "hw/lsi-scsi.h" // lsi_scsi_process_op
#include "hw/megasas.h" // megasas_process_op
+#include "hw/mpt-scsi.h" // mpt_scsi_process_op
#include "hw/pci.h" // pci_bdf_to_bus
#include "hw/pvscsi.h" // pvscsi_process_op
#include "hw/rtc.h" // rtc_read
@@ -521,6 +522,8 @@ process_op_both(struct disk_op_s *op)
return esp_scsi_process_op(op);
case DTYPE_MEGASAS:
return megasas_process_op(op);
+ case DTYPE_MPT_SCSI:
+ return mpt_scsi_process_op(op);
default:
if (!MODESEGMENT)
return DISK_RET_EPARAM;
diff --git a/src/block.h b/src/block.h
index 2ff359f..7de6f54 100644
--- a/src/block.h
+++ b/src/block.h
@@ -80,6 +80,7 @@ struct drive_s {
#define DTYPE_ESP_SCSI 0x81
#define DTYPE_MEGASAS 0x82
#define DTYPE_PVSCSI 0x83
+#define DTYPE_MPT_SCSI 0x84
#define DTYPE_SDCARD 0x90
#define MAXDESCSIZE 80
diff --git a/src/hw/mpt-scsi.c b/src/hw/mpt-scsi.c
new file mode 100644
index 0000000..c3b227b
--- /dev/null
+++ b/src/hw/mpt-scsi.c
@@ -0,0 +1,307 @@
+// MPT Fusion boot support.
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "biosvar.h" // GET_GLOBALFLAT
+#include "block.h" // struct drive_s
+#include "blockcmd.h" // scsi_drive_setup
+#include "config.h" // CONFIG_*
+#include "malloc.h" // free
+#include "output.h" // dprintf
+#include "pci.h" // foreachpci
+#include "pci_ids.h" // PCI_DEVICE_ID
+#include "pci_regs.h" // PCI_VENDOR_ID
+#include "std/disk.h" // DISK_RET_SUCCESS
+#include "string.h" // memset
+#include "util.h" // usleep
+
+#define MPT_REG_DOORBELL 0x00
+#define MPT_REG_WRITE_SEQ 0x04
+#define MPT_REG_HOST_DIAG 0x08
+#define MPT_REG_TEST 0x0c
+#define MPT_REG_DIAG_DATA 0x10
+#define MPT_REG_DIAG_ADDR 0x14
+#define MPT_REG_ISTATUS 0x30
+#define MPT_REG_IMASK 0x34
+#define MPT_REG_REQ_Q 0x40
+#define MPT_REG_REP_Q 0x44
+
+#define MPT_DOORBELL_MSG_RESET 0x40
+#define MPT_DOORBELL_HANDSHAKE 0x42
+
+#define MPT_IMASK_DOORBELL 0x01
+#define MPT_IMASK_REPLY 0x08
+
+struct mpt_lun_s {
+ struct drive_s drive;
+ struct pci_device *pci;
+ u32 iobase;
+ u8 target;
+ u8 lun;
+};
+
+u8 reply_msg[4] __attribute((aligned(4))) VARFSEG;
+
+#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST (0x00)
+#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT (0x02)
+
+static struct MptIOCInitRequest
+{
+ u8 WhoInit; /* Which system sent this init request. */
+ u8 Reserved1; /* Reserved */
+ u8 ChainOffset; /* Chain offset in the SG list. */
+ u8 Function; /* Function to execute. */
+ u8 Flags; /* Flags */
+ u8 MaxDevices; /* Max devices the driver can handle. */
+ u8 MaxBuses; /* Max buses the driver can handle. */
+ u8 MessageFlags; /* Message flags. */
+ u32 MessageContext; /* Message context ID. */
+ u16 ReplyFrameSize; /* Reply frame size. */
+ u16 Reserved2; /* Reserved */
+ u32 HostMfaHighAddr; /* Upper 32bit of the message frames. */
+ u32 SenseBufferHighAddr; /* Upper 32bit of the sense buffer. */
+} MptIOCInitRequest = {
+ .WhoInit = 2,
+ .Function = MPT_MESSAGE_HDR_FUNCTION_IOC_INIT,
+ .MaxDevices = 8,
+ .MaxBuses = 1,
+ .ReplyFrameSize = sizeof(reply_msg),
+ .HostMfaHighAddr = 0,
+ .SenseBufferHighAddr = 0
+};
+
+struct MptIOCInitReply {
+ u8 WhoInit; /* Which subsystem sent this init request. */
+ u8 Reserved1; /* Reserved */
+ u8 MessageLength; /* Message length */
+ u8 Function; /* Function. */
+ u8 Flags; /* Flags */
+ u8 MaxDevices; /* Maximum number of devices the driver can handle. */
+ u8 MaxBuses; /* Maximum number of busses the driver can handle. */
+ u8 MessageFlags; /* Message flags. */
+ u32 MessageContext; /* Message context ID */
+ u16 Reserved2; /* Reserved */
+ u16 IOCStatus; /* IO controller status. */
+ u32 IOCLogInfo; /* IO controller log information. */
+};
+
+typedef struct MptSCSIIORequest {
+ u8 TargetID; /* Target ID */
+ u8 Bus; /* Bus number */
+ u8 ChainOffset; /* Chain offset */
+ u8 Function; /* Function number. */
+ u8 CDBLength; /* CDB length. */
+ u8 SenseBufferLength; /* Sense buffer length. */
+ u8 Reserved; /* Reserved */
+ u8 MessageFlags; /* Message flags. */
+ u32 MessageContext; /* Message context ID. */
+ u8 LUN[8]; /* LUN */
+ u32 Control; /* Control values. */
+ u8 CDB[16]; /* The CDB. */
+ u32 DataLength; /* Data length. */
+ u32 SenseBufferLowAddr; /* Sense buffer low 32bit address. */
+} __attribute__((packed)) MptSCSIIORequest_t;
+
+#define MPT_CONTEXT_MAGIC 0x5555aaaa
+
+typedef struct MptSGEntrySimple32 {
+ u32 FlagsLength;
+ u32 DataBufferAddressLow;
+} __attribute__((packed)) MptSGEntrySimple32_t;
+
+static int
+mpt_scsi_cmd(u32 iobase, struct disk_op_s *op,
+ u8 *cdb, u16 target, u16 lun, u16 blocksize)
+{
+ if (lun != 0)
+ return DISK_RET_ENOTREADY;
+
+ u8 sense_buf[18];
+ struct scsi_req {
+ MptSCSIIORequest_t scsi_io;
+ MptSGEntrySimple32_t sge;
+ } __attribute__((packed, aligned(4))) req = {
+ .scsi_io = {
+ .TargetID = target,
+ .Bus = 0,
+ .Function = MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST,
+ .CDBLength = 16,
+ .SenseBufferLength = 18,
+ .MessageContext = MPT_CONTEXT_MAGIC,
+ .DataLength = op->count * blocksize,
+ .SenseBufferLowAddr = (u32)MAKE_FLATPTR(GET_SEG(SS), &sense_buf[0]),
+ },
+ .sge = {
+ /* end of list, simple entry, end of buffer, last element */
+ .FlagsLength = (op->count * blocksize) | 0xD1000000,
+ .DataBufferAddressLow = (u32)op->buf_fl,
+ }
+ };
+
+ req.scsi_io.LUN[1] = lun;
+ memcpy(req.scsi_io.CDB, cdb, 16);
+ if (blocksize) {
+ if (scsi_is_read(op)) {
+ req.scsi_io.Control = 2 << 24;
+ } else {
+ req.scsi_io.Control = 1 << 24;
+ req.sge.FlagsLength |= 0x04000000;
+ }
+ }
+
+ outl((u32)MAKE_FLATPTR(GET_SEG(SS), &req), iobase + MPT_REG_REQ_Q);
+
+ for (;;) {
+ u32 istatus = inl(iobase + MPT_REG_ISTATUS);
+ if (istatus & MPT_IMASK_REPLY) {
+ u32 resp = inl(iobase + MPT_REG_REP_Q);
+ /* another read to turn interrupt off */
+ inl(iobase + MPT_REG_REP_Q);
+ if (resp == MPT_CONTEXT_MAGIC) {
+ return DISK_RET_SUCCESS;
+ } else if (resp & 0x80000000) {
+ outl((u32)&reply_msg[0], iobase + MPT_REG_REP_Q);
+ return DISK_RET_EBADTRACK;
+ }
+ }
+ usleep(50);
+ }
+}
+
+int
+mpt_scsi_process_op(struct disk_op_s *op)
+{
+ if (!CONFIG_MPT_SCSI)
+ return DISK_RET_EBADTRACK;
+
+ u8 cdbcmd[16];
+ int blocksize = scsi_fill_cmd(op, cdbcmd, sizeof(cdbcmd));
+ if (blocksize < 0)
+ return default_process_op(op);
+
+ struct mpt_lun_s *llun_gf =
+ container_of(op->drive_gf, struct mpt_lun_s, drive);
+ u16 target = GET_GLOBALFLAT(llun_gf->target);
+ u16 lun = GET_GLOBALFLAT(llun_gf->lun);
+ u32 iobase = GET_GLOBALFLAT(llun_gf->iobase);
+ return mpt_scsi_cmd(iobase, op, cdbcmd, target, lun, blocksize);
+}
+
+static int
+mpt_scsi_add_lun(struct pci_device *pci, u32 iobase, u8 target, u8 lun)
+{
+ struct mpt_lun_s *llun = malloc_fseg(sizeof(*llun));
+ if (!llun) {
+ warn_noalloc();
+ return -1;
+ }
+ memset(llun, 0, sizeof(*llun));
+ llun->drive.type = DTYPE_MPT_SCSI;
+ llun->drive.cntl_id = pci->bdf;
+ llun->pci = pci;
+ llun->target = target;
+ llun->lun = lun;
+ llun->iobase = iobase;
+
+ char *name = znprintf(16, "mpt %02x:%02x.%x %d:%d",
+ pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
+ pci_bdf_to_fn(pci->bdf), target, lun);
+ int prio = bootprio_find_scsi_device(pci, target, lun);
+ int ret = scsi_drive_setup(&llun->drive, name, prio);
+ free(name);
+ if (ret) {
+ goto fail;
+ }
+ return 0;
+
+fail:
+ free(llun);
+ return -1;
+}
+
+static void
+mpt_scsi_scan_target(struct pci_device *pci, u32 iobase, u8 target)
+{
+ /* TODO: send REPORT LUNS. For now, only LUN 0 is recognized. */
+ mpt_scsi_add_lun(pci, iobase, target, 0);
+}
+
+static inline void
+mpt_out_doorbell(u8 func, u8 arg, u16 iobase)
+{
+ outl((func << 24) | (arg << 16), iobase + MPT_REG_DOORBELL);
+}
+
+static void
+init_mpt_scsi(struct pci_device *pci, const char *dev_name)
+{
+ u16 *msg_in_p;
+ u16 bdf = pci->bdf;
+ u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0)
+ & PCI_BASE_ADDRESS_IO_MASK;
+ struct MptIOCInitReply MptIOCInitReply;
+
+ pci_config_maskw(bdf, PCI_COMMAND, 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+
+ dprintf(1, "found %s at %02x:%02x.%x, io @ %x\n", dev_name,
+ pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf),
+ pci_bdf_to_fn(bdf), iobase);
+
+ // reset
+ mpt_out_doorbell(MPT_DOORBELL_MSG_RESET, 0, iobase);
+ outl(MPT_IMASK_DOORBELL|MPT_IMASK_REPLY , iobase + MPT_REG_IMASK);
+ outl(0, iobase + MPT_REG_ISTATUS);
+
+ // send IOC Init message through the doorbell
+ mpt_out_doorbell(MPT_DOORBELL_HANDSHAKE,
+ sizeof(MptIOCInitRequest)/sizeof(u32),
+ iobase);
+
+ outsl(iobase + MPT_REG_DOORBELL,
+ (u32 *)&MptIOCInitRequest,
+ sizeof(MptIOCInitRequest)/sizeof(u32));
+
+ // Read the reply 16 bits at a time. Cannot use insl
+ // because the port is 32 bits wide.
+ msg_in_p = (u16 *)&MptIOCInitReply;
+ while(msg_in_p != (u16 *)(&MptIOCInitReply + 1))
+ *msg_in_p++ = (u16)inl(iobase + MPT_REG_DOORBELL);
+
+ // Eat doorbell interrupt
+ outl(0, iobase + MPT_REG_ISTATUS);
+
+ // Post reply message used for SCSI errors
+ outl((u32)&reply_msg[0], iobase + MPT_REG_REP_Q);
+
+ for (int i = 0; i < 7; i++)
+ mpt_scsi_scan_target(pci, iobase, i);
+
+ return;
+}
+
+void
+mpt_scsi_setup(void)
+{
+ ASSERT32FLAT();
+ if (!CONFIG_MPT_SCSI) {
+ return;
+ }
+
+ dprintf(3, "init MPT\n");
+
+ struct pci_device *pci;
+ foreachpci(pci) {
+ if (pci->vendor == PCI_VENDOR_ID_LSI_LOGIC) {
+ if (pci->device == PCI_DEVICE_ID_LSI_53C1030) {
+ init_mpt_scsi(pci, "lsi53c1030");
+ }
+ if (pci->device == PCI_DEVICE_ID_LSI_SAS1068) {
+ init_mpt_scsi(pci, "sas1068");
+ }
+ if (pci->device == PCI_DEVICE_ID_LSI_SAS1068E) {
+ init_mpt_scsi(pci, "sas1068e");
+ }
+ }
+ }
+}
diff --git a/src/hw/mpt-scsi.h b/src/hw/mpt-scsi.h
new file mode 100644
index 0000000..6535dd8
--- /dev/null
+++ b/src/hw/mpt-scsi.h
@@ -0,0 +1,8 @@
+#ifndef __MPT_SCSI_H
+#define __MPT_SCSI_H
+
+struct disk_op_s;
+int mpt_scsi_process_op(struct disk_op_s *op);
+void mpt_scsi_setup(void);
+
+#endif /* __MPT_SCSI_H */
diff --git a/src/post.c b/src/post.c
index 6803585..1dd075e 100644
--- a/src/post.c
+++ b/src/post.c
@@ -14,6 +14,7 @@
#include "hw/ata.h" // ata_setup
#include "hw/esp-scsi.h" // esp_scsi_setup
#include "hw/lsi-scsi.h" // lsi_scsi_setup
+#include "hw/mpt-scsi.h" // lsi_scsi_setup
#include "hw/megasas.h" // megasas_setup
#include "hw/pvscsi.h" // pvscsi_setup
#include "hw/pic.h" // pic_setup
@@ -153,6 +154,7 @@ device_hardware_setup(void)
esp_scsi_setup();
megasas_setup();
pvscsi_setup();
+ mpt_scsi_setup();
}
static void
--
2.5.0
3 years, 3 months
sd card support
by Wim Vervoorn
Hello Kevin,
I am trying to use the sdcard support in SeaBIOS.
It is working but the performance is far from optimal. As far as I was able to see this is because the current support is polling only.
Do you know if there are plans to make dma versions of the code available?
Best regards,
Wim Vervoorn
3 years, 3 months
Re: [SeaBIOS] Qemu/Seabios and loading option roms
by Kevin O'Connor
On Sat, Jan 23, 2016 at 12:24:38AM +0000, Bob Moore wrote:
> Hi,
>
> I'm new to qemu/seabios and am in the process of developing an
> option rom for a pcie device. I want to use seabios as a driver for
> debugging this code. I see documentation that says I can put my
> option rom into a file with name of the form pciVVVV,DDDD.rom to
> contain my compiled/linked code that will be used when the device
> having that VendorID/DeviceId is processed in init_pcirom(). The
> lookup_hardcode() call looks for this file on a list via
> romfile_find(). The list looks to be populated from FW_CFG_FILE_DIR
> but I can't seem to find where the entries on this list actually
> come from. Is there a specific directory in the qemu project that
> is configured to contain these entries? Or maybe these are just
> configured in a file someplace?
>
> Any help would be greatly appreciated.
As discussed offline, it's possible to use the qemu command line
-option-rom option. Alternatively, one can place the rom in fwcfg
directly via the -fw_cfg command line option. If you're writing qemu
code the fw_cfg_add_file() function is also available.
[...]
> HGST E-mail Confidentiality Notice & Disclaimer:
> This e-mail and any files transmitted with it may contain confidential or legally privileged information of HGST and are intended solely for the use of the individual or entity to which they are addressed. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited. If you have received this e-mail in error, please notify the sender immediately and delete the e-mail in its entirety from your system.
This email was sent to a public email list.
-Kevin
3 years, 3 months
