[PATCH v2] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update
by David Woodhouse
We expect to use the space between the top of option ROMs and the bottom
of our own BIOS code as a stack. OVMF was previously marking the whole
region from 0xC0000 to 0xFFFFF read-only before invoking our Legacy16Boot
method. Read-only stack considered harmful.
Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which
allow the CSM to specify a memory region that needs to be writable.
There exists CONFIG_MALLOC_UPPERMEMORY which we could turn off to use
the 9-segment, but that isn't particularly useful for the CSM case
either because that memory isn't ours to play with until the final
Legacy16Boot call. There's a LowPmmMemory given to use by UEFI to play
with, but that's right in the *middle* of low memory and using that for
persistent allocations would be painful. So just require
CONFIG_MALLOC_UPPERMEMORY when building a CSM.
Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com>
---
v2: Require CONFIG_MALLOC_UPPERMEMORY. Default UmaAddress to &zonelow_base.
src/Kconfig | 2 +-
src/fw/csm.c | 6 +++++-
src/std/LegacyBios.h | 20 ++++++++++++++++++++
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index a42ab2d..093075c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -114,7 +114,7 @@ endchoice
the BIOS in 16bit protected mode.
config MALLOC_UPPERMEMORY
- bool "Allocate memory that needs to be in first Meg above 0xc0000"
+ bool "Allocate memory that needs to be in first Meg above 0xc0000" if !CSM
default y
help
Use the "Upper Memory Block" area (0xc0000-0xf0000) for
diff --git a/src/fw/csm.c b/src/fw/csm.c
index dfb0d12..4e4b688 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -34,6 +34,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG __aligned(16) = {
.Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
.OemIdStringPointer = (u32)"SeaBIOS",
.AcpiRsdPtrPointer = (u32)&csm_rsdp,
+ .UmaAddress = (u32)&zonelow_base,
+ .UmaSize = 0x10000,
};
EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table;
@@ -46,9 +48,11 @@ extern void __csm_return(struct bregs *regs) __noreturn;
static void
csm_return(struct bregs *regs)
{
- dprintf(3, "handle_csm returning AX=%04x\n", regs->ax);
+ u32 top = rom_get_max();
PICMask = pic_irqmask_read();
+ csm_compat_table.UmaAddress = top;
+ csm_compat_table.UmaSize = 0xf0000 - top;
__csm_return(regs);
}
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h
index cf0c3c5..5170c37 100644
--- a/src/std/LegacyBios.h
+++ b/src/std/LegacyBios.h
@@ -228,6 +228,26 @@ typedef struct {
/// Maximum PCI bus number assigned.
///
UINT8 LastPciBus;
+
+ ///
+ /// Start address of UMB RAM
+ ///
+ UINT32 UmaAddress;
+
+ ///
+ /// Size of UMB RAM
+ ///
+ UINT32 UmaSize;
+
+ ///
+ /// Start address of persistent allocation in high (>1MiB) memory
+ ///
+ UINT32 HiPermanentMemoryAddress;
+
+ ///
+ /// Size of persistent allocation in high (>1MiB) memory
+ ///
+ UINT32 HiPermanentMemorySize;
} EFI_COMPATIBILITY16_TABLE;
///
--
1.8.3.1
--
David Woodhouse Open Source Technology Centre
David.Woodhouse(a)intel.com Intel Corporation
4 years, 11 months
[PATCH 0/3] Run pvscsi driver entirely in 32bit mode.
by Kevin O'Connor
As with the recent change to AHCI, if the pvscsi driver needs to jump
into 32bit mode to access a register, then it's better to run the
pvscsi driver entirely in 32bit mode.
Evgeny, can you take a look at this and give it a test? Also, what
command line do you use for testing?
I tried testing locally by adding:
-device pvscsi,id=pvscsi0 -device scsi-disk,bus=pvscsi0.0,drive=drive0 -drive id=drive0,if=none,file=dos-drivec-new
to my qemu command line (both qemu v1.6 and qemu v1.7), but it doesn't
work for me even before my changes. It hangs in
pvscsi_wait_intr_cmpl().
-Kevin
Kevin O'Connor (3):
pvscsi: Don't store reference to struct pci_device.
pvscsi: Always run entirely in 32bit mode.
pvscsi: Remove use of LOWFLAT and GLOBALFLAT macros.
Makefile | 4 +--
src/block.c | 8 +++--
src/hw/blockcmd.c | 3 +-
src/hw/pvscsi.c | 106 +++++++++++++++++++++++++-----------------------------
4 files changed, 58 insertions(+), 63 deletions(-)
--
1.8.3.1
4 years, 11 months
[RFC PATCH] Add support for Intel Quark UART.
by David Woodhouse
This provides basic debug output on the Quark system, assuming that
*something* (i.e. coreboot or UEFI) has set it up in advance for us.
Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com>
---
I looked briefly at making this part of the CONFIG_DEBUG_SERIAL code,
and making that generic enough to handle I/O access *or* MMIO access
depending on what's present... but in fact that's probably overkill.
This isn't really limited to Quark; it would work with any 16550 device
wired up as MMIO32. But we can expand it as required, I think. No point
in starting off with the same functionality as the 5000-odd lines of the
Linux kernel's 8250_pci.c.
What do I need to do if called in 32-bit segmented mode? I'm guessing
that's not going to work right now...
src/Kconfig | 5 +++++
src/fw/csm.c | 2 ++
src/output.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 71 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index a42ab2d..bdc2602 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -472,6 +472,11 @@ menu "Debugging"
Set to zero to disable debugging.
+ config DEBUG_QUARK_UART
+ depends on DEBUG_LEVEL != 0
+ bool "Debug to Quark UART #1"
+ default n
+
config DEBUG_SERIAL
depends on DEBUG_LEVEL != 0
bool "Serial port debugging"
diff --git a/src/fw/csm.c b/src/fw/csm.c
index dfb0d12..afd7ffe 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -280,6 +280,8 @@ handle_csm(struct bregs *regs)
if (!CONFIG_CSM)
return;
+ debug_serial_preinit();
+
dprintf(3, "handle_csm regs %p AX=%04x\n", regs, regs->ax);
pic_irqmask_write(PICMask);
diff --git a/src/output.c b/src/output.c
index b47625f..a90d350 100644
--- a/src/output.c
+++ b/src/output.c
@@ -17,6 +17,8 @@
#include "stacks.h" // call16_int
#include "string.h" // memset
#include "util.h" // ScreenAndDebug
+#include "hw/pci_regs.h" // PCI_VENDOR_ID, PCI_BASE_ADDRESS_0
+#include "hw/pci.h" // pci_config_readl
struct putcinfo {
void (*func)(struct putcinfo *info, char c);
@@ -31,9 +33,59 @@ struct putcinfo {
u16 DebugOutputPort VARFSEG = 0x402;
+static volatile u32 *quark_uart_addr = 0;
+
+extern void _cfunc32flat_quark_uart_preinit(void);
+extern void _cfunc32flat_quark_uart_putc(void);
+extern void _cfunc32flat_quark_uart_flush(void);
+
+void quark_uart_preinit(void)
+{
+ // debug port is bus 0, device 0x14, function 5.
+ u16 uart_bdf = pci_to_bdf(0, 0x14, 5);
+
+ // If it isn't a Quark UART...
+ if (pci_config_readl(uart_bdf, PCI_VENDOR_ID) != 0x09368086)
+ return;
+
+ u32 bar0 = pci_config_readl(uart_bdf, PCI_BASE_ADDRESS_0);
+ if (!(bar0 & 0xf))
+ quark_uart_addr = (void *)bar0;
+}
+
+void quark_uart_putc(char c)
+{
+ if (!quark_uart_addr)
+ return;
+
+ int timeout = DEBUG_TIMEOUT;
+ while ((quark_uart_addr[SEROFF_LSR] & 0x20) != 0x20)
+ if (!timeout--)
+ // Ran out of time.
+ return;
+ quark_uart_addr[SEROFF_DATA] = c;
+}
+
+void quark_uart_flush(void)
+{
+ if (!quark_uart_addr)
+ return;
+ int timeout = DEBUG_TIMEOUT;
+ while ((quark_uart_addr[SEROFF_LSR] & 0x60) != 0x60)
+ if (!timeout--)
+ // Ran out of time.
+ return;
+}
+
void
debug_serial_preinit(void)
{
+ if (CONFIG_DEBUG_QUARK_UART) {
+ if (MODE16)
+ call32(_cfunc32flat_quark_uart_preinit, 0, 0);
+ else
+ quark_uart_preinit();
+ }
if (!CONFIG_DEBUG_SERIAL)
return;
// setup for serial logging: 8N1
@@ -54,6 +106,12 @@ debug_serial_preinit(void)
static void
debug_serial(char c)
{
+ if (CONFIG_DEBUG_QUARK_UART) {
+ if (MODE16)
+ call32(_cfunc32flat_quark_uart_putc, c, 0);
+ else
+ quark_uart_putc(c);
+ }
if (!CONFIG_DEBUG_SERIAL)
return;
int timeout = DEBUG_TIMEOUT;
@@ -68,6 +126,12 @@ debug_serial(char c)
static void
debug_serial_flush(void)
{
+ if (CONFIG_DEBUG_QUARK_UART) {
+ if (MODE16)
+ call32(_cfunc32flat_quark_uart_flush, 0, 0);
+ else
+ quark_uart_flush();
+ }
if (!CONFIG_DEBUG_SERIAL)
return;
int timeout = DEBUG_TIMEOUT;
--
1.8.3.1
--
dwmw2
4 years, 11 months
[PATCH 00/10] XHCI patches for real-hardware
by Kevin O'Connor
The following is my test series for XHCI. I've gotten it to the point
that I can boot from a "super speed" USB flash drive. However, high
speed flash drives and low speed keyboard/mouse still don't work for
me. Hopefully, when Gerd returns he'll have some insight.
The most notable part of this series is the work to make the code
auto-detect and handle 64 byte contexts (which the xhci controller on
my e350m1 requires).
The series is also available at:
https://github.com/KevinOConnor/seabios/tree/xhci-testing
-Kevin
Gerd Hoffmann (1):
xhci: allocate scratch pad buffers
Kevin O'Connor (9):
xhci: Use 64bit writes to ERDP register.
xhci: Fix incorrect direction setting on status transmissions.
xhci: Set the interval parameter on interrupt pipes.
xhci: Verify PAGESIZE register before initializing driver.
xhci: Allocate and free the xhci inctx structure on each use.
xhci: Move set_address code from xhci_control to xhci_alloc_pipe.
xhci: Eliminate 'struct xhci_device'.
xhci: Support xhci controllers with 64 byte contexts.
xhci: Allow the XHCI USB controller to be enabled for coreboot.
src/Kconfig | 2 +-
src/hw/usb-xhci.c | 342 +++++++++++++++++++++++++++++-------------------------
src/hw/usb-xhci.h | 8 --
src/hw/usb.c | 4 +-
src/hw/usb.h | 1 +
5 files changed, 186 insertions(+), 171 deletions(-)
--
1.8.3.1
5 years, 4 months
[PATCH] seabios: call pci_init_device on resume
by Michael S. Tsirkin
PIIX spec says that most its registers are reset on suspend.
However, QEMU didn't reset most of them properly.
Now that it started doing that, resume is broken.
Fix it up by probing system devices on bus 0 and re-initializing them.
Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com>
Reported-by: Gal Hammer <ghammer(a)redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a(a)redhat.com>
Tested-by: Marcel Apfelbaum <marcel.a(a)redhat.com>
---
src/hw/pci.h | 1 +
src/util.h | 1 +
src/fw/pciinit.c | 5 +++++
src/hw/pci.c | 31 ++++++++++++++++++++-----------
src/resume.c | 8 ++++++++
5 files changed, 35 insertions(+), 11 deletions(-)
diff --git a/src/hw/pci.h b/src/hw/pci.h
index 9c7351d..a64f7c5 100644
--- a/src/hw/pci.h
+++ b/src/hw/pci.h
@@ -66,6 +66,7 @@ extern u64 pcimem64_start, pcimem64_end;
extern struct hlist_head PCIDevices;
extern int MaxPCIBus;
int pci_probe_host(void);
+void pci_probe_device(int bdf, struct pci_device *dev);
void pci_probe_devices(void);
static inline u32 pci_classprog(struct pci_device *pci) {
return (pci->class << 8) | pci->prog_if;
diff --git a/src/util.h b/src/util.h
index e6a6cb5..3a24dba 100644
--- a/src/util.h
+++ b/src/util.h
@@ -28,6 +28,7 @@ void boot_add_cbfs(void *data, const char *desc, int prio);
void interactive_bootmenu(void);
void bcv_prepboot(void);
struct pci_device;
+void pci_bios_resume_device(struct pci_device *pci);
int bootprio_find_pci_device(struct pci_device *pci);
int bootprio_find_scsi_device(struct pci_device *pci, int target, int lun);
int bootprio_find_ata_device(struct pci_device *pci, int chanid, int slave);
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 34279a4..a4cedfb 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -293,6 +293,11 @@ static const struct pci_device_id pci_device_tbl[] = {
PCI_DEVICE_END,
};
+void pci_bios_resume_device(struct pci_device *pci)
+{
+ pci_init_device(pci_device_tbl, pci, NULL);
+}
+
static void pci_bios_init_device(struct pci_device *pci)
{
u16 bdf = pci->bdf;
diff --git a/src/hw/pci.c b/src/hw/pci.c
index 6c9aa81..c2873c3 100644
--- a/src/hw/pci.c
+++ b/src/hw/pci.c
@@ -105,6 +105,24 @@ pci_probe_host(void)
return 0;
}
+void
+pci_probe_device(int bdf, struct pci_device *dev)
+{
+ dev->bdf = bdf;
+ u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID);
+ dev->vendor = vendev & 0xffff;
+ dev->device = vendev >> 16;
+ u32 classrev = pci_config_readl(bdf, PCI_CLASS_REVISION);
+ dev->class = classrev >> 16;
+ dev->prog_if = classrev >> 8;
+ dev->revision = classrev & 0xff;
+ dev->header_type = pci_config_readb(bdf, PCI_HEADER_TYPE);
+ u8 v = dev->header_type & 0x7f;
+ if (v == PCI_HEADER_TYPE_BRIDGE || v == PCI_HEADER_TYPE_CARDBUS) {
+ u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
+ dev->secondary_bus = secbus;
+ }
+}
// Find all PCI devices and populate PCIDevices linked list.
void
pci_probe_devices(void)
@@ -145,21 +163,12 @@ pci_probe_devices(void)
}
// Populate pci_device info.
- dev->bdf = bdf;
+ pci_probe_device(bdf, dev);
dev->parent = parent;
dev->rootbus = rootbus;
- u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID);
- dev->vendor = vendev & 0xffff;
- dev->device = vendev >> 16;
- u32 classrev = pci_config_readl(bdf, PCI_CLASS_REVISION);
- dev->class = classrev >> 16;
- dev->prog_if = classrev >> 8;
- dev->revision = classrev & 0xff;
- dev->header_type = pci_config_readb(bdf, PCI_HEADER_TYPE);
u8 v = dev->header_type & 0x7f;
if (v == PCI_HEADER_TYPE_BRIDGE || v == PCI_HEADER_TYPE_CARDBUS) {
- u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
- dev->secondary_bus = secbus;
+ u8 secbus = dev->secondary_bus;
if (secbus > bus && !busdevs[secbus])
busdevs[secbus] = dev;
if (secbus > MaxPCIBus)
diff --git a/src/resume.c b/src/resume.c
index fc2fee9..9aac853 100644
--- a/src/resume.c
+++ b/src/resume.c
@@ -101,6 +101,14 @@ s3_resume(void)
pic_setup();
smm_setup();
+ int bdf;
+ foreachbdf(bdf, 0) {
+ // Create new pci_device struct and add to list.
+ struct pci_device pci;
+ pci_probe_device(bdf, &pci);
+ pci_bios_resume_device(&pci);
+ }
+
s3_resume_vga();
make_bios_readonly();
--
MST
5 years, 4 months
[PATCH 1/3] Introduce serial_out(), serial_in() macros in serialio.c
by David Woodhouse
This will make it easier to abstract out the MMIO serial access. Even if
that ends up in separate code which is a *copy* of this, at least they'll
match.
Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com>
---
src/hw/serialio.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/src/hw/serialio.c b/src/hw/serialio.c
index 6486fc0..8ec36c2 100644
--- a/src/hw/serialio.c
+++ b/src/hw/serialio.c
@@ -1,6 +1,6 @@
// Low-level serial (and serial-like) device access.
//
-// Copyright (C) 2008-1013 Kevin O'Connor <kevin(a)koconnor.net>
+// Copyright (C) 2008-2013 Kevin O'Connor <kevin(a)koconnor.net>
//
// This file may be distributed under the terms of the GNU LGPLv3 license.
@@ -17,6 +17,9 @@
#define DEBUG_TIMEOUT 100000
+#define serial_out(d, reg) outb(d, CONFIG_DEBUG_SERIAL_PORT+(reg))
+#define serial_in(reg) inb(CONFIG_DEBUG_SERIAL_PORT+(reg))
+
// Setup the debug serial port for output.
void
serial_debug_preinit(void)
@@ -25,12 +28,12 @@ serial_debug_preinit(void)
return;
// setup for serial logging: 8N1
u8 oldparam, newparam = 0x03;
- oldparam = inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LCR);
- outb(newparam, CONFIG_DEBUG_SERIAL_PORT+SEROFF_LCR);
+ oldparam = serial_in(SEROFF_LCR);
+ serial_out(newparam, SEROFF_LCR);
// Disable irqs
u8 oldier, newier = 0;
- oldier = inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_IER);
- outb(newier, CONFIG_DEBUG_SERIAL_PORT+SEROFF_IER);
+ oldier = serial_in(SEROFF_IER);
+ serial_out(newier, SEROFF_IER);
if (oldparam != newparam || oldier != newier)
dprintf(1, "Changing serial settings was %x/%x now %x/%x\n"
@@ -44,11 +47,11 @@ serial_debug(char c)
if (!CONFIG_DEBUG_SERIAL)
return;
int timeout = DEBUG_TIMEOUT;
- while ((inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LSR) & 0x20) != 0x20)
+ while ((serial_in(SEROFF_LSR) & 0x20) != 0x20)
if (!timeout--)
// Ran out of time.
return;
- outb(c, CONFIG_DEBUG_SERIAL_PORT+SEROFF_DATA);
+ serial_out(c, SEROFF_DATA);
}
void
@@ -66,7 +69,7 @@ serial_debug_flush(void)
if (!CONFIG_DEBUG_SERIAL)
return;
int timeout = DEBUG_TIMEOUT;
- while ((inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LSR) & 0x60) != 0x60)
+ while ((serial_in(SEROFF_LSR) & 0x60) != 0x60)
if (!timeout--)
// Ran out of time.
return;
--
1.8.3.1
--
David Woodhouse Open Source Technology Centre
David.Woodhouse(a)intel.com Intel Corporation
5 years, 4 months
[PATCH 0/4] Make XHCI driver run entirely in 32bit mode
by Kevin O'Connor
Some further testing code for xhci. This patch set allows the xhci
controller to run entirely in 32bit mode, which can lead to further
code simplifications and reduces the overall seabios binary size.
I've pushed this to the xhci-testing branch at:
https://github.com/KevinOConnor/seabios/tree/xhci-testing
-Kevin
Kevin O'Connor (4):
Add call32_params() helper function.
Add space between DTYPE_* definitions.
xhci: Run the XHCI driver entirely in 32bit mode.
Remove pci_writel() and pci_readl() functions.
Makefile | 4 ++--
src/block.c | 2 ++
src/block.h | 32 +++++++++++++++++---------------
src/hw/blockcmd.c | 6 ++++++
src/hw/pci.c | 46 ----------------------------------------------
src/hw/pci.h | 4 ----
src/hw/usb-msc.c | 5 ++++-
src/hw/usb-uas.c | 5 ++++-
src/hw/usb-xhci.c | 13 ++++++-------
src/hw/usb.c | 13 +++++++++++--
src/hw/usb.h | 1 +
src/stacks.c | 27 +++++++++++++++++++++++++++
src/stacks.h | 1 +
13 files changed, 81 insertions(+), 78 deletions(-)
--
1.8.3.1
5 years, 4 months
Opal SSC (encrypted) hard drives unsupported, despite TPM support?
by GNUtoo＠no-log.org
The http://www.coreboot.org/Benefits page says under "possible
advantages":
* TPMs...
with no detail. (note that the three dots are literally on the
webpage, not my paraphrasing).
Support for TPMs /could/ mean support for self-encrypted (Opal) hard
drives, but there are other kinds of TPMs (e.g. fingerprint reading)
so it's unclear what actually works on coreboot.
Someone in #coreboot hinted (without confidence) that only software
encryption is possible under coreboot. Is that true?
5 years, 4 months
[PATCH] xhci: Hack to get hubs working.
by Kevin O'Connor
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
This patch is for testing. It allows me to use low speed devices
behind a high speed hub attached to an xhci controller.
Interestingly, high speed devices behind a high speed hub didn't
require any changes on my xhci controller. I don't have a super speed
hub to test with.
I've also pushed this to:
https://github.com/KevinOConnor/seabios/tree/xhci-testing
---
src/hw/usb-xhci.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 57 insertions(+), 10 deletions(-)
diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c
index 4529724..78ad03c 100644
--- a/src/hw/usb-xhci.c
+++ b/src/hw/usb-xhci.c
@@ -818,24 +818,65 @@ xhci_alloc_inctx(struct usbdevice_s *usbdev)
}
memset(in, 0, size);
- u32 route = 0;
- while (usbdev->hub->usbdev) {
- route <<= 4;
- route |= (usbdev->port+1) & 0xf;
- usbdev = usbdev->hub->usbdev;
- }
-
in->add = 0x01;
struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64];
slot->ctx[0] |= (1 << 27); // context entries
slot->ctx[0] |= speed_to_xhci[usbdev->speed] << 20;
- slot->ctx[0] |= route;
+
+ // Set high-speed hub flags.
+ struct usbdevice_s *hubdev = usbdev->hub->usbdev;
+ if (hubdev) {
+ if (usbdev->speed == USB_LOWSPEED || usbdev->speed == USB_FULLSPEED) {
+ struct xhci_pipe *hpipe = container_of(
+ hubdev->defpipe, struct xhci_pipe, pipe);
+ if (hubdev->speed == USB_HIGHSPEED) {
+ slot->ctx[2] |= hpipe->slotid;
+ slot->ctx[2] |= (usbdev->port+1) << 8;
+ } else {
+ struct xhci_slotctx *hslot = (void*)xhci->devs[hpipe->slotid].ptr_low;
+ slot->ctx[2] = hslot->ctx[2];
+ }
+ }
+ u32 route = 0;
+ while (usbdev->hub->usbdev) {
+ route <<= 4;
+ route |= (usbdev->port+1) & 0xf;
+ usbdev = usbdev->hub->usbdev;
+ }
+ slot->ctx[0] |= route;
+ }
+
slot->ctx[1] |= (usbdev->port+1) << 16;
- /* TODO ctx0: hub bit */
- /* TODO ctx1: hub ports */
+
return in;
}
+static int xhci_config_hub(struct usbhub_s *hub)
+{
+ struct usb_xhci_s *xhci = container_of(
+ hub->cntl, struct usb_xhci_s, usb);
+ struct xhci_pipe *pipe = container_of(
+ hub->usbdev->defpipe, struct xhci_pipe, pipe);
+ struct xhci_slotctx *hdslot = (void*)xhci->devs[pipe->slotid].ptr_low;
+ if ((hdslot->ctx[3] >> 27) == 3)
+ // Already configured
+ return 0;
+ struct xhci_inctx *in = xhci_alloc_inctx(hub->usbdev);
+ if (!in)
+ return -1;
+ struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64];
+ slot->ctx[0] |= 1 << 26;
+ slot->ctx[1] |= hub->portcount << 24;
+
+ int cc = xhci_cmd_configure_endpoint(xhci, pipe->slotid, in);
+ free(in);
+ if (cc != CC_SUCCESS) {
+ dprintf(1, "%s: configure hub: failed (cc %d)\n", __func__, cc);
+ return -1;
+ }
+ return 0;
+}
+
struct usb_pipe *
xhci_alloc_pipe(struct usbdevice_s *usbdev
, struct usb_endpoint_descriptor *epdesc)
@@ -875,6 +916,12 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev
dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__,
usbdev, &pipe->reqs, pipe->slotid, pipe->epid);
if (pipe->epid == 1) {
+ if (usbdev->hub->usbdev) {
+ // Ugly hack to enable hub ports.
+ int ret = xhci_config_hub(usbdev->hub);
+ if (ret)
+ goto fail;
+ }
// Enable slot and send set_address command.
u32 size = (sizeof(struct xhci_slotctx) * 32) << xhci->context64;
struct xhci_slotctx *dev = memalign_high(1024 << xhci->context64, size);
--
1.8.3.1
5 years, 4 months
Re: [SeaBIOS] [PATCH] Remove the pmm handle argument from _malloc().
by Don Slutz
On 12/27/13 11:35, Kevin O'Connor wrote:
> The PMM handle argument will almost always be 0xffffffff. Use
> separate code for the few rare cases where it may not be the default
> value. Gcc produces better code if _malloc() only requires three
> parameters.
>
> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
> ---
> src/fw/csm.c | 4 ++--
> src/fw/romfile_loader.c | 2 +-
> src/malloc.c | 23 ++++++++++++++++++-----
> src/malloc.h | 23 ++++++++++++-----------
> src/pmm.c | 19 ++++++++++++-------
> 5 files changed, 45 insertions(+), 26 deletions(-)
>
> diff --git a/src/fw/csm.c b/src/fw/csm.c
> index dfb0d12..a44ed26 100644
> --- a/src/fw/csm.c
> +++ b/src/fw/csm.c
> @@ -257,9 +257,9 @@ handle_csm_0006(struct bregs *regs)
> size, align, region);
>
> if (region & 2)
> - chunk = _malloc(&ZoneLow, MALLOC_DEFAULT_HANDLE, size, align);
> + chunk = _malloc(&ZoneLow, size, align);
> if (!chunk && (region & 1))
> - chunk = _malloc(&ZoneFSeg, MALLOC_DEFAULT_HANDLE, size, align);
> + chunk = _malloc(&ZoneFSeg, size, align);
>
> dprintf(3, "Legacy16GetTableAddress size %x align %x region %d yields %p\n",
> size, align, region, chunk);
> diff --git a/src/fw/romfile_loader.c b/src/fw/romfile_loader.c
> index 325a0fa..f4b17ff 100644
> --- a/src/fw/romfile_loader.c
> +++ b/src/fw/romfile_loader.c
> @@ -57,7 +57,7 @@ static void romfile_loader_allocate(struct romfile_loader_entry_s *entry,
> file->file = romfile_find(entry->alloc_file);
> if (!file->file || !file->file->size)
> return;
> - data = _malloc(zone, MALLOC_DEFAULT_HANDLE, file->file->size, alloc_align);
> + data = _malloc(zone, file->file->size, alloc_align);
> if (!data) {
> warn_noalloc();
> return;
> diff --git a/src/malloc.c b/src/malloc.c
> index 6ef418a..c4cb171 100644
> --- a/src/malloc.c
> +++ b/src/malloc.c
> @@ -225,7 +225,7 @@ zonelow_expand(u32 size, u32 align, struct allocinfo_s *fill)
>
> // Allocate memory from the given zone and track it as a PMM allocation
> void * __malloc
> -_malloc(struct zone_s *zone, u32 handle, u32 size, u32 align)
> +_malloc(struct zone_s *zone, u32 size, u32 align)
> {
> ASSERT32FLAT();
> if (!size)
> @@ -240,6 +240,7 @@ _malloc(struct zone_s *zone, u32 handle, u32 size, u32 align)
> if (!detail)
> return NULL;
> }
> + detail->handle = MALLOC_DEFAULT_HANDLE;
>
> // Find and reserve space for main allocation
> void *data = allocSpace(zone, size, align, &detail->datainfo);
> @@ -250,9 +251,8 @@ _malloc(struct zone_s *zone, u32 handle, u32 size, u32 align)
> return NULL;
> }
>
> - dprintf(8, "_malloc zone=%p handle=%x size=%d align=%x ret=%p (detail=%p)\n"
> - , zone, handle, size, align, data, detail);
> - detail->handle = handle;
> + dprintf(8, "_malloc zone=%p size=%d align=%x ret=%p (detail=%p)\n"
> + , zone, size, align, data, detail);
>
> return data;
> }
> @@ -296,9 +296,22 @@ malloc_getspace(struct zone_s *zone)
> return maxspace - reserve;
> }
>
> +// Set a handle associated with an allocation.
> +void
> +malloc_sethandle(void *data, u32 handle)
> +{
> + ASSERT32FLAT();
> + struct allocinfo_s *info = findAlloc(data);
> + if (!info || data == (void*)info || data == info->dataend)
> + return;
> + struct allocdetail_s *detail = container_of(
> + info, struct allocdetail_s, datainfo);
> + detail->handle = handle;
I would think a "dprint(8" should be here like:
dprintf(8, "malloc_sethandle handle=%x data=%p (detail=%p)\n"
, handle, data, detail);
-Don Slutz
> +}
> +
> // Find the data block allocated with _malloc with a given handle.
> void *
> -malloc_find(u32 handle)
> +malloc_findhandle(u32 handle)
> {
> int i;
> for (i=0; i<ARRAY_SIZE(Zones); i++) {
> diff --git a/src/malloc.h b/src/malloc.h
> index af8a21d..2bcb5bf 100644
> --- a/src/malloc.h
> +++ b/src/malloc.h
> @@ -15,29 +15,30 @@ void malloc_preinit(void);
> extern u32 LegacyRamSize;
> void malloc_init(void);
> void malloc_prepboot(void);
> -void *_malloc(struct zone_s *zone, u32 handle, u32 size, u32 align);
> +void *_malloc(struct zone_s *zone, u32 size, u32 align);
> int _free(void *data);
> u32 malloc_getspace(struct zone_s *zone);
> -void *malloc_find(u32 handle);
> +void malloc_sethandle(void *data, u32 handle);
> +void *malloc_findhandle(u32 handle);
>
> #define MALLOC_DEFAULT_HANDLE 0xFFFFFFFF
> // Minimum alignment of malloc'd memory
> #define MALLOC_MIN_ALIGN 16
> // Helper functions for memory allocation.
> static inline void *malloc_low(u32 size) {
> - return _malloc(&ZoneLow, MALLOC_DEFAULT_HANDLE, size, MALLOC_MIN_ALIGN);
> + return _malloc(&ZoneLow, size, MALLOC_MIN_ALIGN);
> }
> static inline void *malloc_high(u32 size) {
> - return _malloc(&ZoneHigh, MALLOC_DEFAULT_HANDLE, size, MALLOC_MIN_ALIGN);
> + return _malloc(&ZoneHigh, size, MALLOC_MIN_ALIGN);
> }
> static inline void *malloc_fseg(u32 size) {
> - return _malloc(&ZoneFSeg, MALLOC_DEFAULT_HANDLE, size, MALLOC_MIN_ALIGN);
> + return _malloc(&ZoneFSeg, size, MALLOC_MIN_ALIGN);
> }
> static inline void *malloc_tmplow(u32 size) {
> - return _malloc(&ZoneTmpLow, MALLOC_DEFAULT_HANDLE, size, MALLOC_MIN_ALIGN);
> + return _malloc(&ZoneTmpLow, size, MALLOC_MIN_ALIGN);
> }
> static inline void *malloc_tmphigh(u32 size) {
> - return _malloc(&ZoneTmpHigh, MALLOC_DEFAULT_HANDLE, size, MALLOC_MIN_ALIGN);
> + return _malloc(&ZoneTmpHigh, size, MALLOC_MIN_ALIGN);
> }
> static inline void *malloc_tmp(u32 size) {
> void *ret = malloc_tmphigh(size);
> @@ -46,16 +47,16 @@ static inline void *malloc_tmp(u32 size) {
> return malloc_tmplow(size);
> }
> static inline void *memalign_low(u32 align, u32 size) {
> - return _malloc(&ZoneLow, MALLOC_DEFAULT_HANDLE, size, align);
> + return _malloc(&ZoneLow, size, align);
> }
> static inline void *memalign_high(u32 align, u32 size) {
> - return _malloc(&ZoneHigh, MALLOC_DEFAULT_HANDLE, size, align);
> + return _malloc(&ZoneHigh, size, align);
> }
> static inline void *memalign_tmplow(u32 align, u32 size) {
> - return _malloc(&ZoneTmpLow, MALLOC_DEFAULT_HANDLE, size, align);
> + return _malloc(&ZoneTmpLow, size, align);
> }
> static inline void *memalign_tmphigh(u32 align, u32 size) {
> - return _malloc(&ZoneTmpHigh, MALLOC_DEFAULT_HANDLE, size, align);
> + return _malloc(&ZoneTmpHigh, size, align);
> }
> static inline void *memalign_tmp(u32 align, u32 size) {
> void *ret = memalign_tmphigh(align, size);
> diff --git a/src/pmm.c b/src/pmm.c
> index be03bdb..304faab 100644
> --- a/src/pmm.c
> +++ b/src/pmm.c
> @@ -65,21 +65,26 @@ handle_pmm00(u16 *args)
> if (align < MALLOC_MIN_ALIGN)
> align = MALLOC_MIN_ALIGN;
> }
> + void *data;
> switch (flags & 3) {
> default:
> case 0:
> return 0;
> case 1:
> - return (u32)_malloc(lowzone, handle, size, align);
> + data = _malloc(lowzone, size, align);
> + break;
> case 2:
> - return (u32)_malloc(highzone, handle, size, align);
> + data = _malloc(highzone, size, align);
> + break;
> case 3: {
> - void *data = _malloc(lowzone, handle, size, align);
> - if (data)
> - return (u32)data;
> - return (u32)_malloc(highzone, handle, size, align);
> + data = _malloc(lowzone, size, align);
> + if (!data)
> + data = _malloc(highzone, size, align);
> }
> }
> + if (data && handle != MALLOC_DEFAULT_HANDLE)
> + malloc_sethandle(data, handle);
> + return (u32)data;
> }
>
> // PMM - find
> @@ -90,7 +95,7 @@ handle_pmm01(u16 *args)
> dprintf(3, "pmm01: handle=%x\n", handle);
> if (handle == MALLOC_DEFAULT_HANDLE)
> return 0;
> - return (u32)malloc_find(handle);
> + return (u32)malloc_findhandle(handle);
> }
>
> // PMM - deallocate
5 years, 4 months
