This patch aimed to avoid problem with uninitialized virtio-blk and
virtio-scsi boot devices.
Currently, 12 KiB of memory is allocated for each virtio-blk/scsi, so
no more than about 10 devices can be initialized. If the device is not
initialized, we cannot boot from it. So, if we have more than 10 devices,
we can't boot from any of the following (11, 12, etc.).
We can initialize only bootable devices, i.e. listed in boot order list,
that this patch does.
Alexey Kirillov (2):
boot: Detect strict boot order (HALT record) in function
virtio: Do not init non-bootable devices
src/boot.c | 5 +++++
src/hw/virtio-blk.c | 11 ++++++++++-
src/hw/virtio-scsi.c | 11 ++++++++++-
src/util.h | 1 +
4 files changed, 26 insertions(+), 2 deletions(-)
--
2.17.1
Hi Michael & Lists,
I'd like to ask for ideas with the following problem we have.
(1) There is a functional iPXE + WDS setup, with iPXE built as a
traditional BIOS PCI option ROM, using CONFIG=qemu. Accordingly the
platform is qemu, with SeaBIOS, and the NIC is virtio-net-pci.
I don't know anything about the particulars of the WDS setup at this
point, only that the boot loader program it exposes is WDSNBP.COM.
(2) The setup works fine when iPXE is built at commit 4e85b2708fa0
("[virtio] Use host-specified MTU when available", 2017-01-23).
(3) When iPXE is built at commit 133f4c47baef ("[build] Handle
R_X86_64_PLT32 from binutils 2.31", 2018-09-17), the setup breaks.
The symptom is that iPXE fetches WDSNBP.COM just fine, but WDSNBP.COM,
rather than doing whatever it does otherwise, keeps PXE-booting itself
(3+ times), and finally aborts.
Consider the following log output (my undertanding is that all this is
logged by WDSNBP.COM):
> Downloaded WDSNBP...
>
> Press F12 for network service boot
> Architecture: x64
> WDSNBP started using DHCP Referral.
> Contacting Server: ... (Gateway: ...)
> Contacting Server: ...
> TFTP Download: boot\x86\wdsnbp.com
This block repeats approx. 3 times, after which the following is
displayed:
> Windows Deployment Services: PXE Boot Aborted.
> Could not boot image: Error 0x7f8d8101 (http://ipxe.org/7f8d8101)
> No more network devices
>
> No bootable device
My understanding is that the first line from this last block is printed
by WDSNBP.COM, the second line by iPXE (in pxe_start_nbp()), the third
line also by iPXE, and the last one by SeaBIOS.
This seems to indicate that WDSNBP.COM exits with an error code, and
pxe_start_nbp() logs it as "Error 0x7f8d8101".
(4) Now, after a bit of searching the web, I've found the following
articles, which indicate that the WDS (= server side) setup is
incorrect:
(4a) "disable NetBios over TCPIP, on the WDS server"
https://techthoughts.info/pxe-booting-wds-dhcp-scope-vs-ip-helpers/#comme...https://social.technet.microsoft.com/Forums/ie/en-US/f3883e8b-1039-477d-9...
(4b) "cover all combinations of forward and backwards slashes in
ReadFilter, on the WDS server"
http://ipxe.org/appnote/chainload_wds#tftp_loops
However: the regression appears to be a function of *only* the git
commit at which we build iPXE. It seems so deterministic that we
bisected commit range 4e85b2708fa0..133f4c47baef. (Hence we have not
captured the network traffic yet, nor have we investigated the WDS
server config.)
The "culprit" commit is ea29122a70c6 ("[http] Include error messages for
4xx and 5xx response codes", 2017-12-28).
(5) Which makes no sense to me, unfortunately. :(
Commit ea29122a70c6 adds the "http_errors" array to the code. According
to
src/include/ipxe/tables.h
and the build artifact
src/bin/1af41000.rom.tmp.map
this new array is placed in a new section called
.textdata.tbl.errortab.01
Trying to retro-fit those facts to the symptom encountered, I came up
with the idea that *maybe* the new array (or section) causes a memory
allocation failure in WDSNBP.COM -- due to increased memory footprint of
iPXE. Which then leads to the misbehavior of WDSNBP.COM.
After all, WDSNBP.COM is a 16-bit real-mode program:
https://support.microsoft.com/en-us/help/4468601/pxe-boot-in-configuratio...
so it could be susceptible to the size & fragmentation of the RAM that
is under 640KB.
(6) Unfortunately, this "low RAM exhaustion" idea doesn't seem to hold
water. There are at least two counter-arguments:
(6a) if I revert commit ea29122a70c6 on top of commit 133f4c47baef, then
the issue does *not* go away.
(The issue also does not go away if I remove the "netdev_errors" array,
also on top of commit 133f4c47baef -- that's a larger array.)
(... In theory anyway, this might not necessarily disprove the memory
exhaustion idea. What if the iPXE footprint grows, over the
ea29122a70c6..133f4c47baef so much, for independent reasons, that
reverting ea29122a70c6 at the end cannot compensate for that increase?)
(6b) I added "DEBUG=pxe_call:1" to the "make" command, and compared the
debug messages printed by pxe_start_nbp(), between 4e85b2708fa0 and
133f4c47baef. Alas, the debug messages are identical:
> PXE NBP starting with netdev net0, code 9c6c:0802, data 9cf0:2ce0
which to me suggests that there is no change in the amount of memory
that is made available to WDSNBP.COM -- its code and data continue to
start at 0x9_CEC2 and 0x9_FBE0, respectively.
Any hints as to what could be going wrong?
Thanks!
Laszlo
This patch aimed to avoid problem with uninitialized virtio-blk and
virtio-scsi boot devices.
Currently, 12 KiB of memory is allocated for each virtio-blk/scsi, so
no more than about 10 devices can be initialized. If the device is not
initialized, we cannot boot from it. So, if we have more than 10 devices,
we can't boot from any of the following (11, 12, etc.).
We can initialize only bootable devices, i.e. listed in boot order list,
that this patch does.
Alexey Kirillov (1):
virtio: do not init non-bootable devices
docs/Runtime_config.md | 1 +
src/hw/virtio-blk.c | 10 ++++++++++
src/hw/virtio-scsi.c | 10 ++++++++++
3 files changed, 21 insertions(+)
--
2.17.1
On physical hardware, some PCI devices are not detectable when UEFI
BIOS invokes our InitializeYourself() function. But they are
guaranteed to be available before UEFI invokes our PreparToBoot()
function. So in the case of running CSM on physical hardware, we execute
pci_probe_devices() at PrepareToBoot() stage.
Signed-off-by: Bin Gao <gaobin(a)amazon.com>
---
src/fw/csm.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/fw/csm.c b/src/fw/csm.c
index 8359bcb..82d375c 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -63,7 +63,9 @@ static void
csm_maininit(struct bregs *regs)
{
interface_init();
- pci_probe_devices();
+
+ if (CONFIG_CSM && CONFIG_QEMU_HARDWARE)
+ pci_probe_devices();
csm_compat_table.PnPInstallationCheckSegment = SEG_BIOS;
csm_compat_table.PnPInstallationCheckOffset = get_pnp_offset();
@@ -143,6 +145,13 @@ handle_csm_0002(struct bregs *regs)
return;
}
+ // On physical hardware, some PCI devices are not detectable when
+ // UEFI invokes our InitializeYourself() function. But they
+ // are guaranteed to be available before UEFI invokes our
+ // PreparToBoot() function.
+ if (CONFIG_CSM && !CONFIG_QEMU_HARDWARE)
+ pci_probe_devices();
+
dprintf(3, "PrepareToBoot table %04x:%04x\n", regs->es, regs->bx);
struct e820entry *p = (void *)csm_compat_table.E820Pointer;
--
2.17.1
Some USB keyboards report 9 or 10-byte max packet sizes, instead
of the 8-byte max specified by the USB HID spec. Handle this by
increasing the size of the keyevent struct to 10 bytes, and using the key
array size of the usbkeyinfo struct as loop bounds rather than that of the
keyevent struct (since the former will always be smaller, and within spec).
Test: built/boot on Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/hw/usb-hid.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/hw/usb-hid.c b/src/hw/usb-hid.c
index fa4d9a2..bce1b5f 100644
--- a/src/hw/usb-hid.c
+++ b/src/hw/usb-hid.c
@@ -8,6 +8,7 @@
#include "config.h" // CONFIG_*
#include "output.h" // dprintf
#include "ps2port.h" // ATKBD_CMD_GETID
+#include <string.h> //memset
#include "usb.h" // usb_ctrlrequest
#include "usb-hid.h" // usb_keyboard_setup
#include "util.h" // process_key
@@ -59,8 +60,10 @@ usb_kbd_setup(struct usbdevice_s *usbdev
// XXX - this enables the first found keyboard (could be random)
return -1;
- if (epdesc->wMaxPacketSize != 8)
+ if (epdesc->wMaxPacketSize > 10) {
+ dprintf(1, "USB keyboard endpoint wMaxPacketSize > 10; aborting\n");
return -1;
+ }
// Enable "boot" protocol.
int ret = set_protocol(usbdev->defpipe, 0);
@@ -163,11 +166,15 @@ static u16 ModifierToScanCode[] VAR16 = {
#define RELEASEBIT 0x80
-// Format of USB keyboard event data
+// Format of USB keyboard event data.
+// Some keyboards use a 9/10 byte packet size,
+// so account for that here to prevent buffer
+// overflow. We'll ignore the 9th/10th bytes
+// as it's out of spec.
struct keyevent {
u8 modifiers;
u8 reserved;
- u8 keys[6];
+ u8 keys[8];
};
// Translate data from KeyToScanCode[] to calls to process_key().
@@ -253,7 +260,7 @@ handle_key(struct keyevent *data)
break;
int j;
for (j=0;; j++) {
- if (j>=ARRAY_SIZE(data->keys)) {
+ if (j>=ARRAY_SIZE(old.keys)) {
// Key released.
procscankey(key, RELEASEBIT, data->modifiers);
if (i+1 >= ARRAY_SIZE(old.keys) || !old.keys[i+1])
@@ -274,7 +281,7 @@ handle_key(struct keyevent *data)
// Process new keys
procmodkey(data->modifiers & ~old.modifiers, 0);
old.modifiers = data->modifiers;
- for (i=0; i<ARRAY_SIZE(data->keys); i++) {
+ for (i=0; i<ARRAY_SIZE(old.keys); i++) {
u8 key = data->keys[i];
if (!key)
continue;
--
2.20.1
Some USB keyboards report 9 or 10-byte max packet sizes, instead
of the 8-byte max specified by the USB HID spec. Handle this by
increasing the size of the keyevent struct to 10 bytes, zeroizing
it before use, and using the key array size of the usbkeyinfo
struct as loop bounds rather than that of the keyevent struct
(since the former will always be smaller, and within spec) to
prevent buffer overflow.
Test: built/boot on Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/hw/usb-hid.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/hw/usb-hid.c b/src/hw/usb-hid.c
index fa4d9a2..bce1b5f 100644
--- a/src/hw/usb-hid.c
+++ b/src/hw/usb-hid.c
@@ -8,6 +8,7 @@
#include "config.h" // CONFIG_*
#include "output.h" // dprintf
#include "ps2port.h" // ATKBD_CMD_GETID
+#include <string.h> //memset
#include "usb.h" // usb_ctrlrequest
#include "usb-hid.h" // usb_keyboard_setup
#include "util.h" // process_key
@@ -59,8 +60,10 @@ usb_kbd_setup(struct usbdevice_s *usbdev
// XXX - this enables the first found keyboard (could be random)
return -1;
- if (epdesc->wMaxPacketSize != 8)
+ if (epdesc->wMaxPacketSize > 10) {
+ dprintf(1, "USB keyboard endpoint wMaxPacketSize > 10; aborting\n");
return -1;
+ }
// Enable "boot" protocol.
int ret = set_protocol(usbdev->defpipe, 0);
@@ -163,11 +166,15 @@ static u16 ModifierToScanCode[] VAR16 = {
#define RELEASEBIT 0x80
-// Format of USB keyboard event data
+// Format of USB keyboard event data.
+// Some keyboards use a 9/10 byte packet size,
+// so account for that here to prevent buffer
+// overflow. We'll ignore the 9th/10th bytes
+// as it's out of spec.
struct keyevent {
u8 modifiers;
u8 reserved;
- u8 keys[6];
+ u8 keys[8];
};
// Translate data from KeyToScanCode[] to calls to process_key().
@@ -253,7 +260,7 @@ handle_key(struct keyevent *data)
break;
int j;
for (j=0;; j++) {
- if (j>=ARRAY_SIZE(data->keys)) {
+ if (j>=ARRAY_SIZE(old.keys)) {
// Key released.
procscankey(key, RELEASEBIT, data->modifiers);
if (i+1 >= ARRAY_SIZE(old.keys) || !old.keys[i+1])
@@ -274,7 +281,7 @@ handle_key(struct keyevent *data)
// Process new keys
procmodkey(data->modifiers & ~old.modifiers, 0);
old.modifiers = data->modifiers;
- for (i=0; i<ARRAY_SIZE(data->keys); i++) {
+ for (i=0; i<ARRAY_SIZE(old.keys); i++) {
u8 key = data->keys[i];
if (!key)
continue;
@@ -310,6 +317,8 @@ usb_check_key(void)
for (;;) {
struct keyevent data;
+ // zeroize struct as most keyboards won't fill it
+ memset(&data, 0, sizeof(data));
int ret = usb_poll_intr(pipe, &data);
if (ret)
break;
--
2.20.1
Some USB keyboards report 9 or 10-byte max packet sizes, instead
of the 8-byte max specified by the USB HID spec. Handle this by
increasing the size of the keyevent struct to 10 bytes, zeroizing
it before use, and using the key array size of the usbkeyinfo
struct as loop bounds rather than that of the keyevent struct
(since the former will always be smaller, and within spec).
Test: built/boot on Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/hw/usb-hid.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/hw/usb-hid.c b/src/hw/usb-hid.c
index fa4d9a2..cedec0b 100644
--- a/src/hw/usb-hid.c
+++ b/src/hw/usb-hid.c
@@ -8,6 +8,7 @@
#include "config.h" // CONFIG_*
#include "output.h" // dprintf
#include "ps2port.h" // ATKBD_CMD_GETID
+#include <string.h> //memset
#include "usb.h" // usb_ctrlrequest
#include "usb-hid.h" // usb_keyboard_setup
#include "util.h" // process_key
@@ -59,7 +60,7 @@ usb_kbd_setup(struct usbdevice_s *usbdev
// XXX - this enables the first found keyboard (could be random)
return -1;
- if (epdesc->wMaxPacketSize != 8)
+ if (epdesc->wMaxPacketSize > 10)
return -1;
// Enable "boot" protocol.
@@ -163,11 +164,15 @@ static u16 ModifierToScanCode[] VAR16 = {
#define RELEASEBIT 0x80
-// Format of USB keyboard event data
+// Format of USB keyboard event data.
+// Some keyboards use a 9/10 byte packet size,
+// so account for that here to prevent buffer
+// overflow. We'll ignore the 9th/10th bytes
+// as it's out of spec.
struct keyevent {
u8 modifiers;
u8 reserved;
- u8 keys[6];
+ u8 keys[8];
};
// Translate data from KeyToScanCode[] to calls to process_key().
@@ -253,7 +258,7 @@ handle_key(struct keyevent *data)
break;
int j;
for (j=0;; j++) {
- if (j>=ARRAY_SIZE(data->keys)) {
+ if (j>=ARRAY_SIZE(old.keys)) {
// Key released.
procscankey(key, RELEASEBIT, data->modifiers);
if (i+1 >= ARRAY_SIZE(old.keys) || !old.keys[i+1])
@@ -274,7 +279,7 @@ handle_key(struct keyevent *data)
// Process new keys
procmodkey(data->modifiers & ~old.modifiers, 0);
old.modifiers = data->modifiers;
- for (i=0; i<ARRAY_SIZE(data->keys); i++) {
+ for (i=0; i<ARRAY_SIZE(old.keys); i++) {
u8 key = data->keys[i];
if (!key)
continue;
@@ -310,6 +315,8 @@ usb_check_key(void)
for (;;) {
struct keyevent data;
+ //zeroize struct as most keyboards won't fill it
+ memset(&data, 0, sizeof(data));
int ret = usb_poll_intr(pipe, &data);
if (ret)
break;
--
2.20.1
From f65c435b8e3caf7249a3fb25150e7055898ccc12 Mon Sep 17 00:00:00 2001
From: gaobin <gaobin(a)amazon.com>
Date: Fri, 18 Oct 2019 23:00:21 -0700
Subject: [PATCH 4/4] serialio: Support for pci serial ports
Some Intel PCHs integrate pci uarts which are used for serial
port debugging. For compatibility purpose, BIOS implementation
may assign 0x3f8 to the pci uart's io bar at PEI stage, later
during DXE stage the pci uart's bar is re-assigned to a different
address. As a result, we can't use the hard coded IO port 0x3f8
in SeaBIOS for debugging. Instead, we need read the port base
address from the pci uart's BAR, either an IO BAR, or a 32bit
memory BAR. This patch adds support for pci serial port debugging.
Signed-off-by: gaobin <gaobin(a)amazon.com>
---
src/Kconfig | 34 +++++++++++++++++++++++++++++++++-
src/hw/serialio.c | 29 +++++++++++++++++++++++++++--
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 6606ce4..6d9ce3b 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -550,8 +550,40 @@ menu "Debugging"
default 0x3f8
help
Base port for serial - generally 0x3f8, 0x2f8, 0x3e8, or 0x2e8.
- config DEBUG_SERIAL_MMIO
+ config DEBUG_SERIAL_PCI_IO
depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL
+ bool "Serial port debugging via PCI IO"
+ default n
+ help
+ Send debugging information to PCI serial port.
+ The base address of the uart is in the PCI device's IO bar.
+ config DEBUG_SERIAL_PCI_MEM32
+ depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO
+ bool "Serial port debugging via PCI MEM32"
+ default n
+ help
+ Send debugging information to PCI serial port.
+ The base address of the uart is in the PCI device's MEM32 bar.
+ config DEBUG_SERIAL_PCI_BDF
+ depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32
+ hex "Serial port PCI bus/device/function"
+ range 0 ffff
+ help
+ 16bit hex of B:D:F of the PCI serial port.
+ Bit 15:8 - bus, bit 7:3 - device, bit 2:0 - function
+ E.g. for a PCI device: bus 0x0, dev 0x1a, func 0x1 you
+ should input 00d1.
+ config DEBUG_SERIAL_PCI_BAR
+ depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32
+ hex "Serial port PCI BAR index (0 - 5)"
+ range 0 5
+ default 0
+ help
+ The index of the BAR where the base address would be read
+ from for the PCI serial port. Only IO BAR and 32bit memory
+ BAR are supported.
+ config DEBUG_SERIAL_MMIO
+ depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO && !DEBUG_SERIAL_PCI_MEM32
bool "Serial port debugging via memory mapped IO"
default n
help
diff --git a/src/hw/serialio.c b/src/hw/serialio.c
index 3163344..9a8565c 100644
--- a/src/hw/serialio.c
+++ b/src/hw/serialio.c
@@ -9,6 +9,7 @@
#include "output.h" // dprintf
#include "serialio.h" // serial_debug_preinit
#include "x86.h" // outb
+#include "pci.h" //pci_config_readw
/****************************************************************
@@ -23,6 +24,15 @@ serial_debug_write(u8 offset, u8 val)
{
if (CONFIG_DEBUG_SERIAL) {
outb(val, CONFIG_DEBUG_SERIAL_PORT + offset);
+ } else if (CONFIG_DEBUG_SERIAL_PCI_IO) {
+ u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF,
+ 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3);
+ outb(val, base + offset);
+ } else if (CONFIG_DEBUG_SERIAL_PCI_MEM32) {
+ ASSERT32FLAT();
+ u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF,
+ 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7);
+ writeb((void*)base + 4*offset, val);
} else if (CONFIG_DEBUG_SERIAL_MMIO) {
ASSERT32FLAT();
writeb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset, val);
@@ -35,6 +45,17 @@ serial_debug_read(u8 offset)
{
if (CONFIG_DEBUG_SERIAL)
return inb(CONFIG_DEBUG_SERIAL_PORT + offset);
+ if (CONFIG_DEBUG_SERIAL_PCI_IO) {
+ u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF,
+ 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3);
+ return inb(base + offset);
+ }
+ if (CONFIG_DEBUG_SERIAL_PCI_MEM32) {
+ ASSERT32FLAT();
+ u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF,
+ 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7);
+ return readb((void*)base + 4*offset);
+ }
if (CONFIG_DEBUG_SERIAL_MMIO) {
ASSERT32FLAT();
return readb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset);
@@ -65,7 +86,9 @@ serial_debug_preinit(void)
static void
serial_debug(char c)
{
- if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT))
+ if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO &&
+ ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) ||
+ MODESEGMENT))
return;
int timeout = DEBUG_TIMEOUT;
while ((serial_debug_read(SEROFF_LSR) & 0x20) != 0x20)
@@ -87,7 +110,9 @@ serial_debug_putc(char c)
void
serial_debug_flush(void)
{
- if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT))
+ if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO &&
+ ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) ||
+ MODESEGMENT))
return;
int timeout = DEBUG_TIMEOUT;
while ((serial_debug_read(SEROFF_LSR) & 0x60) != 0x60)
--
2.17.1
