by Paul Menzel
Dear SeaBIOS folks,
on LinuxTag 2014 the OpenMandriva project [1] gave away USB flash
storage devices with OpenMandriva installed for live booting. Testing it
out on the ASRock E350M1 with coreboot and SeaBIOS payload it was not
detected by SeaBIOS, meaning pressing F12 it was not listed in the boot
options.
Rebooting the system by pressing Ctrl + Alt + Del the USB device was
recognized by SeaBIOS and listed in the boot menu.
I am still able to reproduce this with SeaBIOS build from master. Please
find the coreboot and SeaBIOS logs attached.
Thanks,
Paul
[1] http://openmandriva.org/
by David Woodhouse
We expect to use the space between the top of option ROMs and the bottom
of our own BIOS code as a stack. OVMF was previously marking the whole
region from 0xC0000 to 0xFFFFF read-only before invoking our Legacy16Boot
method. Read-only stack considered harmful.
Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which
allow the CSM to specify a memory region that needs to be writable.
There exists CONFIG_MALLOC_UPPERMEMORY which we could turn off to use
the 9-segment, but that isn't particularly useful for the CSM case
either because that memory isn't ours to play with until the final
Legacy16Boot call. There's a LowPmmMemory given to use by UEFI to play
with, but that's right in the *middle* of low memory and using that for
persistent allocations would be painful. So just require
CONFIG_MALLOC_UPPERMEMORY when building a CSM.
Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com>
---
v2: Require CONFIG_MALLOC_UPPERMEMORY. Default UmaAddress to &zonelow_base.
src/Kconfig | 2 +-
src/fw/csm.c | 6 +++++-
src/std/LegacyBios.h | 20 ++++++++++++++++++++
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index a42ab2d..093075c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -114,7 +114,7 @@ endchoice
the BIOS in 16bit protected mode.
config MALLOC_UPPERMEMORY
- bool "Allocate memory that needs to be in first Meg above 0xc0000"
+ bool "Allocate memory that needs to be in first Meg above 0xc0000" if !CSM
default y
help
Use the "Upper Memory Block" area (0xc0000-0xf0000) for
diff --git a/src/fw/csm.c b/src/fw/csm.c
index dfb0d12..4e4b688 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -34,6 +34,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG __aligned(16) = {
.Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
.OemIdStringPointer = (u32)"SeaBIOS",
.AcpiRsdPtrPointer = (u32)&csm_rsdp,
+ .UmaAddress = (u32)&zonelow_base,
+ .UmaSize = 0x10000,
};
EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table;
@@ -46,9 +48,11 @@ extern void __csm_return(struct bregs *regs) __noreturn;
static void
csm_return(struct bregs *regs)
{
- dprintf(3, "handle_csm returning AX=%04x\n", regs->ax);
+ u32 top = rom_get_max();
PICMask = pic_irqmask_read();
+ csm_compat_table.UmaAddress = top;
+ csm_compat_table.UmaSize = 0xf0000 - top;
__csm_return(regs);
}
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h
index cf0c3c5..5170c37 100644
--- a/src/std/LegacyBios.h
+++ b/src/std/LegacyBios.h
@@ -228,6 +228,26 @@ typedef struct {
/// Maximum PCI bus number assigned.
///
UINT8 LastPciBus;
+
+ ///
+ /// Start address of UMB RAM
+ ///
+ UINT32 UmaAddress;
+
+ ///
+ /// Size of UMB RAM
+ ///
+ UINT32 UmaSize;
+
+ ///
+ /// Start address of persistent allocation in high (>1MiB) memory
+ ///
+ UINT32 HiPermanentMemoryAddress;
+
+ ///
+ /// Size of persistent allocation in high (>1MiB) memory
+ ///
+ UINT32 HiPermanentMemorySize;
} EFI_COMPATIBILITY16_TABLE;
///
--
1.8.3.1
--
David Woodhouse Open Source Technology Centre
David.Woodhouse(a)intel.com Intel Corporation
by Kevin O'Connor
On Sat, May 31, 2014 at 12:18:32PM -0400, Kevin O'Connor wrote:
> Change the multi-processor init code to trampoline into 32bit mode on
> each of the additional processors. Implement an atomic lock so that
> each processor performs its initialization serially.
>
> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
> ---
>
> Changed since v2:
> * Use "lock btsl" instead of "lock cmpxchgl" as suggested by Paolo.
> * Enable CPU caching on the APs
> * Report the apic_id in debug messages for each AP
FYI, I did try with the BSP loop in assembler (see below), but it made
the assembler slightly more complex. In theory, the comparison in
assembler would result in less lock contention, but in practice it
doesn't seem to matter. (With a small number of APs it's fast
regardless, and with a large number of APs the contention comes from
all the APs so the addition of the BSP contention is small.)
-Kevin
diff --git a/src/fw/smp.c b/src/fw/smp.c
index 51c0cae..bc5ebaf 100644
--- a/src/fw/smp.c
+++ b/src/fw/smp.c
@@ -123,17 +123,19 @@ smp_setup(void)
// Wait for other CPUs to process the SIPI.
u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1;
- while (cmos_smp_count != CountCPUs)
asm volatile(
// Release lock and allow other processors to use the stack.
" movl %%esp, %1\n"
" movl $0, %0\n"
// Reacquire lock and take back ownership of stack.
"1:rep ; nop\n"
+ " cmp %3, %2\n"
+ " jne 1b\n"
" lock btsl $0, %0\n"
" jc 1b\n"
: "+m" (SMPLock), "+m" (SMPStack)
- : : "cc", "memory");
+ : "r" (cmos_smp_count), "m" (CountCPUs)
+ : "cc", "memory");
yield();
// Restore memory.
by Kevin O'Connor
Change the multi-processor init code to trampoline into 32bit mode on
each of the additional processors. Implement an atomic lock so that
each processor performs its initialization serially.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
Changed since v2:
* Use "lock btsl" instead of "lock cmpxchgl" as suggested by Paolo.
* Enable CPU caching on the APs
* Report the apic_id in debug messages for each AP
---
Makefile | 3 +-
src/config.h | 1 +
src/fw/smp.c | 102 ++++++++++++++++++++++++++++----------------------------
src/romlayout.S | 20 +++++++++++
src/util.h | 1 -
5 files changed, 73 insertions(+), 54 deletions(-)
diff --git a/Makefile b/Makefile
index 78b598e..fb4e683 100644
--- a/Makefile
+++ b/Makefile
@@ -29,7 +29,6 @@ LD32BIT_FLAG:=-melf_i386
# Source files
SRCBOTH=misc.c stacks.c output.c string.c x86.c block.c cdrom.c mouse.c kbd.c \
serial.c clock.c resume.c pnpbios.c vgahooks.c pcibios.c apm.c \
- fw/smp.c \
hw/pci.c hw/timer.c hw/rtc.c hw/dma.c hw/pic.c hw/ps2port.c hw/serialio.c \
hw/usb.c hw/usb-uhci.c hw/usb-ohci.c hw/usb-ehci.c \
hw/usb-hid.c hw/usb-msc.c hw/usb-uas.c \
@@ -41,7 +40,7 @@ SRC32FLAT=$(SRCBOTH) post.c memmap.c malloc.c pmm.c romfile.c optionroms.c \
boot.c bootsplash.c jpeg.c bmp.c \
hw/ahci.c hw/pvscsi.c hw/usb-xhci.c hw/usb-hub.c \
fw/coreboot.c fw/lzmadecode.c fw/csm.c fw/biostables.c \
- fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/mtrr.c fw/xen.c \
+ fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c fw/xen.c \
fw/acpi.c fw/mptable.c fw/pirtable.c fw/smbios.c fw/romfile_loader.c
SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c
DIRS=src src/hw src/fw vgasrc
diff --git a/src/config.h b/src/config.h
index 6f1a5b9..6da067d 100644
--- a/src/config.h
+++ b/src/config.h
@@ -95,6 +95,7 @@
#define DEBUG_ISR_hwpic1 5
#define DEBUG_ISR_hwpic2 5
#define DEBUG_HDL_smi 9
+#define DEBUG_HDL_smp 1
#define DEBUG_HDL_pnp 1
#define DEBUG_HDL_pmm 1
#define DEBUG_HDL_pcibios 9
diff --git a/src/fw/smp.c b/src/fw/smp.c
index 38fe383..51c0cae 100644
--- a/src/fw/smp.c
+++ b/src/fw/smp.c
@@ -1,4 +1,4 @@
-// CPU count detection
+// QEMU multi-CPU initialization code
//
// Copyright (C) 2008 Kevin O'Connor <kevin(a)koconnor.net>
// Copyright (C) 2006 Fabrice Bellard
@@ -20,8 +20,8 @@
#define APIC_ENABLED 0x0100
-struct { u32 ecx, eax, edx; } smp_mtrr[32] VARFSEG;
-u32 smp_mtrr_count VARFSEG;
+static struct { u32 index; u64 val; } smp_mtrr[32];
+static u32 smp_mtrr_count;
void
wrmsr_smp(u32 index, u64 val)
@@ -31,52 +31,40 @@ wrmsr_smp(u32 index, u64 val)
warn_noalloc();
return;
}
- smp_mtrr[smp_mtrr_count].ecx = index;
- smp_mtrr[smp_mtrr_count].eax = val;
- smp_mtrr[smp_mtrr_count].edx = val >> 32;
+ smp_mtrr[smp_mtrr_count].index = index;
+ smp_mtrr[smp_mtrr_count].val = val;
smp_mtrr_count++;
}
-u32 CountCPUs VARFSEG;
u32 MaxCountCPUs;
+static u32 CountCPUs;
+u32 SMPLock __VISIBLE;
+u32 SMPStack __VISIBLE;
// 256 bits for the found APIC IDs
-u32 FoundAPICIDs[256/32] VARFSEG;
-extern void smp_ap_boot_code(void);
-ASM16(
- " .global smp_ap_boot_code\n"
- "smp_ap_boot_code:\n"
+static u32 FoundAPICIDs[256/32];
- // Setup data segment
- " movw $" __stringify(SEG_BIOS) ", %ax\n"
- " movw %ax, %ds\n"
+void VISIBLE32FLAT
+handle_smp(void)
+{
+ // Enable CPU caching
+ setcr0(getcr0() & ~(CR0_CD|CR0_NW));
+
+ // Detect apic_id
+ u32 eax, ebx, ecx, cpuid_features;
+ cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
+ u8 apic_id = ebx>>24;
+ dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id);
// MTRR setup
- " movl $smp_mtrr, %esi\n"
- " movl smp_mtrr_count, %ebx\n"
- "1:testl %ebx, %ebx\n"
- " jz 2f\n"
- " movl 0(%esi), %ecx\n"
- " movl 4(%esi), %eax\n"
- " movl 8(%esi), %edx\n"
- " wrmsr\n"
- " addl $12, %esi\n"
- " decl %ebx\n"
- " jmp 1b\n"
- "2:\n"
-
- // get apic ID on EBX, set bit on FoundAPICIDs
- " movl $1, %eax\n"
- " cpuid\n"
- " shrl $24, %ebx\n"
- " lock btsl %ebx, FoundAPICIDs\n"
-
- // Increment the cpu counter
- " lock incl CountCPUs\n"
-
- // Halt the processor.
- "1:hlt\n"
- " jmp 1b\n"
- );
+ int i;
+ for (i=0; i<smp_mtrr_count; i++)
+ wrmsr(smp_mtrr[i].index, smp_mtrr[i].val);
+
+ // Set bit on FoundAPICIDs
+ FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32));
+
+ CountCPUs++;
+}
int apic_id_is_present(u8 apic_id)
{
@@ -104,15 +92,14 @@ smp_setup(void)
// mark the BSP initial APIC ID as found, too:
u8 apic_id = ebx>>24;
FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32));
-
- // Init the counter.
- writel(&CountCPUs, 1);
+ CountCPUs = 1;
// Setup jump trampoline to counter code.
u64 old = *(u64*)BUILD_AP_BOOT_ADDR;
- // ljmpw $SEG_BIOS, $(smp_ap_boot_code - BUILD_BIOS_ADDR)
+ // ljmpw $SEG_BIOS, $(entry_smp - BUILD_BIOS_ADDR)
+ extern void entry_smp(void);
u64 new = (0xea | ((u64)SEG_BIOS<<24)
- | (((u32)smp_ap_boot_code - BUILD_BIOS_ADDR) << 8));
+ | (((u32)entry_smp - BUILD_BIOS_ADDR) << 8));
*(u64*)BUILD_AP_BOOT_ADDR = new;
// enable local APIC
@@ -125,6 +112,9 @@ smp_setup(void)
/* Set LINT1 as NMI, level triggered */
writel(APIC_LINT1, 0x8400);
+ // Init the lock.
+ writel(&SMPLock, 1);
+
// broadcast SIPI
barrier();
writel(APIC_ICR_LOW, 0x000C4500);
@@ -132,9 +122,19 @@ smp_setup(void)
writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
// Wait for other CPUs to process the SIPI.
- u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT);
- while (cmos_smp_count + 1 != readl(&CountCPUs))
- yield();
+ u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1;
+ while (cmos_smp_count != CountCPUs)
+ asm volatile(
+ // Release lock and allow other processors to use the stack.
+ " movl %%esp, %1\n"
+ " movl $0, %0\n"
+ // Reacquire lock and take back ownership of stack.
+ "1:rep ; nop\n"
+ " lock btsl $0, %0\n"
+ " jc 1b\n"
+ : "+m" (SMPLock), "+m" (SMPStack)
+ : : "cc", "memory");
+ yield();
// Restore memory.
*(u64*)BUILD_AP_BOOT_ADDR = old;
@@ -143,6 +143,6 @@ smp_setup(void)
if (!MaxCountCPUs || MaxCountCPUs < CountCPUs)
MaxCountCPUs = CountCPUs;
- dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", readl(&CountCPUs),
- MaxCountCPUs);
+ dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", CountCPUs,
+ MaxCountCPUs);
}
diff --git a/src/romlayout.S b/src/romlayout.S
index 0d6af39..4922279 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -274,6 +274,26 @@ entry_smi:
rsm
.code16gcc
+// Entry point for QEMU smp sipi interrupts.
+ DECLFUNC entry_smp
+entry_smp:
+ // Transition to 32bit mode.
+ movl $2f + BUILD_BIOS_ADDR, %edx
+ jmp transition32
+ .code32
+ // Acquire lock and take ownership of shared stack
+1: rep nop
+2: lock btsl $0, SMPLock
+ jc 1b
+ movl SMPStack, %esp
+ // Call handle_smp
+ calll _cfunc32flat_handle_smp - BUILD_BIOS_ADDR
+ // Release lock and halt processor.
+ movl $0, SMPLock
+3: hlt
+ jmp 3b
+ .code16gcc
+
// Resume (and reboot) entry point - called from entry_post
DECLFUNC entry_resume
entry_resume:
diff --git a/src/util.h b/src/util.h
index b54271b..8c794c4 100644
--- a/src/util.h
+++ b/src/util.h
@@ -126,7 +126,6 @@ void smm_device_setup(void);
void smm_setup(void);
// fw/smp.c
-extern u32 CountCPUs;
extern u32 MaxCountCPUs;
void wrmsr_smp(u32 index, u64 val);
void smp_setup(void);
--
1.9.3
by Paolo Bonzini
Il 31/05/2014 03:20, Kevin O'Connor ha scritto:
> Change the multi-processor init code to trampoline into 32bit mode on
> each of the additional processors. Implement an atomic lock so that
> each processor performs its initialization serially.
I don't see much benefit in this change, in fact the new code is more
complex than the old one... But anyway, if you prefer to go this way I
have just a couple observations on the patch:
1) acquiring the lock can be done simply by a "1: lock btsl; jc 1b"; no
need to use the cmpxchg.
2) There's no need to acquire the lock repeatedly in the BSP, I think
writing the loop in assembly is acceptable:
asm volatile(
"movl %%esp, %1\n"
// Release lock, other processors use the stack now
"mov $0, %0\n"
"1: cmp %3, %2\n"
"rep; nop\n"
"jne 1b\n"
// Reacquire lock; last processor is still using the stack!
"1b: lock btsl $0, %0\n"
"rep; nop\n"
"jc 1b\n" :
"+m" (SMPLock), "=m" (SMPStack) : "r" (cmos_smp_count),
"m" (CountCPUs) : "cc", "memory");
Paolo
> + : "+m" (SMPLock), "+m" (SMPStack), "=&a" (eax)
> + : "r" (lockval)
> + : "cc", "memory");
> + yield();
>
> // Restore memory.
> *(u64*)BUILD_AP_BOOT_ADDR = old;
> @@ -143,6 +142,6 @@ smp_setup(void)
> if (!MaxCountCPUs || MaxCountCPUs < CountCPUs)
> MaxCountCPUs = CountCPUs;
>
> - dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", readl(&CountCPUs),
> - MaxCountCPUs);
> + dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", CountCPUs,
> + MaxCountCPUs);
> }
> diff --git a/src/romlayout.S b/src/romlayout.S
> index 0d6af39..bee3943 100644
> --- a/src/romlayout.S
> +++ b/src/romlayout.S
> @@ -274,6 +274,29 @@ entry_smi:
> rsm
> .code16gcc
>
> +// Entry point for QEMU smp sipi interrupts.
> + DECLFUNC entry_smp
> +entry_smp:
> + // Transition to 32bit mode.
> + movl $1f + BUILD_BIOS_ADDR, %edx
> + jmp transition32
> + .code32
> + // Acquire lock
> +1: movl $1, %ecx
> +2: xorl %eax, %eax
> + lock cmpxchgl %ecx, SMPLock
> + jz 3f
> + rep nop
> + jmp 2b
> + // Setup stack and call handle_smp
> +3: movl SMPStack, %esp
> + calll _cfunc32flat_handle_smp - BUILD_BIOS_ADDR
> + // Release lock and halt processor.
> + movl $0, SMPLock
> +4: hlt
> + jmp 4b
> + .code16gcc
> +
> // Resume (and reboot) entry point - called from entry_post
> DECLFUNC entry_resume
> entry_resume:
> diff --git a/src/util.h b/src/util.h
> index b54271b..8c794c4 100644
> --- a/src/util.h
> +++ b/src/util.h
> @@ -126,7 +126,6 @@ void smm_device_setup(void);
> void smm_setup(void);
>
> // fw/smp.c
> -extern u32 CountCPUs;
> extern u32 MaxCountCPUs;
> void wrmsr_smp(u32 index, u64 val);
> void smp_setup(void);
>
by Paul Menzel
Dear Kevin,
thank you for the patch.
Am Freitag, den 30.05.2014, 21:47 -0400 schrieb Kevin O'Connor:
> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
> ---
> src/stacks.c |
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/stacks.c b/src/stacks.c
> index 6bcb319..beccc0f 100644
> --- a/src/stacks.c
> +++ b/src/stacks.c
> @@ -287,7 +287,7 @@ thread_init(void)
> int
> threads_during_optionroms(void)
> {
> - return CONFIG_THREADS && ThreadControl == 2;
> + return CONFIG_THREADS && ThreadControl == 2 && in_post();
> }
>
> // Switch to next thread stack.
What problem did it cause and on what systems?
Thanks,
Paul
by Kevin O'Connor
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/disk.c | 3 ---
src/hw/floppy.c | 2 --
src/misc.c | 8 ++++++++
src/serial.c | 3 ---
src/util.h | 1 +
5 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/disk.c b/src/disk.c
index 2aadd8a..fe2e2c3 100644
--- a/src/disk.c
+++ b/src/disk.c
@@ -744,6 +744,3 @@ handle_76(void)
SET_BDA(disk_interrupt_flag, 0xff);
pic_eoi2();
}
-
-// Old Fixed Disk Parameter Table (newer tables are in the ebda).
-struct fdpt_s OldFDPT VAR16FIXED(0xe401);
diff --git a/src/hw/floppy.c b/src/hw/floppy.c
index f4d7c01..aa8583d 100644
--- a/src/hw/floppy.c
+++ b/src/hw/floppy.c
@@ -58,8 +58,6 @@ struct floppy_ext_dbt_s diskette_param_table2 VARFSEG = {
.drive_type = 4, // drive type in cmos
};
-struct floppy_dbt_s diskette_param_table VAR16FIXED(0xefc7);
-
struct floppyinfo_s {
struct chs_s chs;
u8 floppy_size;
diff --git a/src/misc.c b/src/misc.c
index 21693fc..889064a 100644
--- a/src/misc.c
+++ b/src/misc.c
@@ -188,6 +188,14 @@ u8 BiosModelId VAR16FIXED(0xfffe) = BUILD_MODEL_ID;
u8 BiosChecksum VAR16FIXED(0xffff);
+struct floppy_dbt_s diskette_param_table VAR16FIXED(0xefc7);
+
+// Old Fixed Disk Parameter Table (newer tables are in the ebda).
+struct fdpt_s OldFDPT VAR16FIXED(0xe401);
+
+// XXX - Baud Rate Generator Table
+u8 BaudTable[16] VAR16FIXED(0xe729);
+
// XXX - Initial Interrupt Vector Offsets Loaded by POST
u8 InitVectors[13] VAR16FIXED(0xfef3);
diff --git a/src/serial.c b/src/serial.c
index 00c6eb7..88349c8 100644
--- a/src/serial.c
+++ b/src/serial.c
@@ -181,9 +181,6 @@ handle_14(struct bregs *regs)
}
}
-// XXX - Baud Rate Generator Table
-u8 BaudTable[16] VAR16FIXED(0xe729);
-
/****************************************************************
* LPT ports
diff --git a/src/util.h b/src/util.h
index e7c9ff9..8b078e8 100644
--- a/src/util.h
+++ b/src/util.h
@@ -176,6 +176,7 @@ void process_key(u8 key);
// misc.c
extern struct bios_config_table_s BIOS_CONFIG_TABLE __aligned(1);
+extern struct floppy_dbt_s diskette_param_table __aligned(1);
extern u8 BiosChecksum;
int in_post(void);
void mathcp_setup(void);
--
1.9.3
by Kevin O'Connor
There is no indication that the address 0xff00 is a BIOS standard, so
don't emit the old Bochs copyright string at that fixed address.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/misc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/misc.c b/src/misc.c
index 6712355..21693fc 100644
--- a/src/misc.c
+++ b/src/misc.c
@@ -181,9 +181,6 @@ struct descloc_s rombios32_gdt_48 VARFSEG = {
* Misc fixed vars
****************************************************************/
-char BiosCopyright[] VAR16FIXED(0xff00) =
- "(c) 2002 MandrakeSoft S.A. Written by Kevin Lawton & the Bochs team.";
-
// BIOS build date
char BiosDate[] VAR16FIXED(0xfff5) = "06/23/99";
--
1.9.3
by Kevin O'Connor
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/stacks.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/stacks.c b/src/stacks.c
index 6bcb319..beccc0f 100644
--- a/src/stacks.c
+++ b/src/stacks.c
@@ -287,7 +287,7 @@ thread_init(void)
int
threads_during_optionroms(void)
{
- return CONFIG_THREADS && ThreadControl == 2;
+ return CONFIG_THREADS && ThreadControl == 2 && in_post();
}
// Switch to next thread stack.
--
1.9.3
by Kevin O'Connor
Change the multi-processor init code to trampoline into 32bit mode on
each of the additional processors. Implement an atomic lock so that
each processor performs its initialization serially.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
Makefile | 3 +-
src/config.h | 1 +
src/fw/smp.c | 101 ++++++++++++++++++++++++++++----------------------------
src/romlayout.S | 23 +++++++++++++
src/util.h | 1 -
5 files changed, 75 insertions(+), 54 deletions(-)
diff --git a/Makefile b/Makefile
index 78b598e..fb4e683 100644
--- a/Makefile
+++ b/Makefile
@@ -29,7 +29,6 @@ LD32BIT_FLAG:=-melf_i386
# Source files
SRCBOTH=misc.c stacks.c output.c string.c x86.c block.c cdrom.c mouse.c kbd.c \
serial.c clock.c resume.c pnpbios.c vgahooks.c pcibios.c apm.c \
- fw/smp.c \
hw/pci.c hw/timer.c hw/rtc.c hw/dma.c hw/pic.c hw/ps2port.c hw/serialio.c \
hw/usb.c hw/usb-uhci.c hw/usb-ohci.c hw/usb-ehci.c \
hw/usb-hid.c hw/usb-msc.c hw/usb-uas.c \
@@ -41,7 +40,7 @@ SRC32FLAT=$(SRCBOTH) post.c memmap.c malloc.c pmm.c romfile.c optionroms.c \
boot.c bootsplash.c jpeg.c bmp.c \
hw/ahci.c hw/pvscsi.c hw/usb-xhci.c hw/usb-hub.c \
fw/coreboot.c fw/lzmadecode.c fw/csm.c fw/biostables.c \
- fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/mtrr.c fw/xen.c \
+ fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c fw/xen.c \
fw/acpi.c fw/mptable.c fw/pirtable.c fw/smbios.c fw/romfile_loader.c
SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c
DIRS=src src/hw src/fw vgasrc
diff --git a/src/config.h b/src/config.h
index 6f1a5b9..6da067d 100644
--- a/src/config.h
+++ b/src/config.h
@@ -95,6 +95,7 @@
#define DEBUG_ISR_hwpic1 5
#define DEBUG_ISR_hwpic2 5
#define DEBUG_HDL_smi 9
+#define DEBUG_HDL_smp 1
#define DEBUG_HDL_pnp 1
#define DEBUG_HDL_pmm 1
#define DEBUG_HDL_pcibios 9
diff --git a/src/fw/smp.c b/src/fw/smp.c
index 38fe383..c8b48b6 100644
--- a/src/fw/smp.c
+++ b/src/fw/smp.c
@@ -1,4 +1,4 @@
-// CPU count detection
+// QEMU multi-CPU initialization code
//
// Copyright (C) 2008 Kevin O'Connor <kevin(a)koconnor.net>
// Copyright (C) 2006 Fabrice Bellard
@@ -20,8 +20,8 @@
#define APIC_ENABLED 0x0100
-struct { u32 ecx, eax, edx; } smp_mtrr[32] VARFSEG;
-u32 smp_mtrr_count VARFSEG;
+static struct { u32 index; u64 val; } smp_mtrr[32];
+static u32 smp_mtrr_count;
void
wrmsr_smp(u32 index, u64 val)
@@ -31,52 +31,36 @@ wrmsr_smp(u32 index, u64 val)
warn_noalloc();
return;
}
- smp_mtrr[smp_mtrr_count].ecx = index;
- smp_mtrr[smp_mtrr_count].eax = val;
- smp_mtrr[smp_mtrr_count].edx = val >> 32;
+ smp_mtrr[smp_mtrr_count].index = index;
+ smp_mtrr[smp_mtrr_count].val = val;
smp_mtrr_count++;
}
-u32 CountCPUs VARFSEG;
u32 MaxCountCPUs;
+static u32 CountCPUs;
+u32 SMPLock __VISIBLE;
+u32 SMPStack __VISIBLE;
// 256 bits for the found APIC IDs
-u32 FoundAPICIDs[256/32] VARFSEG;
-extern void smp_ap_boot_code(void);
-ASM16(
- " .global smp_ap_boot_code\n"
- "smp_ap_boot_code:\n"
+static u32 FoundAPICIDs[256/32];
- // Setup data segment
- " movw $" __stringify(SEG_BIOS) ", %ax\n"
- " movw %ax, %ds\n"
+void VISIBLE32FLAT
+handle_smp(void)
+{
+ dprintf(DEBUG_HDL_smp, "handle_smp\n");
// MTRR setup
- " movl $smp_mtrr, %esi\n"
- " movl smp_mtrr_count, %ebx\n"
- "1:testl %ebx, %ebx\n"
- " jz 2f\n"
- " movl 0(%esi), %ecx\n"
- " movl 4(%esi), %eax\n"
- " movl 8(%esi), %edx\n"
- " wrmsr\n"
- " addl $12, %esi\n"
- " decl %ebx\n"
- " jmp 1b\n"
- "2:\n"
-
- // get apic ID on EBX, set bit on FoundAPICIDs
- " movl $1, %eax\n"
- " cpuid\n"
- " shrl $24, %ebx\n"
- " lock btsl %ebx, FoundAPICIDs\n"
-
- // Increment the cpu counter
- " lock incl CountCPUs\n"
-
- // Halt the processor.
- "1:hlt\n"
- " jmp 1b\n"
- );
+ int i;
+ for (i=0; i<smp_mtrr_count; i++)
+ wrmsr(smp_mtrr[i].index, smp_mtrr[i].val);
+
+ // Set bit on FoundAPICIDs
+ u32 eax, ebx, ecx, cpuid_features;
+ cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
+ u8 apic_id = ebx>>24;
+ FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32));
+
+ CountCPUs++;
+}
int apic_id_is_present(u8 apic_id)
{
@@ -104,15 +88,14 @@ smp_setup(void)
// mark the BSP initial APIC ID as found, too:
u8 apic_id = ebx>>24;
FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32));
-
- // Init the counter.
- writel(&CountCPUs, 1);
+ CountCPUs = 1;
// Setup jump trampoline to counter code.
u64 old = *(u64*)BUILD_AP_BOOT_ADDR;
- // ljmpw $SEG_BIOS, $(smp_ap_boot_code - BUILD_BIOS_ADDR)
+ // ljmpw $SEG_BIOS, $(entry_smp - BUILD_BIOS_ADDR)
+ extern void entry_smp(void);
u64 new = (0xea | ((u64)SEG_BIOS<<24)
- | (((u32)smp_ap_boot_code - BUILD_BIOS_ADDR) << 8));
+ | (((u32)entry_smp - BUILD_BIOS_ADDR) << 8));
*(u64*)BUILD_AP_BOOT_ADDR = new;
// enable local APIC
@@ -125,6 +108,9 @@ smp_setup(void)
/* Set LINT1 as NMI, level triggered */
writel(APIC_LINT1, 0x8400);
+ // Init the lock.
+ writel(&SMPLock, 1);
+
// broadcast SIPI
barrier();
writel(APIC_ICR_LOW, 0x000C4500);
@@ -132,9 +118,22 @@ smp_setup(void)
writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
// Wait for other CPUs to process the SIPI.
- u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT);
- while (cmos_smp_count + 1 != readl(&CountCPUs))
- yield();
+ u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1;
+ u32 lockval = 1;
+ while (cmos_smp_count != CountCPUs)
+ asm volatile(
+ // Store %esp value and unlock.
+ " movl %%esp, %1\n"
+ " movl $0, %0\n"
+ // Reacquire lock.
+ "1:rep ; nop\n"
+ " xorl %2, %2\n"
+ " lock cmpxchgl %3, %0\n"
+ " jnz 1b\n"
+ : "+m" (SMPLock), "+m" (SMPStack), "=&a" (eax)
+ : "r" (lockval)
+ : "cc", "memory");
+ yield();
// Restore memory.
*(u64*)BUILD_AP_BOOT_ADDR = old;
@@ -143,6 +142,6 @@ smp_setup(void)
if (!MaxCountCPUs || MaxCountCPUs < CountCPUs)
MaxCountCPUs = CountCPUs;
- dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", readl(&CountCPUs),
- MaxCountCPUs);
+ dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", CountCPUs,
+ MaxCountCPUs);
}
diff --git a/src/romlayout.S b/src/romlayout.S
index 0d6af39..bee3943 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -274,6 +274,29 @@ entry_smi:
rsm
.code16gcc
+// Entry point for QEMU smp sipi interrupts.
+ DECLFUNC entry_smp
+entry_smp:
+ // Transition to 32bit mode.
+ movl $1f + BUILD_BIOS_ADDR, %edx
+ jmp transition32
+ .code32
+ // Acquire lock
+1: movl $1, %ecx
+2: xorl %eax, %eax
+ lock cmpxchgl %ecx, SMPLock
+ jz 3f
+ rep nop
+ jmp 2b
+ // Setup stack and call handle_smp
+3: movl SMPStack, %esp
+ calll _cfunc32flat_handle_smp - BUILD_BIOS_ADDR
+ // Release lock and halt processor.
+ movl $0, SMPLock
+4: hlt
+ jmp 4b
+ .code16gcc
+
// Resume (and reboot) entry point - called from entry_post
DECLFUNC entry_resume
entry_resume:
diff --git a/src/util.h b/src/util.h
index b54271b..8c794c4 100644
--- a/src/util.h
+++ b/src/util.h
@@ -126,7 +126,6 @@ void smm_device_setup(void);
void smm_setup(void);
// fw/smp.c
-extern u32 CountCPUs;
extern u32 MaxCountCPUs;
void wrmsr_smp(u32 index, u64 val);
void smp_setup(void);
--
1.9.3
