Hi,
Quite a few changes accumulated in master. Time to plan a new release
I think, so we can pick up the improvements in qemu 2.11.
Comments?
Anything pending for qemu which needs firmware support?
cheers,
Gerd
Dear SeaBIOS folks,
GCC 7.1 warns about a maybe uninitialized struct member.
```
src/tcgbios.c: In function 'tpm_interrupt_handler32':
src/tcgbios.c:1232:30: warning: 'hleo.eventnumber' may be used
uninitialized in this function [-Wmaybe-uninitialized]
hleeo->eventnumber = hleo.eventnumber;
~~~~^~~~~~~~~~~~
Compiling whole program out/ccode32flat.o
In file included from out/ccode32flat.o.tmp.c:52:0:
./src/tcgbios.c: In function 'tpm_interrupt_handler32':
./src/tcgbios.c:1232:30: warning: 'hleo.eventnumber' may be used
uninitialized in this function [-Wmaybe-uninitialized]
hleeo->eventnumber = hleo.eventnumber;
~~~~^~~~~~~~~~~~
```
It looks valid, as in the beginning the struct hleo is only declared.
```
1189 struct hleo hleo;
```
Kind regards,
Paul
This patch series adds serial console support to seabios. Patches 1-4
add some bits the serial console patch depends on. Patch 5 adds the
actual serial console support, for both primary display mode and
splitmode (running in parallel to a vga display).
The recommended way to activate the serial console is "qemu -machine
graphics=no".
Patch 6 is just for testing convenience and will not be merged. It
makes the seabios serial console a drop-in replacement for sgabios,
i.e. it is possible to activate it using "qemu -device sga".
Gerd Hoffmann (6):
std: add cp437 to unicode map
kbd: make enqueue_key public, add ascii_to_keycode
romfile: add support for constant files.
paravirt: serial console configuration.
add serial console support
[hack] ignore sgabios, enable sercon instead
Makefile | 3 +-
src/config.h | 1 -
src/cp437.h | 1 +
src/romfile.h | 2 +
src/util.h | 6 +
src/clock.c | 1 +
src/cp437.c | 275 ++++++++++++++++++++++
src/fw/paravirt.c | 8 +
src/kbd.c | 18 +-
src/misc.c | 8 -
src/optionroms.c | 16 +-
src/post.c | 2 +
src/romfile.c | 46 ++++
src/sercon.c | 673 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
src/Kconfig | 5 +
src/romlayout.S | 50 +++-
16 files changed, 1097 insertions(+), 18 deletions(-)
create mode 100644 src/cp437.h
create mode 100644 src/cp437.c
create mode 100644 src/sercon.c
--
2.9.3
This series updates the generic code so that either "low" memory or
the f-segment can be used for storing drive mapping information. It
also updates the virtio code to use "low" memory for its allocations.
I think there is a good chance this series will, in practice, avoid
running out of memory when a large number of virtio drives are
available.
There are other ways to tackle this problem (eg, more of the virtio
storage could be moved into "high" memory), but I think this approach
has the benefit of avoiding a "big bang" patch series.
Comments welcome.
-Kevin
Kevin O'Connor (4):
boot: Rename drive_g to drive
disk: Don't require the 'struct drive_s' to be in the f-segment
block: Rename disk_op_s->drive_gf to drive_fl
virtio: Allocate drive_s storage in low memory
src/block.c | 36 ++++-----
src/block.h | 2 +-
src/boot.c | 16 ++--
src/cdrom.c | 6 +-
src/disk.c | 218 +++++++++++++++++++++++++--------------------------
src/hw/ahci.c | 4 +-
src/hw/ata.c | 26 +++---
src/hw/blockcmd.c | 10 +--
src/hw/esp-scsi.c | 2 +-
src/hw/floppy.c | 20 ++---
src/hw/lsi-scsi.c | 2 +-
src/hw/megasas.c | 2 +-
src/hw/mpt-scsi.c | 2 +-
src/hw/nvme.c | 2 +-
src/hw/pvscsi.c | 2 +-
src/hw/ramdisk.c | 2 +-
src/hw/sdcard.c | 2 +-
src/hw/usb-msc.c | 4 +-
src/hw/usb-uas.c | 2 +-
src/hw/virtio-blk.c | 14 ++--
src/hw/virtio-ring.c | 1 -
src/hw/virtio-scsi.c | 5 +-
22 files changed, 189 insertions(+), 191 deletions(-)
--
2.9.4
The first patch fixes a regression where many disks on a single SCSI
target could prevent LUN0 from booting on another target.
The second patch then exploits the new scanning algorithm to speed up
the bus scan on virtio-scsi, which has a higher limit for the target
than the other adaptors and therefore was slowed down the most.
Paolo Bonzini (2):
scsi: ensure LUN0 is added first
virtio-scsi: speed up SCSI bus scan
src/hw/blockcmd.c | 6 ++++--
src/hw/esp-scsi.c | 10 ++++++++--
src/hw/lsi-scsi.c | 10 ++++++++--
src/hw/mpt-scsi.c | 10 ++++++++--
src/hw/usb-uas.c | 1 +
src/hw/virtio-scsi.c | 46 ++++++++++++++++++++++++++++++++++++++--------
6 files changed, 67 insertions(+), 16 deletions(-)
--
2.13.0
On Wed, Sep 20, 2017 at 09:52:01AM +0000, Aleksandr Bezzubikov wrote:
> ср, 20 сент. 2017 г. в 10:13, Marcel Apfelbaum <marcel(a)redhat.com>:
>
> > On 19/09/2017 23:34, Eduardo Habkost wrote:
> > > On Fri, Aug 18, 2017 at 02:36:47AM +0300, Aleksandr Bezzubikov wrote:
> > >> Introduce a new PCIExpress-to-PCI Bridge device,
> > >> which is a hot-pluggable PCI Express device and
> > >> supports devices hot-plug with SHPC.
> > >>
> > >> This device is intended to replace the DMI-to-PCI Bridge.
> > >>
> > >> Signed-off-by: Aleksandr Bezzubikov <zuban32s(a)gmail.com>
> > >> Reviewed-by: Marcel Apfelbaum <marcel(a)redhat.com>
> > >
> > > It's possible to crash QEMU by instantiating this device, with;
> > >
> > > $ qemu-system-ppc64 -machine prep -device pcie-pci-bridge
> > > qemu-system-ppc64: qemu/memory.c:1533: memory_region_finalize:
> > Assertion `!mr->container' failed.
> > > Aborted
> >
> > Hi Edurado,
> >
> > >
> > > I didn't investigate the root cause.
> > >
> >
> > Thanks for reporting it!
> > Aleksandr, can you have a look? Maybe we should not compile
> > the device for ppc arch. (x86 and arm is enough)
>
>
> I will see what can we do. Is x86 and arm really enough?
I would investigate the original cause before disabling the device on other
architectures, as we could be hiding a bug that's also present in x86. The
backtrace looks like broken error handling logic somewhere:
#0 0x00007fffea9ff1f7 in __GI_raise (sig=sig@entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56
#1 0x00007fffeaa008e8 in __GI_abort () at abort.c:90
#2 0x00007fffea9f8266 in __assert_fail_base (fmt=0x7fffeab4ae68 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n", assertion=assertion@entry=0x555555be4ac1 "!mr->container", file=file@entry=0x555555be49c4 "/root/qemu/memory.c", line=line@entry=1533, function=function@entry=0x555555be5100 <__PRETTY_FUNCTION__.28908> "memory_region_finalize") at assert.c:92
#3 0x00007fffea9f8312 in __GI___assert_fail (assertion=assertion@entry=0x555555be4ac1 "!mr->container", file=file@entry=0x555555be49c4 "/root/qemu/memory.c", line=line@entry=1533, function=function@entry=0x555555be5100 <__PRETTY_FUNCTION__.28908> "memory_region_finalize") at assert.c:101
#4 0x00005555557ff2df in memory_region_finalize (obj=<optimized out>) at /root/qemu/memory.c:1533
#5 0x0000555555ae77a2 in object_unref (type=<optimized out>, obj=0x555557c00d80) at /root/qemu/qom/object.c:453
#6 0x0000555555ae77a2 in object_unref (data=0x555557c00d80) at /root/qemu/qom/object.c:467
#7 0x0000555555ae77a2 in object_unref (obj=0x555557c00d80) at /root/qemu/qom/object.c:902
#8 0x0000555555ae67d7 in object_property_del_child (obj=0x555557ab6500, child=child@entry=0x555557c00d80, errp=0x0) at /root/qemu/qom/object.c:427
#9 0x0000555555ae6ff4 in object_unparent (obj=obj@entry=0x555557c00d80) at /root/qemu/qom/object.c:446
#10 0x0000555555a1c94e in shpc_free (d=d@entry=0x555557ab6500) at /root/qemu/hw/pci/shpc.c:676
#11 0x0000555555a12560 in pcie_pci_bridge_realize (d=0x555557ab6500, errp=0x7fffffffd530) at /root/qemu/hw/pci-bridge/pcie_pci_bridge.c:84
#12 0x0000555555a18d07 in pci_qdev_realize (qdev=0x555557ab6500, errp=0x7fffffffd5d0) at /root/qemu/hw/pci/pci.c:2024
#13 0x00005555559b53aa in device_set_realized (obj=<optimized out>, value=<optimized out>, errp=0x7fffffffd708) at /root/qemu/hw/core/qdev.c:914
#14 0x0000555555ae62fe in property_set_bool (obj=0x555557ab6500, v=<optimized out>, name=<optimized out>, opaque=0x555557ab7b30, errp=0x7fffffffd708) at /root/qemu/qom/object.c:1886
#15 0x0000555555aea3ef in object_property_set_qobject (obj=obj@entry=0x555557ab6500, value=value@entry=0x555557ab86b0, name=name@entry=0x555555c4f217 "realized", errp=errp@entry=0x7fffffffd708) at /root/qemu/qom/qom-qobject.c:27
#16 0x0000555555ae80a0 in object_property_set_bool (obj=0x555557ab6500, value=<optimized out>, name=0x555555c4f217 "realized", errp=0x7fffffffd708) at /root/qemu/qom/object.c:1162
#17 0x0000555555949824 in qdev_device_add (opts=0x5555567795b0, errp=errp@entry=0x7fffffffd7e0) at /root/qemu/qdev-monitor.c:630
#18 0x000055555594be87 in device_init_func (opaque=<optimized out>, opts=<optimized out>, errp=<optimized out>) at /root/qemu/vl.c:2418
#19 0x0000555555bc85ba in qemu_opts_foreach (list=<optimized out>, func=func@entry=0x55555594be60 <device_init_func>, opaque=opaque@entry=0x0, errp=errp@entry=0x0) at /root/qemu/util/qemu-option.c:1104
#20 0x000055555579f497 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at /root/qemu/vl.c:4745
(gdb) fr 11
#11 0x0000555555a12560 in pcie_pci_bridge_realize (d=0x555557ab6500, errp=0x7fffffffd530) at /root/qemu/hw/pci-bridge/pcie_pci_bridge.c:84
84 shpc_free(d);
(gdb) l
79 pcie_aer_exit(d);
80 aer_error:
81 pm_error:
82 pcie_cap_exit(d);
83 cap_error:
84 shpc_free(d);
85 error:
86 pci_bridge_exitfn(d);
87 }
88
(gdb)
--
Eduardo
On 20/09/2017 12:52, Aleksandr Bezzubikov wrote:
>
> ср, 20 сент. 2017 г. в 10:13, Marcel Apfelbaum <marcel(a)redhat.com
> <mailto:marcel@redhat.com>>:
>
> On 19/09/2017 23:34, Eduardo Habkost wrote:
> > On Fri, Aug 18, 2017 at 02:36:47AM +0300, Aleksandr Bezzubikov wrote:
> >> Introduce a new PCIExpress-to-PCI Bridge device,
> >> which is a hot-pluggable PCI Express device and
> >> supports devices hot-plug with SHPC.
> >>
> >> This device is intended to replace the DMI-to-PCI Bridge.
> >>
> >> Signed-off-by: Aleksandr Bezzubikov <zuban32s(a)gmail.com
> <mailto:zuban32s@gmail.com>>
> >> Reviewed-by: Marcel Apfelbaum <marcel(a)redhat.com
> <mailto:marcel@redhat.com>>
> >
> > It's possible to crash QEMU by instantiating this device, with;
> >
> > $ qemu-system-ppc64 -machine prep -device pcie-pci-bridge
> > qemu-system-ppc64: qemu/memory.c:1533: memory_region_finalize:
> Assertion `!mr->container' failed.
> > Aborted
>
> Hi Edurado,
>
> >
> > I didn't investigate the root cause.
> >
>
> Thanks for reporting it!
> Aleksandr, can you have a look? Maybe we should not compile
> the device for ppc arch. (x86 and arm is enough)
>
>
> I will see what can we do. Is x86 and arm really enough?
>
Well, I am being selfish, and it works for me lately :).
Seriously speaking, the new generic PCI Express
Port was restricted to x86 and arm for reasons I don't remember.
Since your work has the same scope, the restriction makes sense.
Please grep for CONFIG_PCIE_PORT to convince yourself
and to help coding it.
Thanks,
Marcel
>
>
> Appreciated,
> Marcel
>
> --
> Aleksandr Bezzubikov
This series introduces a new device - Generic PCI Express to PCI bridge,
and also makes all necessary changes to enable hotplug of the bridge itself
and any device into the bridge.
Changes v6->v7:
Change IO/MEM/PREF reservation properties type to SIZE.
Changes v5->v6:
1. Fix indentation in the cap creation function (addresses Marcel's comment)
2. Simplify capability pref_mem_* fields assignment (addresses Marcel's comment)
3. Documentation fixes:
- fix mutually exclusive fields definition (addresses Laszlo's comment)
- fix pcie-pci-bridge usage example (addresses Marcel's comment)
Changes v4->v5:
1. Change PCIE-PCI Bridge license (addresses Marcel's comment)
2. The capability layout changes (adress Laszlo' comments):
- separate pref_mem into pref_mem_32 and pref_mem_64 fields (SeaBIOS side has the same changes)
- accordingly change the Generic Root Port's properties
3. Do not add the capability to the root port if no valid values are provided (adresses Michael's comment)
4. Rename the capability type to 'RESOURCE_RESERVE' (addresses Marcel's comment)
5. Remove shpc_present check function (addresses Marcel's comment)
6. Fix the 4th patch message (adresses Michael's comment)
7. Patch for SHPC enabling in _OSC method has been already merged
Changes v3->v4:
1. PCIE-PCI Bridge device: "msi_enable"->"msi", "shpc"->"shpc_bar", remove local_err,
make "msi" property OnOffAuto, shpc_present() is still here
to avoid SHPC_VMSTATE refactoring (address Marcel's comments).
2. Change QEMU PCI capability layout (SeaBIOS side has the same changes):
- change reservation fields types: bus_res - uint32_t, others - uint64_t
- rename 'non_pref' and 'pref' fields
- interpret -1 value as 'ignore'
3. Use parent_realize in Generic PCI Express Root Port properly.
4. Fix documentation: fully replace the DMI-PCI bridge references with the new PCIE-PCI bridge,
"PCIE"->"PCI Express", small mistakes and typos - address Laszlo's and Marcel's comments.
5. Rename QEMU PCI cap creation fucntion - addresses Marcel's comment.
Changes v2->v3:
(0). 'do_not_use' capability field flag is still _not_ in here since we haven't come to consesus on it yet.
1. Merge commits 5 (bus_reserve property creation) and 6 (property usage) together - addresses Michael's comment.
2. Add 'bus_reserve' property and QEMU PCI capability only to Generic PCIE Root Port - addresses Michael's and Marcel's comments.
3. Change 'bus_reserve' property's default value to 0 - addresses Michael's comment.
4. Rename QEMU bridge-specific PCI capability creation function - addresses Michael's comment.
5. Init the whole QEMU PCI capability with zeroes - addresses Michael's and Laszlo's comments.
6. Change QEMU PCI capability layout (SeaBIOS side has the same changes)
- add 'type' field to distinguish multiple
RedHat-specific capabilities - addresses Michael's comment
- do not mimiс PCI Config space register layout, but use mutually exclusive differently
sized fields for IO and prefetchable memory limits - addresses Laszlo's comment
7. Correct error handling in PCIE-PCI bridge realize function.
8. Replace a '2' constant with PCI_CAP_FLAGS in the capability creation function - addresses Michael's comment.
9. Remove a comment on _OSC which isn't correct anymore - address Marcel's comment.
10. Add documentation for the Generic PCIE-PCI Bridge and QEMU PCI capability - addresses Michael's comment.
Changes v1->v2:
1. Enable SHPC for the bridge.
2. Enable SHPC support for the Q35 machine (ACPI stuff).
3. Introduce PCI capability to help firmware on the system init.
This allows the bridge to be hotpluggable. Now it's supported
only for pcie-root-port. Now it's supposed to used with
SeaBIOS only, look at the SeaBIOS corresponding series
"Allow RedHat PCI bridges reserve more buses than necessary during init".
Aleksandr Bezzubikov (4):
hw/pci: introduce pcie-pci-bridge device
hw/pci: introduce bridge-only vendor-specific capability to provide
some hints to firmware
hw/pci: add QEMU-specific PCI capability to the Generic PCI Express
Root Port
docs: update documentation considering PCIE-PCI bridge
docs/pcie.txt | 49 +++++-----
docs/pcie_pci_bridge.txt | 114 ++++++++++++++++++++++
hw/pci-bridge/Makefile.objs | 2 +-
hw/pci-bridge/gen_pcie_root_port.c | 36 +++++++
hw/pci-bridge/pcie_pci_bridge.c | 192 +++++++++++++++++++++++++++++++++++++
hw/pci/pci_bridge.c | 46 +++++++++
include/hw/pci/pci.h | 1 +
include/hw/pci/pci_bridge.h | 25 +++++
include/hw/pci/pcie_port.h | 1 +
9 files changed, 442 insertions(+), 24 deletions(-)
create mode 100644 docs/pcie_pci_bridge.txt
create mode 100644 hw/pci-bridge/pcie_pci_bridge.c
--
2.7.4
