SeaBIOS February 2015

seabios@seabios.org

19 participants
20 discussions

[PATCH V2 0/2] fw/pci: better support for multiple host bridges
by Marcel Apfelbaum 11 Mar '15

11 Mar '15

The series is developed together with QEMU's: [Qemu-devel] [PATCH RFC 00/17] implement multiple primary busses for pc machines http://lists.gnu.org/archive/html/qemu-ppc/2015-01/msg00159.html (not related to ppc) v1 -> v2: - Addressed Kevin O'Connor idea (Thanks!) to treat devices behind extra root PCI buses as belonging to Bus 0 for resource resizing and mapping. The series fixes some issues when more than one root primary bus is present. First patch scans all the bus range to find the extra root buses. Second patch extends memory and IO mapping for found buses. Marcel Apfelbaum (2): fw/pci: scan all buses if extraroots romfile is present fw/pci: map memory and IO regions for multiple pci root buses src/fw/pciinit.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.1.0

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Re: [SeaBIOS] question about usb and memory zones
by Kevin O'Connor 28 Feb '15

28 Feb '15

On Sat, Feb 28, 2015 at 10:24:16AM +0330, Navid Movahedi wrote: > Hi > I'm reading the seabios source code, the usb part and found that for > example in usb-uhci.c file, in some parts malloc_low is used and in other > malloc_high > Now, the question: is it important for usb endpoints or pipes to be > allocated in low or high zone of memory? and if yes, why? There is some documentation on the memory zones at: http://www.seabios.org/Memory_Model In the uhci driver, the low memory zone is used for any allocations that need to be read/writable to code that runs in 16bit mode (uhci_send_pipe and uhci_poll_intr). The high memory allocations are for DMA structures that aren't read/written to by the CPU during runtime. -Kevin

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question about usb and memory zones
by Navid Movahedi 28 Feb '15

28 Feb '15

Hi I'm reading the seabios source code, the usb part and found that for example in usb-uhci.c file, in some parts malloc_low is used and in other malloc_high Now, the question: is it important for usb endpoints or pipes to be allocated in low or high zone of memory? and if yes, why?

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[PATCH V3 0/2] fw/pci: better support for multiple host bridges
by Marcel Apfelbaum 25 Feb '15

25 Feb '15

The series is developed together with QEMU's: [Qemu-devel] [PATCH RFC 00/17] implement multiple primary busses for pc machines http://lists.gnu.org/archive/html/qemu-ppc/2015-01/msg00159.html (not related to ppc) v2 -> v3: - Addressed Kevin O'Connor comment to drop res_on_default_bus flag. - Added him as signed-off-by, I hope is OK. v1 -> v2: - Addressed Kevin O'Connor idea (Thanks!) to treat devices behind extra root PCI buses as belonging to Bus 0 for resource resizing and mapping. The series fixes some issues when more than one root primary bus is present. First patch scans all the bus range to find the extra root buses. Second patch extends memory and IO mapping for found buses. Marcel Apfelbaum (2): fw/pci: scan all buses if extraroots romfile is present fw/pci: map memory and IO regions for multiple pci root buses src/fw/pciinit.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.1.0

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[PATCH] pci: enable SERR# for error forwording in bridge control register
by Chen Fan 25 Feb '15

25 Feb '15

For PCIe device support AER(Advanced Error Reporting), from the pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL can be forwarded from the secondary interface to the primary interface, only require the SERR# Enable bit in the Bridge Control register is set. and at the kernel side, we found only _HPP() method can enable SERR#, So here we want to turn on this bit. Signed-off-by: Chen Fan <chen.fan.fnst(a)cn.fujitsu.com> --- src/fw/pciinit.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 34279a4..28ed1af 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -310,6 +310,10 @@ static void pci_bios_init_device(struct pci_device *pci) /* enable memory mappings */ pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR); + /* enable SERR# for forwording */ + if (pci->header_type & PCI_HEADER_TYPE_BRIDGE) + pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, + PCI_BRIDGE_CTL_SERR); } static void pci_bios_init_devices(void) -- 1.9.3

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[PATCH V4 1/1] Add an option to only execute option ROMs contained in CBFS
by tpearson＠raptorengineeringinc.com 24 Feb '15

24 Feb '15

TEST: Booted ASUS KFSN4-DRE with iPXE ROMs built in to CBFS; with etc/pci-optionrom-exec set to 0 the on-board network ROMs were ignored while the iPXE ROMs executed normally. When set to 2 or greater all option ROMs executed normally. Tests of VGA only were not possible due to a lack of supported hardware. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/optionroms.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/optionroms.c b/src/optionroms.c index 93d9d2f..374e52f 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -20,6 +20,8 @@ #include "string.h" // memset #include "util.h" // get_pnp_offset +static int EnforceChecksum, S3ResumeVga, RunPCIroms; + /**************************************************************** * Helper functions @@ -60,8 +62,6 @@ call_bcv(u16 seg, u16 ip) __callrom(MAKE_FLATPTR(seg, 0), ip, 0); } -static int EnforceChecksum; - // Verify that an option rom looks valid static int is_valid_rom(struct rom_header *rom) @@ -320,7 +320,16 @@ fail: return NULL; } -// Attempt to map and initialize the option rom on a given PCI device. +/* + * Attempt to map and initialize the option rom on a given PCI device. + * + * The following values are supported by RunPCIroms: + * 0: Execute no ROMs + * 1: Execute only VGA ROMs + * 2: Execute all ROMs + * This value is read from the CBFS file etc/pci-optionrom-exec + * Default is 2 (execute all ROMs) + */ static int init_pcirom(struct pci_device *pci, int isvga, u64 *sources) { @@ -329,7 +338,7 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources) , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf) , pci->vendor, pci->device); struct rom_header *rom = lookup_hardcode(pci); - if (! rom) + if (!rom && ((RunPCIroms > 1) || ((RunPCIroms == 1) && isvga))) rom = map_pcirom(pci); if (! rom) // No ROM present. @@ -416,7 +425,6 @@ optionrom_setup(void) * VGA init ****************************************************************/ -static int S3ResumeVga; int ScreenAndDebug; struct rom_header *VgaROM; @@ -432,8 +440,12 @@ vgarom_setup(void) // Load some config settings that impact VGA. EnforceChecksum = romfile_loadint("etc/optionroms-checksum", 1); S3ResumeVga = romfile_loadint("etc/s3-resume-vga-init", CONFIG_QEMU); + RunPCIroms = romfile_loadint("etc/pci-optionrom-exec", 2); ScreenAndDebug = romfile_loadint("etc/screen-and-debug", 1); + if (RunPCIroms > 2) + dprintf(1, "WARNING: etc/pci-optionrom-exec value %d out of range\n", RunPCIroms); + if (CONFIG_OPTIONROMS_DEPLOYED) { // Option roms are already deployed on the system. init_optionrom((void*)BUILD_ROM_START, 0, 1); -- 1.7.9.5

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[PATCH] docs: Add page on available CBFS/fw_cfg runtime config files
by Kevin O'Connor 24 Feb '15

24 Feb '15

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- Much of the content on this page is also on the coreboot SeaBIOS wiki page. After adding this page to the SeaBIOS wiki, my intent would be to prune back the contents of the coreboot page and instead point to the new SeaBIOS wiki page. (Though, I would leave most of the examples in place on the coreboot page.) I think it would be better for this to be in the SeaBIOS repo so that new config settings and changes can be documented at the same time they are updated. --- docs/Developer_Documentation.md | 8 +- docs/Runtime_config.md | 189 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 193 insertions(+), 4 deletions(-) create mode 100644 docs/Runtime_config.md diff --git a/docs/Developer_Documentation.md b/docs/Developer_Documentation.md index 843d612..24bf48a 100644 --- a/docs/Developer_Documentation.md +++ b/docs/Developer_Documentation.md @@ -10,12 +10,12 @@ page. See details on [building SeaBIOS](Build overview). There is also information on the SeaBIOS [Memory Model](Memory Model). - Along with information on SeaBIOS [Execution and code flow](Execution -and code flow). +and code flow). A description of the process of linking the final +SeaBIOS binary is available at [Linking overview](Linking overview). -A description of the process of linking the final SeaBIOS binary is -available at [Linking overview](Linking overview). +The list of available runtime configuration items is at +[runtime config](Runtime_config). To debug SeaBIOS and report problems see SeaBIOS [debugging](Debugging). To contribute changes to SeaBIOS see diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md new file mode 100644 index 0000000..77e157b --- /dev/null +++ b/docs/Runtime_config.md @@ -0,0 +1,189 @@ +SeaBIOS can read several configuration items at runtime. On coreboot +the configuration comes from files located in CBFS. When SeaBIOS runs +natively on QEMU the files are passed from QEMU via the fw_cfg +interface. + +This page documents the user visible configuration and control +features that SeaBIOS supports. + +LZMA compression +================ + +On coreboot, when scanning files in CBFS, any filename that ends with +a ".lzma" suffix will be treated as a raw file that is compressed with +the lzma compression algorithm. This works for option ROMs, +configuration files, floppy images, etc. . (This feature should not be +used with embedded payloads - to compress payloads, use the standard +section based compression algorithm that is built into the payload +specification.) + +For example, the file **pci1106,3344.rom.lzma** would be treated the +same as **pci1106,3344.rom**, but will be automatically uncompressed +when accessed. + +A file is typically compressed with the lzma compression command line +tool. For example: + +`lzma -zc /path/to/somefile.bin > somefile.bin.lzma` + +However, some recent versions of lzma no longer supply an uncompressed +file size in the lzma header. (They instead populate the field with +zero.) Unfortunately, SeaBIOS requires the uncompressed file size, so +it may be necessary to use a different version of the lzma tool. + +File aliases +============ + +It is possible to create the equivalent of "symbolic links" so that +one file's content appears under another name. To do this, create a +**links** file with one line per link and each line having the format +of "linkname" and "destname" separated by a space character. For +example, the **links** file may look like: + +``` +pci1234,1000.rom somerom.rom +pci1234,1001.rom somerom.rom +pci1234,1002.rom somerom.rom +``` + +The above example would cause SeaBIOS to treat "pci1234,1000.rom" or +"pci1234,1001.rom" as files with the same content as the file +"somerom.rom". + +Option ROMs +=========== + +SeaBIOS will scan all of the PCI devices in the target machine for +option ROMs on PCI devices. It recognizes option ROMs in files that +have the form **pciVVVV,DDDD.rom**. The VVVV,DDDD should correspond to +the PCI vendor and device id of a device in the machine. If a given +file is found then SeaBIOS will deploy the file instead of attempting +to extract an option ROM from the device. In addition to supplying +option ROMs for on-board devices that do not store their own ROMs, +this mechanism may be used to prevent a ROM on a specific device from +running. + +SeaBIOS always deploys the VGA rom associated with the active VGA +device before any other ROMs. + +In addition, SeaBIOS will also run any file in the directory +**vgaroms/** as a VGA option ROM not specific to a device and files in +**genroms/** as a generic option ROM not specific to a device. The +ROMS in **vgaroms/** are run immediately after running the option ROM +associated with the primary VGA device (if any were found), and the +**genroms/** ROMs are run after all other PCI ROMs are run. + +Bootsplash images +================= + +SeaBIOS can show a custom [JPEG](http://en.wikipedia.org/wiki/JPEG) +image or [BMP](http://en.wikipedia.org/wiki/BMP_file_format) image +during bootup. To enable this, add the JPEG file to flash with the +name **bootsplash.jpg** or BMP file as **bootsplash.bmp**. + +The size of the image determines the video mode to use for showing the +image. Make sure the dimensions of the image exactly correspond to an +available video mode (eg, 640x480, or 1024x768), otherwise it will not +be displayed. + +SeaBIOS will show the image during the wait for the boot menu (if the +boot menu has been disabled, users will not see the image). The image +should probably have "Press F12 for boot menu" embedded in it so users +know they can enter the normal SeaBIOS boot menu. By default, the boot +menu prompt (and thus graphical image) is shown for 2.5 seconds. This +can be customized via a [configuration +parameter](#Other_Configuration_items). + +The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It +supports most common JPEGs, but does not support all possible formats. +Please see the [trouble reporting section](Debugging) if a valid image +isn't displayed properly. + +Payloads +======== + +On coreboot, SeaBIOS will treat all files found in the **img/** +directory as a coreboot payload. Each payload file will be available +for boot, and one can select from the available payloads in the +bootmenu. SeaBIOS supports both uncompressed and lzma compressed +payloads. + +Floppy images +============= + +It is possible to embed an image of a floppy into a file. SeaBIOS can +then boot from and redirect floppy BIOS calls to the image. This is +mainly useful for legacy software (such as DOS utilities). To use this +feature, place a floppy image into the directory **floppyimg/**. + +Using LZMA file compression with the [.lzma file +suffix](#LZMA_compression) is a useful way to reduce the file +size. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, +2.88MB, 160K, 180K, 320K. + +The floppy image will appear as writable to the system, however all +writes are discarded on reboot. + +When using this system, SeaBIOS reserves high-memory to store the +floppy. The reserved memory is then no longer available for OS use, so +this feature should only be used when needed. + +Configuring boot order +====================== + +The **bootorder** file may be used to configure the boot up order. The +file should be ASCII text and contain one line per boot method. The +description of each boot method follows an [Open +Firmware](https://secure.wikimedia.org/wikipedia/en/wiki/Open_firmware) +device path format. SeaBIOS will attempt to boot from each item in the +file — first line of the file first. + +The easiest way to find the available boot methods is to look for +"Searching bootorder for" in the SeaBIOS debug output. For example, +one may see lines similar to: + +``` +Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0 +Searching bootorder for: /pci@i0cf8/*@f,1/drive@2/disk@1 +Searching bootorder for: /pci@i0cf8/usb@10,4/*@2 +``` + +The above represents the patterns SeaBIOS will search for in the +bootorder file. However, it's safe to just copy and paste the pattern +into bootorder. For example, the file: + +``` +/pci@i0cf8/usb@10,4/*@2 +/pci@i0cf8/*@f/drive@1/disk@0 +``` + +will instruct SeaBIOS to attempt to boot from the given USB drive +first and then attempt the given ATA harddrive second. + +SeaBIOS also supports a special "HALT" directive. If a line that +contains "HALT" is found in the bootorder file then SeaBIOS will (by +default) only attempt to boot from devices explicitly listed above +HALT in the file. + +Other Configuration items +========================= + +There are several additional configuration options available in the +**etc/** directory. + +| Filename | Description +|---------------------|--------------------------------------------------- +| show-boot-menu | Controls the display of the boot menu. Set to 0 to disable the boot menu. +| boot-menu-message | Customize the text boot menu message. Normally, when in text mode SeaBIOS will report the string "\\nPress F12 for boot menu.\\n\\n". This field allows the string to be changed. (This is a string field, and is added as a file containing the raw string.) +| boot-menu-key | Controls which key activates the boot menu. The value stored is the DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set, be sure to also customize the **boot-menu-message** field above. +| boot-menu-wait | Amount of time (in milliseconds) to wait at the boot menu prompt before selecting the default boot. +| boot-fail-wait | If no boot devices are found SeaBIOS will reboot after 60 seconds. Set this to the amount of time (in milliseconds) to customize the reboot delay or set to -1 to disable rebooting when no boot devices are found +| extra-pci-roots | If the target machine has multiple independent root buses set this to a positive value. The SeaBIOS PCI probe will then search for the given number of extra root buses. +| ps2-keyboard-spinup | Some laptops that emulate PS2 keyboards don't respond to keyboard commands immediately after powering on. One may specify the amount of time (in milliseconds) here to allow as additional time for the keyboard to become responsive. When this field is set, SeaBIOS will repeatedly attempt to detect the keyboard until the keyboard is found or the specified timeout is reached. +| optionroms-checksum | Option ROMs are required to have correct checksums. However, some option ROMs in the wild don't correctly follow the specifications and have bad checksums. Set this to a zero value to allow SeaBIOS to execute them anyways. +| s3-resume-vga-init | Set this to a non-zero value to instruct SeaBIOS to run the vga rom on an S3 resume. +| screen-and-debug | Set this to a zero value to instruct SeaBIOS to not write characters it sends to the screen to the debug ports. This can be useful when using sgabios. +| advertise-serial-debug-port | If using a serial debug port, one can set this file to a zero value to prevent SeaBIOS from listing that serial port as available for operating system use. This can be useful when running old DOS programs that are known to reset the baud rate of all advertised serial ports. +| floppy0 | Set this to the type of the first floppy drive in the system (only type 4 for 3.5 inch drives is supported). +| floppy1 | The type of the second floppy drive in the system. See the description of **floppy0** for more info. +| threads | By default, SeaBIOS will parallelize hardware initialization during bootup to reduce boot time. Multiple hardware devices can be initialized in parallel between vga initialization and option rom initialization. One can set this file to a value of zero to force hardware initialization to run serially. Alternatively, one can set this file to 2 to enable early hardware initialization that runs in parallel with vga, option rom initialization, and the boot menu. -- 1.9.3

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[Qemu-devel] [PATCH RFC V2 00/17] hw/pc: implement multiple primary busses for pc machines
by Marcel Apfelbaum 20 Feb '15

20 Feb '15

Series status: The series is fully functional. The reason is still RFC is because depends on Igor's ACPI series that is still in the mailing list. Once it gets accepted I'll resend this series rebased on it. - Limitations: - Pxb's bus does not support hotplug. It will be addressed on top of this series because is already getting to big. You are more than welcome to try using: -device pxb-device,id=pxb,bus_nr=4,numa_node=1 -device e1000,bus=pxb,addr=0x1 -bios <patched with the above series> v1->v2: - Add support for multiple pxb devices. - Attach pxb's bus to specific NUMA node. - Got rid of the hacks from prev version. - Tested also for Win7 and Fedora 20, and for virtio blk devices. - Several bug-fixes resulting in a stable version ready for submission. This series depends on: - [SeaBIOS] [PATCH V2 0/2] fw/pci: better support for multiple host bridges - [Qemu-devel] [PATCH v4 0/3] pc: acpi-build: make linker & RSDP tables dynamic - [PATCH v3 00/52] ACPI refactoring: replace template patching with C AML API Reasoning: We need multiple primary busess for a few reasons, the most important one is to be able to associate a pass-trough device with a guest NUMA node. The OS-es are able to associate a NUMA node only to a primary bus, not to a specific PCI device or a pci-2-pci bridge. PC machines support multiple NUMA nodes for CPUs and memory, however the IO was not yet supported. patch 1 adds the necessary acpi constructs based on Igor's series patch 2-5 implements acpi code needed to expose the pxb's primary bus to guests patch 6 separates the pci_bus code into a designated file patch 7-11 handles the implicit assumptions in code that only one primary bus can exist patch 12 handles the actual implementation of the PXB devices patch 13-14 enables the device patch 15 implements PXB map_irq function, (can be squashed into the actual PXB) patch 16-17 adds NUMA support Marcel Apfelbaum (17): acpi: added needed acpi constructs hw/acpi: add support for multiple root busses hw/apci: add _PRT method for extra root busses hw/acpi: add _CRS method for extra root busses hw/acpi: remove from root bus 0 the crs resources used by other busses. hw/pci: move pci bus related code to separate files hw/pci: made pci_bus_is_root a PCIBusClass method hw/pci: made pci_bus_num a PCIBusClass method hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query hw/pci: implement iteration over multiple host bridges hw/pci: introduce PCI Expander Bridge (PXB) hw/pci: inform bios if the system has more than one pci bridge hw/pci: piix - suport multiple host bridges hw/pxb: add map_irq func hw/pci_bus: add support for NUMA nodes hw/pxb: add numa_node parameter arch_init.c | 1 + hw/acpi/acpi-build-utils.c | 107 +++++++- hw/alpha/typhoon.c | 1 + hw/i386/acpi-build.c | 357 ++++++++++++++++++++++++- hw/i386/kvm/pci-assign.c | 1 + hw/i386/pc.c | 13 + hw/mips/gt64xxx_pci.c | 1 + hw/pci-bridge/Makefile.objs | 1 + hw/pci-bridge/pci_expander_bridge.c | 208 +++++++++++++++ hw/pci-host/bonito.c | 1 + hw/pci-host/grackle.c | 1 + hw/pci-host/piix.c | 63 ++++- hw/pci-host/ppce500.c | 1 + hw/pci-host/q35.c | 5 + hw/pci-host/uninorth.c | 1 + hw/pci/Makefile.objs | 2 +- hw/pci/pci-hotplug-old.c | 1 + hw/pci/pci.c | 501 +--------------------------------- hw/pci/pci_bus.c | 517 ++++++++++++++++++++++++++++++++++++ hw/pci/pci_host.c | 6 + hw/ppc/ppc4xx_pci.c | 1 + hw/scsi/megasas.c | 1 + hw/sh4/r2d.c | 1 + hw/sh4/sh_pci.c | 1 + hw/vfio/pci.c | 1 + hw/xen/xen_pt.c | 1 + include/hw/acpi/acpi-build-utils.h | 12 + include/hw/pci/pci.h | 6 +- include/hw/pci/pci_bus.h | 35 +++ include/hw/pci/pci_host.h | 11 + include/sysemu/sysemu.h | 1 + 31 files changed, 1348 insertions(+), 512 deletions(-) create mode 100644 hw/pci-bridge/pci_expander_bridge.c create mode 100644 hw/pci/pci_bus.c -- 2.1.0

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Re: [SeaBIOS] [PATCH] x86: fix read{b, w, l} and write{b, w, l} functions
by Kevin O'Connor 19 Feb '15

19 Feb '15

On Wed, Feb 18, 2015 at 04:38:43PM -0800, Ameya Palande wrote: > Hi Kevin, > > On Wed, Feb 18, 2015 at 12:15 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > > On Tue, Feb 17, 2015 at 02:00:49PM -0800, Ameya Palande wrote: > > > Use barrier() for memory mapped IO functions. > > > > > > This fixes pvscsi driver to boot on QEMU's pvscsi controller. > > > Test command: > > > qemu -m 512 --enable-kvm -device pvscsi,id=pvscsi0 > > > -device scsi-disk,bus=pvscsi0.0,drive=drive0 > > > -drive id=drive0,if=none,file=ubuntu1410.img,if=none > > > -bios seabios/out/bios.bin > > > > Thanks. I didn't think it was standard for a barrier to be present in > > these functions, but I now see that Linux also uses barrier here. So, > > I've committed your patch (with a couple of minor changes). > > Thanks for applying this patch! > > Since memory mapped read and write are now protected by barriers, how > should we deal about use of (potentially redundant) barriers in: > src/hw/usb-ehci.c > src/hw/usb-ohci.c > src/hw/usb-uhci.c I think redundant barriers should ultimately be removed. > Interestingly "src/hw/usb-xhci.c" doesn't use barrier() at all! > Wondering if that was correct? That is a good quesiton. I had not noticed any issues in this area before, but I wasn't looking explicitly for them. > > Thanks, also, for tracking down the PVSCSI problem. > > I could get it booting only under QEMU. I wanted to test seabios under > ESXi to make sure it really boots under ESXi's pvscsi implementation. > Does anyone know a way to get seabios running under ESXi so that > pvscsi validity can be checked? I'm not familiar with ESXi, so I can't help here. -Kevin

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[PATCH] x86: fix read{b,w,l} and write{b,w,l} functions
by Ameya Palande 19 Feb '15

19 Feb '15

Use barrier() for memory mapped IO functions. This fixes pvscsi driver to boot on QEMU's pvscsi controller. Test command: qemu -m 512 --enable-kvm -device pvscsi,id=pvscsi0 -device scsi-disk,bus=pvscsi0.0,drive=drive0 -drive id=drive0,if=none,file=ubuntu1410.img,if=none -bios seabios/out/bios.bin Signed-off-by: Ameya Palande <2ameya(a)gmail.com> --- src/x86.h | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/x86.h b/src/x86.h index 57773d2..570f2f6 100644 --- a/src/x86.h +++ b/src/x86.h @@ -176,22 +176,37 @@ static inline void outsl(u16 port, u32 *data, u32 count) { } static inline void writel(void *addr, u32 val) { + barrier(); *(volatile u32 *)addr = val; } static inline void writew(void *addr, u16 val) { + barrier(); *(volatile u16 *)addr = val; } static inline void writeb(void *addr, u8 val) { + barrier(); *(volatile u8 *)addr = val; } static inline u32 readl(const void *addr) { - return *(volatile const u32 *)addr; + u32 val; + + val = *(volatile const u32 *)addr; + barrier(); + return val; } static inline u16 readw(const void *addr) { - return *(volatile const u16 *)addr; + u16 val; + + val = *(volatile const u16 *)addr; + barrier(); + return val; } static inline u8 readb(const void *addr) { - return *(volatile const u8 *)addr; + u8 val; + + val = *(volatile const u8 *)addr; + barrier(); + return val; } // GDT bits -- 1.8.3.1

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SeaBIOS February 2015