SeaBIOS February 2015

seabios@seabios.org

19 participants
20 discussions

[PATCH] docs: Add page describing the patch contribution process
by Kevin O'Connor 19 Feb '15

19 Feb '15

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- I think it would be worthwhile to document the process of contributing patches to SeaBIOS. However, I don't really want to duplicate all the useful information already available on other projects. In particular, the QEMU wiki documentation for patch submission is quite good. So, this patch adds a new SeaBIOS document which basically just points users to the QEMU wiki page. --- docs/Contributing.md | 20 ++++++++++++++++++++ docs/Developer_Documentation.md | 3 ++- 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 docs/Contributing.md diff --git a/docs/Contributing.md b/docs/Contributing.md new file mode 100644 index 0000000..d0f2b5b --- /dev/null +++ b/docs/Contributing.md @@ -0,0 +1,20 @@ +SeaBIOS welcomes contributions of code (either fixing bugs or adding +new functionality). At a high level, the process to contribute a +change is: + +1. [Obtain](Download) the current code and documentation +2. Enhance and test the code locally +3. Submit changes to the SeaBIOS [mailing list](Mailinglist) as a + patch +4. Receive feedback, answer questions, and possibly provide updated + patches +5. When accepted, a maintainer (Kevin O'Connor or Gerd Hoffman) will + commit the change to the master SeaBIOS repository + +The SeaBIOS patch submission process is similar to the +[QEMU process](http://wiki.qemu.org/Contribute/SubmitAPatch). Please +review the QEMU process for more details and tips on the best way to +submit patches. The SeaBIOS C code does follow a slightly different +coding style from QEMU (eg, mixed code and C99 style variable +declarations are encouraged, braces are not required around single +statement blocks), however patches in the QEMU style are acceptable. diff --git a/docs/Developer_Documentation.md b/docs/Developer_Documentation.md index d50455d..843d612 100644 --- a/docs/Developer_Documentation.md +++ b/docs/Developer_Documentation.md @@ -18,7 +18,8 @@ A description of the process of linking the final SeaBIOS binary is available at [Linking overview](Linking overview). To debug SeaBIOS and report problems see SeaBIOS -[debugging](Debugging). +[debugging](Debugging). To contribute changes to SeaBIOS see +[contributing](Contributing). Useful links to specifications is available at [Developer links](Developer links). -- 1.9.3

1 0

[PATCH] docs: add page for SeaVGABIOS
by Kevin O'Connor 19 Feb '15

19 Feb '15

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- docs/SeaBIOS.md | 2 ++ docs/SeaVGABIOS.md | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 docs/SeaVGABIOS.md diff --git a/docs/SeaBIOS.md b/docs/SeaBIOS.md index 831bfce..e24913a 100644 --- a/docs/SeaBIOS.md +++ b/docs/SeaBIOS.md @@ -10,6 +10,8 @@ information on using SeaBIOS in coreboot. Please see the [releases](Releases) page for information on recent releases. See the [download](Download) page to obtain SeaBIOS. +[SeaVGABIOS](SeaVGABIOS) is a sub-project of SeaBIOS. + Please join the [mailing list](Mailinglist) to contribute to SeaBIOS. Information on the internals of SeaBIOS is available on the [Developer Documentation](Developer Documentation) page. diff --git a/docs/SeaVGABIOS.md b/docs/SeaVGABIOS.md new file mode 100644 index 0000000..8e4e8e8 --- /dev/null +++ b/docs/SeaVGABIOS.md @@ -0,0 +1,38 @@ +SeaVGABIOS is a sub-project of the SeaBIOS project - it is an open +source implementation of a 16bit X86 +[VGA BIOS](http://en.wikipedia.org/wiki/Video_BIOS). SeaVGABIOS is the +default VGA BIOS on [QEMU](http://www.qemu.org/). SeaVGABIOS can also +run natively on some X86 VGA hardware with +[coreboot](http://www.coreboot.org/). + +Building SeaVGABIOS +=================== + +To build SeaVGABIOS, obtain the [code](Download), run `make +menuconfig` and select the type of VGA BIOS to build in the "VGA ROM" +menu. Once selected, run `make` and the final VGA BIOS binary will be +located in "out/vgabios.bin". + +The choice of available VGA BIOSes within "make menuconfig" is +dependent on whether CONFIG_QEMU, CONFIG_COREBOOT, or CONFIG_CSM is +selected. Also, the debug options under the "Debugging" menu apply to +SeaVGABIOS. All other options found in "make menuconfig" apply only to +SeaBIOS and will not impact the SeaVGABIOS build. + +If SeaVGABIOS is needed for multiple different devices (eg, QEMU's +cirrus emulation and QEMU's "dispi" emulation), then one must compile +SeaVGABIOS multiple times with the appropriate config for each build. + +SeaVGABIOS code +=============== + +The source code for SeaVGABIOS is located in the SeaBIOS +[git repository](Download). The main VGA BIOS code is located in the +"vgasrc/" directory. + +The SeaVGABIOS builds to a separate binary from the main SeaBIOS +binary, and much of the VGA BIOS code is separate from the main BIOS +code. However, much of the SeaBIOS +[developer documentation](Developer_Documentation) applies to +SeaVGABIOS. To contribute, please join the +[SeaBIOS mailing list](Mailinglist). -- 1.9.3

1 0

[PATCH 2/2] Add PCI option ROM blacklist in CBFS
by Timothy Pearson 18 Feb '15

18 Feb '15

File: pci_optrom_blacklist.txt Syntax: <bus>,<device>,<function> Numbers or a single wildcard ('*') are allowed Each blacklisted device is placed on separate line Examples: Blacklist device 01:04.0: 1,4,0 Blacklist all devices on bus 5: 5,*,* TEST: Booted ASUS KFSN4-DRE with iPXE ROMs built in to CBFS; with the two add-on network devices blacklisted the add-on network ROMs were ignored while the on-board iPXE ROMs executed normally. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/optionroms.c | 112 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/src/optionroms.c b/src/optionroms.c index fbcb6ca..44967e7 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -1,5 +1,6 @@ // Option rom scanning code. // +// Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com> // Copyright (C) 2008 Kevin O'Connor <kevin(a)koconnor.net> // Copyright (C) 2002 MandrakeSoft S.A. // @@ -346,12 +347,119 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources) * Non-VGA option rom init ****************************************************************/ +u8 char_is_digit(const char c) { + if ((c >= '0') && (c <= '9')) + return 1; + else + return 0; +} + +int atoi(const char* c) +{ + int value = 0; + + while (char_is_digit(*c)) { + value *= 10; + value += (int) (*c - '0'); + c++; + } + + return value; +} + +/* 256: Match none + * 257: Match any + */ +struct pci_optrom_blacklist_entry { + u16 bus; + u16 device; + u16 function; +}; + +u8 pci_device_option_rom_is_blacklisted(struct pci_device *pci, struct pci_optrom_blacklist_entry *pci_optrom_blacklist, int pci_optrom_blacklist_count) +{ + if (!pci) + return 0; + + int i; + for (i=0; i<pci_optrom_blacklist_count; i++) { + if ((pci_optrom_blacklist[i].bus == pci_bdf_to_bus(pci->bdf)) || (pci_optrom_blacklist[i].bus == 257)) { + if ((pci_optrom_blacklist[i].device == pci_bdf_to_dev(pci->bdf)) || (pci_optrom_blacklist[i].device == 257)) { + if ((pci_optrom_blacklist[i].function == pci_bdf_to_fn(pci->bdf)) || (pci_optrom_blacklist[i].function == 257)) { + return 1; + } + } + } + } + + return 0; +} + void optionrom_setup(void) { if (! CONFIG_OPTIONROMS) return; + struct pci_optrom_blacklist_entry *pci_optrom_blacklist = NULL; + int pci_optrom_blacklist_count = 0; + + dprintf(3, "Checking for PCI option ROM blacklist\n"); + int filesize; + u8 *filedata = romfile_loadfile("pci_optrom_blacklist.txt", &filesize); + if (filedata) { + int i = 0; + while (filedata[i]) { + if (filedata[i] == '\n') + pci_optrom_blacklist_count++; + i++; + } + pci_optrom_blacklist = malloc_tmphigh(sizeof(struct pci_optrom_blacklist_entry) + * pci_optrom_blacklist_count); + int bdf_parse = 0; + int j = 0; + i=0; + u16 value = 0; + pci_optrom_blacklist_count = 0; + char bdf_tmp[4]; + while (filedata[i]) { + if ((j > 3) || (bdf_parse > 2)) { + dprintf(1, "WARNING: Incorrect value in PCI option ROM blacklist\n"); + pci_optrom_blacklist[pci_optrom_blacklist_count].bus = 256; + pci_optrom_blacklist[pci_optrom_blacklist_count].device = 256; + pci_optrom_blacklist[pci_optrom_blacklist_count].function = 256; + } else { + bdf_tmp[j] = filedata[i]; + j++; + if ((filedata[i] == ',') || (filedata[i] == '\n')) { + bdf_tmp[j] = 0; + if (bdf_tmp[0] == '*') + value = 257; + else + value = atoi(bdf_tmp); + if (bdf_parse == 0) + pci_optrom_blacklist[pci_optrom_blacklist_count].bus = value; + if (bdf_parse == 1) + pci_optrom_blacklist[pci_optrom_blacklist_count].device = value; + if (bdf_parse == 2) + pci_optrom_blacklist[pci_optrom_blacklist_count].function = value; + bdf_parse++; + j=0; + } + } + if (filedata[i] == '\n') { + dprintf(3, "PCI device %02x:%02x.%x added to PCI option ROM blacklist\n", + pci_optrom_blacklist[pci_optrom_blacklist_count].bus, + pci_optrom_blacklist[pci_optrom_blacklist_count].device, + pci_optrom_blacklist[pci_optrom_blacklist_count].function); + pci_optrom_blacklist_count++; + bdf_parse=0; + } + i++; + } + free(filedata); + } + dprintf(1, "Scan for option roms\n"); u64 sources[(BUILD_BIOS_ADDR - BUILD_ROM_START) / OPTION_ROM_ALIGN]; memset(sources, 0, sizeof(sources)); @@ -373,13 +481,15 @@ optionrom_setup(void) foreachpci(pci) { if (pci->class == PCI_CLASS_DISPLAY_VGA || pci->have_driver) continue; - init_pcirom(pci, 0, sources); + if (!pci_device_option_rom_is_blacklisted(pci, pci_optrom_blacklist, pci_optrom_blacklist_count)) + init_pcirom(pci, 0, sources); } // Find and deploy CBFS roms not associated with a device. run_file_roms("genroms/", 0, sources); } rom_reserve(0); + free(pci_optrom_blacklist); // All option roms found and deployed - now build BEV/BCV vectors. -- 1.7.9.5 -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

3 8

[ANNOUNCE] SeaBIOS 1.8.0
by Kevin O'Connor 18 Feb '15

18 Feb '15

The 1.8.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Several USB timing fixes for USB controllers on real hardware * Initial support for USB3 hubs * Initial support for SD cards (on QEMU only) * Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only) * SeaVGABIOS improvements * Added cursor emulation to coreboot native init vgabios (cbvga) * Added support for read character calls when in graphics mode * Developer documentation added to "docs/" directory in the code repository and several documentation updates * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download

1 0

[PATCH 1/2] Add an option to only execute option ROMs contained in CBFS
by Timothy Pearson 15 Feb '15

15 Feb '15

TEST: Booted ASUS KFSN4-DRE with iPXE ROMs built in to CBFS; with this option set the on-board network ROMs were ignored while the iPXE ROMs executed normally. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 11 +++++++++++ src/optionroms.c | 3 +++ 2 files changed, 14 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 45ca59c..9cac231 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -355,6 +355,17 @@ menu "BIOS interfaces" default y help Support finding and running option roms during POST. + config CBFS_OPTIONROMS_ONLY + depends on OPTIONROMS && COREBOOT_FLASH + bool "Only execute option ROMs stored in CBFS" + default "n" + help + Only execute option ROMs that are stored in CBFS. + Do not scan PCI bus for option ROMs. This is useful + if one or more of your PCI devices crash/hang SeaBIOS + when executing their option ROMs, but you need to use + one or more option ROMs (such as SeaVGABIOS) that were + loaded into CBFS. config OPTIONROMS_DEPLOYED depends on OPTIONROMS && QEMU bool "Option roms are already at 0xc0000-0xf0000" diff --git a/src/optionroms.c b/src/optionroms.c index 93d9d2f..fbcb6ca 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -253,6 +253,9 @@ copy_rom(struct rom_header *rom) static struct rom_header * map_pcirom(struct pci_device *pci) { + if (CONFIG_CBFS_OPTIONROMS_ONLY) + return NULL; + u16 bdf = pci->bdf; dprintf(6, "Attempting to map option rom on dev %02x:%02x.%x\n" , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)); -- 1.7.9.5 -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

4 8

[PATCH] Add option to only execute CBFS option ROMs
by Timothy Pearson 12 Feb '15

12 Feb '15

All, This is my first time submitting a patch to SeaBIOS for review/inclusion; I assume this list is the correct initial contact? I have run into several situations where it is neccessary to execute only the relevant option ROMs contained in CBFS while ignoring any option ROM binary code present on PCI/PCIe devices; e.g. when the option ROM provided by the manufacturer is buggy but a FOSS replacement is available that works properly. This patch adds an option to only execute option ROMs contained in CBFS. Tested on ASUS KFSN4-DRE with iPXE ROMs built in to CBFS; with this option set the on-board network ROMs were ignored while the iPXE ROMs executed normally. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

4 15

Re: [SeaBIOS] [PATCH] pci: enable SERR# for error forwording in bridge control register
by Chen Fan 10 Feb '15

10 Feb '15

On 02/02/2015 10:44 PM, Bjorn Helgaas wrote: > On Sun, Feb 1, 2015 at 10:08 PM, Nishank Trivedi > <nishank.trivedi(a)netapp.com> wrote: >> On 2/1/15 6:13 PM, Chen Fan wrote: >>> >>> On 02/01/2015 07:01 AM, Kevin O'Connor wrote: >>>> On Wed, Jan 28, 2015 at 04:05:13PM +0800, Chen Fan wrote: >>>>> For PCIe device support AER(Advanced Error Reporting), from the >>>>> pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL >>>>> can be forwarded from the secondary interface to the primary interface, >>>>> only require the SERR# Enable bit in the Bridge Control register is set. >>>>> >>>>> and at the kernel side, we found only _HPP() method can enable >>>>> SERR#, So here we want to turn on this bit. >>>>> >>>>> Signed-off-by: Chen Fan <chen.fan.fnst(a)cn.fujitsu.com> >>>>> --- >>>>> src/fw/pciinit.c | 4 ++++ >>>>> 1 file changed, 4 insertions(+) >>>>> >>>>> diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c >>>>> index 34279a4..28ed1af 100644 >>>>> --- a/src/fw/pciinit.c >>>>> +++ b/src/fw/pciinit.c >>>>> @@ -310,6 +310,10 @@ static void pci_bios_init_device(struct >>>>> pci_device *pci) >>>>> /* enable memory mappings */ >>>>> pci_config_maskw(bdf, PCI_COMMAND, 0, >>>>> PCI_COMMAND_IO | PCI_COMMAND_MEMORY | >>>>> PCI_COMMAND_SERR); >>>>> + /* enable SERR# for forwording */ >>>>> + if (pci->header_type & PCI_HEADER_TYPE_BRIDGE) >>>>> + pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, >>>>> + PCI_BRIDGE_CTL_SERR); >>>>> } >>>> Thanks for submitting your patch. >>>> >>>> I'm not that familiar with all the details of the PCI specification. >>>> Can you elaborate on what doesn't work if this patch is not present, >>>> or what does work or work better when present? Is this associated >>>> with a QEMU feature or change? >>> With this patch, the aer error inject feature for pcie device in QEMU >>> will work . the hmp command line is called pcie_aer_inject_error. >>> a endpoint device propagates error messages to guest that need the >>> parent bridge type devices enable the SERR# in bridge control reigster >>> from pcie spec 3.0 chapter 6.2.5, and currently, the register bit is >>> not turned on, so the command pcie_aer_inject_error is not work. >>> and if the patch is ok, could you check in this patch? >> >> Patch looks fine to me. >> Certain PCI switches, like PEX87xx, provide mechanism to explicitly inject >> errors (unlike aer_inject tool where just interrupt is raised). However, if >> SERR bit is not enabled in the bridges, error is not percolated to root >> port, probably because kernel expects BIOS to enable this bit. CC'ing Bjorn >> who can correct if this incorrect understanding. > I think your understanding of PCI_BRIDGE_CTL_SERR is correct. Linux > doesn't really have formal expectations about how platforms should set > PCI_BRIDGE_CTL_SERR. It's possible that Linux should be more > proactive about enabling it. I think it's just an area that nobody > has paid much attention to. Hi Kevin, How do you think of this patch? Thanks, Chen > Bjorn > . >

2 1

[PATCH] build: remove hardcoded timestamp
by Olaf Hering 09 Feb '15

09 Feb '15

The timestamp and hostname carries no value for the default build. If its really required in special environment, or if someone is emotionally attached to such strings, it is is handled by existing logic a few lines above: provide your own .version file Once this patch is applied it is possible to get reproducible builds of Xens hvmloader. Signed-off-by: Olaf Hering <olaf(a)aepfle.de> --- scripts/buildversion.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/buildversion.sh b/scripts/buildversion.sh index e5ce96c..338b7f0 100755 --- a/scripts/buildversion.sh +++ b/scripts/buildversion.sh @@ -11,7 +11,6 @@ elif [ -f .version ]; then else VERSION="?" fi -VERSION="${VERSION}-`date +"%Y%m%d_%H%M%S"`-`hostname`" echo "Version: ${VERSION}" # Build header file

5 9

[PATCH] vgabios: Use EBDA (instead of PMM) for extra stack
by Kevin O'Connor 03 Feb '15

03 Feb '15

Instead of allocating the SeaVGABIOS extra stack via a PCIv3 style PMM call, use the EBDA to store the stack. The stack is placed at the end of the first 1KiB of the EBDA. Normally this EBDA space is reserved for the main BIOS, but SeaBIOS doesn't use the space. This works around an issue with 16bit code running on Windows Vista (and likely later versions of Windows). The Windows 16bit emulator can not handle a stack in the e-segment. Using the EBDA, and thus relocating the stack to the 9-segment, works around the issue. Reported-by: Richard Laager <rlaager(a)wiktel.com> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- There were several possible ways to resolve the main issue. I'm leaning torwards the "use the EBDA for the stack" approach, and the patch below implements that. -Kevin --- vgasrc/Kconfig | 18 ++++++++---------- vgasrc/vgaentry.S | 20 +++++++++++++------- vgasrc/vgainit.c | 56 +++++++------------------------------------------------ 3 files changed, 28 insertions(+), 66 deletions(-) diff --git a/vgasrc/Kconfig b/vgasrc/Kconfig index 400e8da..bc1ea48 100644 --- a/vgasrc/Kconfig +++ b/vgasrc/Kconfig @@ -90,19 +90,17 @@ menu "VGA ROM" Support emulating text mode features when only a framebuffer is available. - config VGA_ALLOCATE_EXTRA_STACK + config VGA_EXTRA_STACK depends on BUILD_VGABIOS - bool "Allocate an internal stack for 16bit interrupt entry point" + bool "Use an extra stack located in the EBDA" default y help - Attempt to allocate (via BIOS PMM call) an internal stack - for the legacy 16bit 0x10 interrupt entry point. This - reduces the amount of space on the caller's stack that - SeaVGABIOS uses. - - config VGA_EXTRA_STACK_SIZE - int - default 512 + Use space at the end of the first 1KiB of the EBDA for an + internal stack when the legacy 16bit 0x10 interrupt entry + point is called. This reduces the amount of space on the + caller's stack that SeaVGABIOS uses. Normally the first + 1KiB of the EBDA is reserved for the main BIOS, but + SeaBIOS does not use this space. config VGA_VBE depends on BUILD_VGABIOS diff --git a/vgasrc/vgaentry.S b/vgasrc/vgaentry.S index f9cf656..2e4b200 100644 --- a/vgasrc/vgaentry.S +++ b/vgasrc/vgaentry.S @@ -104,15 +104,19 @@ entry_10: ENTRY_ARG_VGA handle_10 iretw +#define BDA_ebda_seg 0x0e + // Entry point using extra stack DECLFUNC entry_10_extrastack entry_10_extrastack: cli cld - pushw %ds // Set %ds:%eax to space on ExtraStack + pushw %ds // Set %ds:%eax to end of first 1K of EBDA pushl %eax - movw %cs:ExtraStackSeg, %ds - movl $(CONFIG_VGA_EXTRA_STACK_SIZE-PUSHBREGS_size-16), %eax + movw $SEG_BDA, %ax + movw %ax, %ds + movw BDA_ebda_seg, %ds + movl $(1024-PUSHBREGS_size-16), %eax SAVEBREGS_POP_DSEAX // Save registers on extra stack movl %esp, PUSHBREGS_size+8(%eax) movw %ss, PUSHBREGS_size+12(%eax) @@ -145,11 +149,13 @@ entry_timer_hook: entry_timer_hook_extrastack: cli cld - pushw %ds // Set %ds:%eax to space on ExtraStack + pushw %ds // Set %ds:%eax to end of first 1K of EBDA pushl %eax - movw %cs:ExtraStackSeg, %ds - movl $(CONFIG_VGA_EXTRA_STACK_SIZE-PUSHBREGS_size-8), %eax - SAVEBREGS_POP_DSEAX + movw $SEG_BDA, %ax + movw %ax, %ds + movw BDA_ebda_seg, %ds + movl $(1024-PUSHBREGS_size-8), %eax + SAVEBREGS_POP_DSEAX // Save registers on extra stack movl %esp, PUSHBREGS_size(%eax) movw %ss, PUSHBREGS_size+4(%eax) diff --git a/vgasrc/vgainit.c b/vgasrc/vgainit.c index 8d12261..78d5556 100644 --- a/vgasrc/vgainit.c +++ b/vgasrc/vgainit.c @@ -43,51 +43,6 @@ struct pci_data rom_pci_data VAR16 VISIBLE16 = { /**************************************************************** - * PMM call and extra stack setup - ****************************************************************/ - -u16 ExtraStackSeg VAR16 VISIBLE16; - -static void -allocate_extra_stack(void) -{ - if (!CONFIG_VGA_ALLOCATE_EXTRA_STACK) - return; - u32 pmmscan; - for (pmmscan=0; pmmscan < BUILD_BIOS_SIZE; pmmscan+=16) { - struct pmmheader *pmm = (void*)pmmscan; - if (GET_FARVAR(SEG_BIOS, pmm->signature) != PMM_SIGNATURE) - continue; - if (checksum_far(SEG_BIOS, pmm, GET_FARVAR(SEG_BIOS, pmm->length))) - continue; - struct segoff_s entry = GET_FARVAR(SEG_BIOS, pmm->entry); - dprintf(1, "Attempting to allocate VGA stack via pmm call to %04x:%04x\n" - , entry.seg, entry.offset); - u16 res1, res2; - asm volatile( - "pushl %0\n" - "pushw $(8|1)\n" // Permanent low memory request - "pushl $0xffffffff\n" // Anonymous handle - "pushl $" __stringify(CONFIG_VGA_EXTRA_STACK_SIZE/16) "\n" - "pushw $0x00\n" // PMM allocation request - "lcallw *12(%%esp)\n" - "addl $16, %%esp\n" - "cli\n" - "cld\n" - : "+r" (entry.segoff), "=a" (res1), "=d" (res2) : : "cc", "memory"); - u32 res = res1 | (res2 << 16); - if (!res || res == PMM_FUNCTION_NOT_SUPPORTED) - return; - dprintf(1, "VGA stack allocated at %x\n", res); - SET_VGA(ExtraStackSeg, res >> 4); - extern void entry_10_extrastack(void); - SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10_extrastack)); - return; - } -} - - -/**************************************************************** * Timer hook ****************************************************************/ @@ -110,7 +65,7 @@ hook_timer_irq(void) extern void entry_timer_hook_extrastack(void); struct segoff_s oldirq = GET_IVT(0x08); struct segoff_s newirq = SEGOFF(get_global_seg(), (u32)entry_timer_hook); - if (CONFIG_VGA_ALLOCATE_EXTRA_STACK && GET_GLOBAL(ExtraStackSeg)) + if (CONFIG_VGA_EXTRA_STACK) newirq = SEGOFF(get_global_seg(), (u32)entry_timer_hook_extrastack); dprintf(1, "Hooking hardware timer irq (old=%x new=%x)\n" , oldirq.segoff, newirq.segoff); @@ -177,10 +132,13 @@ vga_post(struct bregs *regs) if (CONFIG_VGA_STDVGA_PORTS) stdvga_build_video_param(); + // Setup int10 entry point extern void entry_10(void); - SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10)); - - allocate_extra_stack(); + extern void entry_10_extrastack(void); + struct segoff_s newirq = SEGOFF(get_global_seg(), (u32)entry_10); + if (CONFIG_VGA_EXTRA_STACK) + newirq = SEGOFF(get_global_seg(), (u32)entry_10_extrastack); + SET_IVT(0x10, newirq); hook_timer_irq(); -- 1.9.3

2 3

Next release
by Kevin O'Connor 01 Feb '15

01 Feb '15

I was originally targeting end of January for the next release, but I'm now planning on pushing that back to mid February. Lets target February 16th as the release date. If you know of any regressions or defects in SeaBIOS, please raise them now. Please consider the code in a "feature freeze" until the next release. Thanks, -Kevin

1 0

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS February 2015