July 2016 - SeaBIOS - mail.coreboot.org

[PATCH 0/5] serial console support
by Gerd Hoffmann Oct. 13, 2016

Oct. 13, 2016

Hi, Next round of serial console patches, Still not ready to merge. Headline feature of this version is split mode (i.e. output on both vga and serial). Have a initial working implementation now, logic is simliar to the vgabios timer hook (as suggested by Kevin). Also changed the output logic, down to a one-cell buffer (char+attr) for output. Cursor updates are simply written to BDA now, with the actual move being done lazily when printing the next character or checking for keyboard input. That is especially useful for splitmode as we can simply skip the cursor position updates and let the vgabios do them instead. TODO list: * compile time (CONFIG_*) option. * input handling cleanups. * implement missing int10h functions. * more testing. cheers, Gerd Gerd Hoffmann (5): std: add cp437 to unicode map kbd: make enqueue_key public, add ascii_to_keycode paravirt: read QEMU_CFG_NOGRAPHIC, store in etc/sercon-enable romfile add serial console support [wip] sercon: initial split-output implementation Makefile | 7 +- src/clock.c | 1 + src/fw/paravirt.c | 2 + src/kbd.c | 17 +- src/misc.c | 2 + src/optionroms.c | 9 +- src/romlayout.S | 39 ++++ src/sercon.c | 621 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/std/cp437.c | 275 ++++++++++++++++++++++++ src/std/cp437.h | 1 + src/util.h | 5 + 11 files changed, 974 insertions(+), 5 deletions(-) create mode 100644 src/sercon.c create mode 100644 src/std/cp437.c create mode 100644 src/std/cp437.h -- 1.8.3.1

3 16

[PATCH v2 0/6] tpm: Extend PCRs in all available PCR banks
by Stefan Berger Aug. 4, 2016

Aug. 4, 2016

This series of patches extends the TPM2 code to extend the BIOS related PCRs 0-7 in all available banks. This prevents that these PCRs remain untouched and filled with bogus values by applications. For example, the SHA1 hash is extended into the SHA256 bank. The value that is extended into this bank is essentially a SHA1 with zero bytes used for filling it to the size of a sha256 hash. This is done for all PCR banks of the TPM2 where these PCRs are available. In v2 of this series I also extended the log functions for logging the additional hashes. So there are more patches now. Regards, Stefan Stefan Berger (6): tpm: Retrieve the PCR Bank configuration tpm: Restructure tpm20_extend to use buffer and take hash as parameter tpm: Extend tpm20_extend to support extending to multiple PCR banks tpm: Move tpm_log_init to a later point tpm: Adjust the TPM2 log header to show all hashes tpm: Append to TPM2 log the hashes used for PCR extension src/std/tcg.h | 78 +++++++++++-- src/tcgbios.c | 348 ++++++++++++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 371 insertions(+), 55 deletions(-) -- 2.5.5

2 10

[QUESTION]stuck in SeaBIOS and vm can not be reset any more
by Xulei (Stone) July 29, 2016

July 29, 2016

Hi, all: Recently when i try to reset a vm, I find it may be stuck in SeaBIOS. I use a shell script to continuously reset a vm to see what may happen. #!/bin/bash while((1)) do virsh reset VMNAME sleep 1 done After one day, the vm is stuck. Looking from the following seabios log, it seems seabios stops at "PCI: Using 00:02.0 for primary VGA", and can not execute handle_smp() any more. What may be the reason? ============My SeaBIOS log============ 2016-07-26 14:58:49PCI: Using 00:02.0 for primary VGA 2016-07-26 14:58:51In resume (status=0) 2016-07-26 14:58:51In 32bit resume 2016-07-26 14:58:51Attempting a hard reboot 2016-07-26 14:58:51SeaBIOS (version rel-1.9.1-0-gb3ef39f-20160720_133625-HGH1000003484) 2016-07-26 14:58:51BUILD: gcc: (GCC) 4.8.3 20140911 (EulerOS 4.8.3-10) binutils: version 2.23.52.0.1-55 20130226 2016-07-26 14:58:51No Xen hypervisor found. 2016-07-26 14:58:51Running on QEMU (i440fx) 2016-07-26 14:58:51Running on KVM 2016-07-26 14:58:51RamSize: 0xc0000000 [cmos] 2016-07-26 14:58:51Relocating init from 0x000dc320 to 0xbffad7e0 (size 75664) 2016-07-26 14:58:51Found QEMU fw_cfg 2016-07-26 14:58:51QEMU fw_cfg DMA interface supported 2016-07-26 14:58:51RamBlock: addr 0x0000000000000000 len 0x00000000c0000000 [e820] 2016-07-26 14:58:51RamBlock: addr 0x0000000100000000 len 0x0000000040000000 [e820] 2016-07-26 14:58:51Moving pm_base to 0x600 2016-07-26 14:58:51boot order: 2016-07-26 14:58:511: /pci@i0cf8/scsi@4/channel@0/disk@0,0 2016-07-26 14:58:512: HALT 2016-07-26 14:58:51=== PCI bus & bridge init === 2016-07-26 14:58:51PCI: pci_bios_init_bus_rec bus = 0x0 2016-07-26 14:58:51=== PCI device probing === 2016-07-26 14:58:51Found 10 PCI devices (max PCI bus is 00) 2016-07-26 14:58:51=== PCI new allocation pass #1 === 2016-07-26 14:58:51PCI: check devices 2016-07-26 14:58:51=== PCI new allocation pass #2 === 2016-07-26 14:58:51PCI: IO: c000 - c1af 2016-07-26 14:58:51PCI: 32: 00000000c0000000 - 00000000fec00000 2016-07-26 14:58:51PCI: map device bdf=00:1f.0 bar 0, addr 0000c000, size 00000100 [io] 2016-07-26 14:58:51PCI: map device bdf=00:04.0 bar 0, addr 0000c100, size 00000040 [io] 2016-07-26 14:58:51PCI: map device bdf=00:01.2 bar 4, addr 0000c140, size 00000020 [io] 2016-07-26 14:58:51PCI: map device bdf=00:03.0 bar 0, addr 0000c160, size 00000020 [io] 2016-07-26 14:58:51PCI: map device bdf=00:05.0 bar 0, addr 0000c180, size 00000020 [io] 2016-07-26 14:58:51PCI: map device bdf=00:01.1 bar 4, addr 0000c1a0, size 00000010 [io] 2016-07-26 14:58:51PCI: map device bdf=00:03.0 bar 6, addr feb80000, size 00040000 [mem] 2016-07-26 14:58:51PCI: map device bdf=00:02.0 bar 6, addr febc0000, size 00010000 [mem] 2016-07-26 14:58:51PCI: map device bdf=00:02.0 bar 1, addr febd0000, size 00001000 [mem] 2016-07-26 14:58:51PCI: map device bdf=00:03.0 bar 1, addr febd1000, size 00001000 [mem] 2016-07-26 14:58:51PCI: map device bdf=00:04.0 bar 1, addr febd2000, size 00001000 [mem] 2016-07-26 14:58:51PCI: map device bdf=00:05.0 bar 1, addr febd3000, size 00001000 [mem] 2016-07-26 14:58:51PCI: map device bdf=00:02.0 bar 0, addr fc000000, size 02000000 [prefmem] 2016-07-26 14:58:51PCI: init bdf=00:00.0 id=8086:1237 2016-07-26 14:58:51PCI: init bdf=00:01.0 id=8086:7000 2016-07-26 14:58:51PIIX3/PIIX4 init: elcr=00 0c 2016-07-26 14:58:51PCI: init bdf=00:01.1 id=8086:7010 2016-07-26 14:58:51PCI: init bdf=00:01.2 id=8086:7020 2016-07-26 14:58:51PCI: init bdf=00:01.3 id=8086:7113 2016-07-26 14:58:51Using pmtimer, ioport 0x608 2016-07-26 14:58:51PCI: init bdf=00:02.0 id=1013:00b8 2016-07-26 14:58:51PCI: init bdf=00:03.0 id=1af4:1000 2016-07-26 14:58:51PCI: init bdf=00:04.0 id=1af4:1004 2016-07-26 14:58:51PCI: init bdf=00:05.0 id=1af4:1003 2016-07-26 14:58:51PCI: init bdf=00:1f.0 id=1af4:8888 2016-07-26 14:58:51PCI: Using 00:02.0 for primary VGA <---------- stuck here 2016-07-26 14:58:52In resume (status=0) 2016-07-26 14:58:52In 32bit resume 2016-07-26 14:58:53Attempting a hard reboot 2016-07-26 14:58:53SeaBIOS (version rel-1.9.1-0-gb3ef39f-20160720_133625-HGH1000003484) 2016-07-26 14:58:53BUILD: gcc: (GCC) 4.8.3 20140911 (EulerOS 4.8.3-10) binutils: version 2.23.52.0.1-55 20130226 2016-07-26 14:58:53No Xen hypervisor found. 2016-07-26 14:58:53Running on QEMU (i440fx) 2016-07-26 14:58:53Running on KVM 2016-07-26 14:58:53RamSize: 0xc0000000 [cmos] 2016-07-26 14:58:53Relocating init from 0x000dc320 to 0xbffad7e0 (size 75664) 2016-07-26 14:58:53Found QEMU fw_cfg 2016-07-26 14:58:53QEMU fw_cfg DMA interface supported 2016-07-26 14:58:53RamBlock: addr 0x0000000000000000 len 0x00000000c0000000 [e820] 2016-07-26 14:58:53RamBlock: addr 0x0000000100000000 len 0x0000000040000000 [e820] 2016-07-26 14:58:53Moving pm_base to 0x600 2016-07-26 14:58:53boot order: 2016-07-26 14:58:531: /pci@i0cf8/scsi@4/channel@0/disk@0,0 2016-07-26 14:58:532: HALT 2016-07-26 14:58:53=== PCI bus & bridge init === 2016-07-26 14:58:53PCI: pci_bios_init_bus_rec bus = 0x0 2016-07-26 14:58:53=== PCI device probing === 2016-07-26 14:58:53Found 10 PCI devices (max PCI bus is 00) 2016-07-26 14:58:53=== PCI new allocation pass #1 === 2016-07-26 14:58:53PCI: check devices 2016-07-26 14:58:53=== PCI new allocation pass #2 === 2016-07-26 14:58:53PCI: IO: c000 - c1af 2016-07-26 14:58:53PCI: 32: 00000000c0000000 - 00000000fec00000 2016-07-26 14:58:53PCI: map device bdf=00:1f.0 bar 0, addr 0000c000, size 00000100 [io] 2016-07-26 14:58:53PCI: map device bdf=00:04.0 bar 0, addr 0000c100, size 00000040 [io] 2016-07-26 14:58:53PCI: map device bdf=00:01.2 bar 4, addr 0000c140, size 00000020 [io] 2016-07-26 14:58:53PCI: map device bdf=00:03.0 bar 0, addr 0000c160, size 00000020 [io] 2016-07-26 14:58:53PCI: map device bdf=00:05.0 bar 0, addr 0000c180, size 00000020 [io] 2016-07-26 14:58:53PCI: map device bdf=00:01.1 bar 4, addr 0000c1a0, size 00000010 [io] 2016-07-26 14:58:53PCI: map device bdf=00:03.0 bar 6, addr feb80000, size 00040000 [mem] 2016-07-26 14:58:53PCI: map device bdf=00:02.0 bar 6, addr febc0000, size 00010000 [mem] 2016-07-26 14:58:53PCI: map device bdf=00:02.0 bar 1, addr febd0000, size 00001000 [mem] 2016-07-26 14:58:53PCI: map device bdf=00:03.0 bar 1, addr febd1000, size 00001000 [mem] 2016-07-26 14:58:53PCI: map device bdf=00:04.0 bar 1, addr febd2000, size 00001000 [mem] 2016-07-26 14:58:53PCI: map device bdf=00:05.0 bar 1, addr febd3000, size 00001000 [mem] 2016-07-26 14:58:53PCI: map device bdf=00:02.0 bar 0, addr fc000000, size 02000000 [prefmem] 2016-07-26 14:58:53PCI: init bdf=00:00.0 id=8086:1237 2016-07-26 14:58:53PCI: init bdf=00:01.0 id=8086:7000 2016-07-26 14:58:53PIIX3/PIIX4 init: elcr=00 0c 2016-07-26 14:58:53PCI: init bdf=00:01.1 id=8086:7010 2016-07-26 14:58:53PCI: init bdf=00:01.2 id=8086:7020 2016-07-26 14:58:53PCI: init bdf=00:01.3 id=8086:7113 2016-07-26 14:58:53Using pmtimer, ioport 0x608 2016-07-26 14:58:53PCI: init bdf=00:02.0 id=1013:00b8 2016-07-26 14:58:53PCI: init bdf=00:03.0 id=1af4:1000 2016-07-26 14:58:53PCI: init bdf=00:04.0 id=1af4:1004 2016-07-26 14:58:53PCI: init bdf=00:05.0 id=1af4:1003 2016-07-26 14:58:53PCI: init bdf=00:1f.0 id=1af4:8888 2016-07-26 14:58:53PCI: Using 00:02.0 for primary VGA <---- i wait here for 3 days, seabios can not go on 2016-07-29 11:33:56In resume (status=0) 2016-07-29 11:33:56In 32bit resume 2016-07-29 11:33:56Attempting a hard reboot 2016-07-29 11:33:56SeaBIOS (version rel-1.9.1-0-gb3ef39f-20160720_133625-HGH1000003484) 2016-07-29 11:33:56BUILD: gcc: (GCC) 4.8.3 20140911 (EulerOS 4.8.3-10) binutils: version 2.23.52.0.1-55 20130226 2016-07-29 11:33:56No Xen hypervisor found. 2016-07-29 11:33:56Running on QEMU (i440fx) 2016-07-29 11:33:56Running on KVM 2016-07-29 11:33:56RamSize: 0xc0000000 [cmos] 2016-07-29 11:33:56Relocating init from 0x000dc320 to 0xbffad7e0 (size 75664) 2016-07-29 11:33:56Found QEMU fw_cfg 2016-07-29 11:33:56QEMU fw_cfg DMA interface supported 2016-07-29 11:33:56RamBlock: addr 0x0000000000000000 len 0x00000000c0000000 [e820] 2016-07-29 11:33:56RamBlock: addr 0x0000000100000000 len 0x0000000040000000 [e820] 2016-07-29 11:33:56Moving pm_base to 0x600 2016-07-29 11:33:56boot order: 2016-07-29 11:33:561: /pci@i0cf8/scsi@4/channel@0/disk@0,0 2016-07-29 11:33:562: HALT 2016-07-29 11:33:56=== PCI bus & bridge init === 2016-07-29 11:33:56PCI: pci_bios_init_bus_rec bus = 0x0 2016-07-29 11:33:56=== PCI device probing === 2016-07-29 11:33:56Found 10 PCI devices (max PCI bus is 00) 2016-07-29 11:33:56=== PCI new allocation pass #1 === 2016-07-29 11:33:56PCI: check devices 2016-07-29 11:33:56=== PCI new allocation pass #2 === 2016-07-29 11:33:56PCI: IO: c000 - c1af 2016-07-29 11:33:56PCI: 32: 00000000c0000000 - 00000000fec00000 2016-07-29 11:33:56PCI: map device bdf=00:1f.0 bar 0, addr 0000c000, size 00000100 [io] 2016-07-29 11:33:56PCI: map device bdf=00:04.0 bar 0, addr 0000c100, size 00000040 [io] 2016-07-29 11:33:56PCI: map device bdf=00:01.2 bar 4, addr 0000c140, size 00000020 [io] 2016-07-29 11:33:56PCI: map device bdf=00:03.0 bar 0, addr 0000c160, size 00000020 [io] 2016-07-29 11:33:56PCI: map device bdf=00:05.0 bar 0, addr 0000c180, size 00000020 [io] 2016-07-29 11:33:56PCI: map device bdf=00:01.1 bar 4, addr 0000c1a0, size 00000010 [io] 2016-07-29 11:33:56PCI: map device bdf=00:03.0 bar 6, addr feb80000, size 00040000 [mem] 2016-07-29 11:33:56PCI: map device bdf=00:02.0 bar 6, addr febc0000, size 00010000 [mem] 2016-07-29 11:33:56PCI: map device bdf=00:02.0 bar 1, addr febd0000, size 00001000 [mem] 2016-07-29 11:33:56PCI: map device bdf=00:03.0 bar 1, addr febd1000, size 00001000 [mem] 2016-07-29 11:33:56PCI: map device bdf=00:04.0 bar 1, addr febd2000, size 00001000 [mem] 2016-07-29 11:33:56PCI: map device bdf=00:05.0 bar 1, addr febd3000, size 00001000 [mem] 2016-07-29 11:33:56PCI: map device bdf=00:02.0 bar 0, addr fc000000, size 02000000 [prefmem] 2016-07-29 11:33:56PCI: init bdf=00:00.0 id=8086:1237 2016-07-29 11:33:56PCI: init bdf=00:01.0 id=8086:7000 2016-07-29 11:33:56PIIX3/PIIX4 init: elcr=00 0c 2016-07-29 11:33:56PCI: init bdf=00:01.1 id=8086:7010 2016-07-29 11:33:56PCI: init bdf=00:01.2 id=8086:7020 2016-07-29 11:33:56PCI: init bdf=00:01.3 id=8086:7113 2016-07-29 11:33:56Using pmtimer, ioport 0x608 2016-07-29 11:33:56PCI: init bdf=00:02.0 id=1013:00b8 2016-07-29 11:33:56PCI: init bdf=00:03.0 id=1af4:1000 2016-07-29 11:33:56PCI: init bdf=00:04.0 id=1af4:1004 2016-07-29 11:33:56PCI: init bdf=00:05.0 id=1af4:1003 2016-07-29 11:33:56PCI: init bdf=00:1f.0 id=1af4:8888 2016-07-29 11:33:56PCI: Using 00:02.0 for primary VGA -------------- Xulei (Stone)

1 0

[PATCH] vgabios: Simplify scroll logic
by Kevin O'Connor July 28, 2016

July 28, 2016

Introduce a new function vgafb_scroll() to scroll a window on the screen and update vgabios.c to use only that function for scrolling. This makes the low-level vgafb_move_chars() and vgafb_clear_chars() local to vgafb.c, and it simplifies the callers. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/vgabios.c | 57 ++++++++++++--------------------------------- vgasrc/vgabios.h | 6 ++--- vgasrc/vgafb.c | 70 ++++++++++++++++++++++++++++++++++++++------------------ 3 files changed, 64 insertions(+), 69 deletions(-) diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index cfb6ba2..2c8cc79 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -198,15 +198,10 @@ write_teletype(struct cursorpos *pcp, struct carattr ca) if (pcp->y > nbrows) { pcp->y--; - struct cursorpos dest = {0, 0, pcp->page}; - struct cursorpos src = {0, 1, pcp->page}; - struct cursorpos size = {GET_BDA(video_cols), nbrows}; - vgafb_move_chars(dest, src, size); - - struct cursorpos clr = {0, nbrows, pcp->page}; + struct cursorpos win = {0, 0, pcp->page}; + struct cursorpos winsize = {GET_BDA(video_cols), nbrows+1}; struct carattr attr = {' ', 0, 0}; - struct cursorpos clrsize = {GET_BDA(video_cols), 1}; - vgafb_clear_chars(clr, attr, clrsize); + vgafb_scroll(win, winsize, 1, attr); } } @@ -400,6 +395,7 @@ handle_1005(struct bregs *regs) static void verify_scroll(struct bregs *regs, int dir) { + // Verify parameters u8 ulx = regs->cl, uly = regs->ch, lrx = regs->dl, lry = regs->dh; u16 nbrows = GET_BDA(video_rows) + 1; if (lry >= nbrows) @@ -410,41 +406,16 @@ verify_scroll(struct bregs *regs, int dir) int wincols = lrx - ulx + 1, winrows = lry - uly + 1; if (wincols <= 0 || winrows <= 0) return; - - u8 page = GET_BDA(video_page); - int clearlines = regs->al, movelines = winrows - clearlines; - if (!clearlines || movelines <= 0) { - // Clear whole area. - struct cursorpos clr = {ulx, uly, page}; - struct carattr attr = {' ', regs->bh, 1}; - struct cursorpos clrsize = {wincols, winrows}; - vgafb_clear_chars(clr, attr, clrsize); - return; - } - - if (dir > 0) { - // Normal scroll - struct cursorpos dest = {ulx, uly, page}; - struct cursorpos src = {ulx, uly + clearlines, page}; - struct cursorpos size = {wincols, movelines}; - vgafb_move_chars(dest, src, size); - - struct cursorpos clr = {ulx, uly + movelines, page}; - struct carattr attr = {' ', regs->bh, 1}; - struct cursorpos clrsize = {wincols, clearlines}; - vgafb_clear_chars(clr, attr, clrsize); - } else { - // Scroll down - struct cursorpos dest = {ulx, uly + clearlines, page}; - struct cursorpos src = {ulx, uly, page}; - struct cursorpos size = {wincols, movelines}; - vgafb_move_chars(dest, src, size); - - struct cursorpos clr = {ulx, uly, page}; - struct carattr attr = {' ', regs->bh, 1}; - struct cursorpos clrsize = {wincols, clearlines}; - vgafb_clear_chars(clr, attr, clrsize); - } + int lines = regs->al; + if (lines >= winrows) + lines = 0; + lines *= dir; + + // Scroll (or clear) window + struct cursorpos win = {ulx, uly, GET_BDA(video_page)}; + struct cursorpos winsize = {wincols, winrows}; + struct carattr attr = {' ', regs->bh, 1}; + vgafb_scroll(win, winsize, lines, attr); } static void diff --git a/vgasrc/vgabios.h b/vgasrc/vgabios.h index 831f694..9fbfb14 100644 --- a/vgasrc/vgabios.h +++ b/vgasrc/vgabios.h @@ -126,10 +126,8 @@ extern struct video_func_static static_functionality; void init_gfx_op(struct gfx_op *op, struct vgamode_s *vmode_g); void handle_gfx_op(struct gfx_op *op); void *text_address(struct cursorpos cp); -void vgafb_move_chars(struct cursorpos dest - , struct cursorpos src, struct cursorpos movesize); -void vgafb_clear_chars(struct cursorpos dest - , struct carattr ca, struct cursorpos movesize); +void vgafb_scroll(struct cursorpos win, struct cursorpos winsize + , int lines, struct carattr ca); void vgafb_write_char(struct cursorpos cp, struct carattr ca); struct carattr vgafb_read_char(struct cursorpos cp); void vgafb_write_pixel(u8 color, u16 x, u16 y); diff --git a/vgasrc/vgafb.c b/vgasrc/vgafb.c index 58c60ad..bd1c8dd 100644 --- a/vgasrc/vgafb.c +++ b/vgasrc/vgafb.c @@ -346,7 +346,7 @@ handle_gfx_op(struct gfx_op *op) // Move characters when in graphics mode. static void gfx_move_chars(struct vgamode_s *vmode_g, struct cursorpos dest - , struct cursorpos src, struct cursorpos movesize) + , struct cursorpos movesize, int lines) { struct gfx_op op; init_gfx_op(&op, vmode_g); @@ -355,23 +355,23 @@ gfx_move_chars(struct vgamode_s *vmode_g, struct cursorpos dest int cheight = GET_BDA(char_height); op.y = dest.y * cheight; op.ylen = movesize.y * cheight; - op.srcy = src.y * cheight; + op.srcy = op.y + lines * cheight; op.op = GO_MEMMOVE; handle_gfx_op(&op); } // Clear area of screen in graphics mode. static void -gfx_clear_chars(struct vgamode_s *vmode_g, struct cursorpos dest - , struct carattr ca, struct cursorpos clearsize) +gfx_clear_chars(struct vgamode_s *vmode_g, struct cursorpos win + , struct cursorpos winsize, struct carattr ca) { struct gfx_op op; init_gfx_op(&op, vmode_g); - op.x = dest.x * 8; - op.xlen = clearsize.x * 8; + op.x = win.x * 8; + op.xlen = winsize.x * 8; int cheight = GET_BDA(char_height); - op.y = dest.y * cheight; - op.ylen = clearsize.y * cheight; + op.y = win.y * cheight; + op.ylen = winsize.y * cheight; op.pixels[0] = ca.attr; if (vga_emulate_text()) op.pixels[0] = ca.attr >> 4; @@ -580,45 +580,71 @@ text_address(struct cursorpos cp) } // Move characters on screen. -void -vgafb_move_chars(struct cursorpos dest - , struct cursorpos src, struct cursorpos movesize) +static void +vgafb_move_chars(struct cursorpos dest, struct cursorpos movesize, int lines) { struct vgamode_s *vmode_g = get_current_mode(); if (!vmode_g) return; - vgafb_set_swcursor(0); if (GET_GLOBAL(vmode_g->memmodel) != MM_TEXT) { - gfx_move_chars(vmode_g, dest, src, movesize); + gfx_move_chars(vmode_g, dest, movesize, lines); return; } int stride = GET_BDA(video_cols) * 2; - memmove_stride(GET_GLOBAL(vmode_g->sstart) - , text_address(dest), text_address(src) + void *dest_addr = text_address(dest), *src_addr = dest_addr + lines * stride; + memmove_stride(GET_GLOBAL(vmode_g->sstart), dest_addr, src_addr , movesize.x * 2, stride, movesize.y); } // Clear area of screen. -void -vgafb_clear_chars(struct cursorpos dest - , struct carattr ca, struct cursorpos clearsize) +static void +vgafb_clear_chars(struct cursorpos win, struct cursorpos winsize + , struct carattr ca) { struct vgamode_s *vmode_g = get_current_mode(); if (!vmode_g) return; - vgafb_set_swcursor(0); if (GET_GLOBAL(vmode_g->memmodel) != MM_TEXT) { - gfx_clear_chars(vmode_g, dest, ca, clearsize); + gfx_clear_chars(vmode_g, win, winsize, ca); return; } int stride = GET_BDA(video_cols) * 2; u16 attr = ((ca.use_attr ? ca.attr : 0x07) << 8) | ca.car; - memset16_stride(GET_GLOBAL(vmode_g->sstart), text_address(dest), attr - , clearsize.x * 2, stride, clearsize.y); + memset16_stride(GET_GLOBAL(vmode_g->sstart), text_address(win), attr + , winsize.x * 2, stride, winsize.y); +} + +// Scroll characters within a window on the screen +void +vgafb_scroll(struct cursorpos win, struct cursorpos winsize + , int lines, struct carattr ca) +{ + vgafb_set_swcursor(0); + if (!lines) { + // Clear window + vgafb_clear_chars(win, winsize, ca); + } else if (lines > 0) { + // Scroll the window up (eg, from page down key) + winsize.y -= lines; + vgafb_move_chars(win, winsize, lines); + + win.y += winsize.y; + winsize.y = lines; + vgafb_clear_chars(win, winsize, ca); + } else { + // Scroll the window down (eg, from page up key) + win.y -= lines; + winsize.y += lines; + vgafb_move_chars(win, winsize, lines); + + win.y += lines; + winsize.y = -lines; + vgafb_clear_chars(win, winsize, ca); + } } // Write a character to the screen. -- 2.5.5

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Re: [SeaBIOS] How CPU executes bios code before copying bios to shadow ram?
by Kevin O'Connor July 26, 2016

July 26, 2016

On Tue, Jul 26, 2016 at 03:02:02PM +0800, Li Wang wrote: > Hi all, > I am reading seaBios code, and I have a question about the shadow memory > copy part. In fw/shadow.c:make_bios_writable_intel() reads pam0 to see if > shadow memory is already readable (if pam0's fourth bit is set), if pam0 > shows shadow memory is not readable running __make_bios_writable_intel from > high-memory flash location (statements marked green below). > But in my understanding the entry point of bios is 0xffff:fff0, then it > jumps to 0xf000:e05b, which points to memory space in shadowing, but before > __make_bios_writable_intel copying bios from high-memory flash to shadow > memory, shadow memory is disabled, so these codes are forwarded to > high-memory flash, including code to read pam0 before invoking > __make_bios_writable_intel (statement marked red below). Why these codes > are not relocate to high-memory flash, but only the invocation of > __make_bios_writable_intel is need to be relocated? > If shadow ram is present and readable, how cpu execute bios codes in > 0xf000:xxxx before copying them to shadow ram? This code only runs on QEMU and is very specific to the quirky way that QEMU implements the pam registers. When emulation starts, QEMU places a read-only copy of the code in 0xe0000-0x100000. When SeaBIOS requests that 0xc0000-0x100000 be read/writable ram by writing to the pam registers in __make_bios_writable_intel(), then qemu converts the region to uninitialized memory. This is why __make_bios_writable_intel() needs to run from the copy of the code in the "flash" location at the end of the first 4Gig of ram. The make_bios_writable_intel() code can run in 0xe0000-0x100000 because prior to __make_bios_writable_intel() QEMU places a read-only copy of the code there and after __make_bios_writable_intel() SeaBIOS has restored the code by copying the code back to that ram. -Kevin

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How CPU executes bios code before copying bios to shadow ram?
by Li Wang July 26, 2016

July 26, 2016

Hi all, I am reading seaBios code, and I have a question about the shadow memory copy part. In fw/shadow.c:make_bios_writable_intel() reads pam0 to see if shadow memory is already readable (if pam0's fourth bit is set), if pam0 shows shadow memory is not readable running __make_bios_writable_intel from high-memory flash location (statements marked green below). But in my understanding the entry point of bios is 0xffff:fff0, then it jumps to 0xf000:e05b, which points to memory space in shadowing, but before __make_bios_writable_intel copying bios from high-memory flash to shadow memory, shadow memory is disabled, so these codes are forwarded to high-memory flash, including code to read pam0 before invoking __make_bios_writable_intel (statement marked red below). Why these codes are not relocate to high-memory flash, but only the invocation of __make_bios_writable_intel is need to be relocated? If shadow ram is present and readable, how cpu execute bios codes in 0xf000:xxxx before copying them to shadow ram? 60 static void 61 make_bios_writable_intel(u16 bdf, u32 pam0) 62 { 63 int reg = pci_config_readb(bdf, pam0); 64 if (!(reg & 0x10)) { 65 // QEMU doesn't fully implement the piix shadow capabilities - 66 // if ram isn't backing the bios segment when shadowing is 67 // disabled, the code itself won't be in memory. So, run the 68 // code from the high-memory flash location. 69 u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET; 70 void (*func)(u16 bdf, u32 pam0) = (void*)pos; 71 func(bdf, pam0); 72 return; 73 } 74 // Ram already present - just enable writes 75 __make_bios_writable_intel(bdf, pam0); 76 } Thanks

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[PATCH 0/3] tpm: Extend PCRs in all available PCR banks
by Stefan Berger July 21, 2016

July 21, 2016

This series of patches extends the TPM2 code to extend the BIOS related PCRs 0-7 in all available banks. This prevents that these PCRs remain untouched and filled with bogus values by applications. For example, the SHA1 hash is extended into the SHA256 bank. The value that is extended into this bank is essentially a SHA1 with zero bytes used for filling it to the size of a sha256 hash. This is done for all PCR banks of the TPM2 where these PCRs are available. Regards, Stefan Stefan Berger (3): tpm: Retrieve the PCR Bank configuration tpm: Restructure tpm20_extend to use buffer and take hash as parameter tpm: Extend tpm20_extend to support extending to multiple PCR banks src/std/tcg.h | 45 +++++++++++++-- src/tcgbios.c | 175 +++++++++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 201 insertions(+), 19 deletions(-) -- 2.5.5

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[PATCH] restore MSRs on S3 resume
by Paolo Bonzini July 13, 2016

July 13, 2016

Currently the MTRRs and MSR_IA32_FEATURE_CONTROL are not restored on S3 resume. Because these have to be applied to all processors, SMP setup has to be added to S3 resume. There are two differences between the boot and resume paths. First, romfile_* is not usable in the resume paths so we move the call out of smp_setup and into a new function smp_boot_setup. Second, smp_msr has to be walked on the BSP as well, so we extract that out of handle_smp and into a new function smp_write_msrs. Then, resume can call smp_write_msrs on the BSP followed by smp_setup to initialize the APs. Reported-by: Laszlo Ersek <lersek(a)redhat.com> Signed-off-by: Paolo Bonzini <pbonzini(a)redhat.com> --- src/fw/paravirt.c | 1 + src/fw/smp.c | 28 +++++++++++++++++++++++----- src/resume.c | 1 + src/util.h | 2 ++ 4 files changed, 27 insertions(+), 5 deletions(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index e8e419e..9189672 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -160,6 +160,7 @@ qemu_platform_setup(void) // Initialize mtrr, msr_feature_control and smp mtrr_setup(); msr_feature_control_setup(); + smp_boot_setup(); smp_setup(); // Create bios tables diff --git a/src/fw/smp.c b/src/fw/smp.c index 6e706e4..64e76b6 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -46,6 +46,15 @@ int apic_id_is_present(u8 apic_id) return !!(FoundAPICIDs[apic_id/32] & (1ul << (apic_id % 32))); } +static void +smp_write_msrs(void) +{ + // MTRR and MSR_IA32_FEATURE_CONTROL setup + int i; + for (i=0; i<smp_msr_count; i++) + wrmsr(smp_msr[i].index, smp_msr[i].val); +} + void VISIBLE32FLAT handle_smp(void) { @@ -58,10 +67,7 @@ handle_smp(void) u8 apic_id = ebx>>24; dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id); - // MTRR and MSR_IA32_FEATURE_CONTROL setup - int i; - for (i=0; i<smp_msr_count; i++) - wrmsr(smp_msr[i].index, smp_msr[i].val); + smp_write_msrs(); // Set bit on FoundAPICIDs FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32)); @@ -73,6 +79,12 @@ handle_smp(void) u32 SMPLock __VISIBLE; u32 SMPStack __VISIBLE; +void +smp_boot_setup(void) +{ + MaxCountCPUs = romfile_loadint("etc/max-cpus", 0); +} + // find and initialize the CPUs by launching a SIPI to them void smp_setup(void) @@ -141,10 +153,16 @@ smp_setup(void) // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; - MaxCountCPUs = romfile_loadint("etc/max-cpus", 0); if (!MaxCountCPUs || MaxCountCPUs < CountCPUs) MaxCountCPUs = CountCPUs; dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", CountCPUs, MaxCountCPUs); } + +void +smp_resume(void) +{ + smp_write_msrs(); + smp_setup(); +} diff --git a/src/resume.c b/src/resume.c index a5465d8..3a26f84 100644 --- a/src/resume.c +++ b/src/resume.c @@ -97,6 +97,7 @@ s3_resume(void) pic_setup(); smm_setup(); + smp_resume(); pci_resume(); diff --git a/src/util.h b/src/util.h index cba3359..510da73 100644 --- a/src/util.h +++ b/src/util.h @@ -131,7 +131,9 @@ void smm_setup(void); // fw/smp.c extern u32 MaxCountCPUs; void wrmsr_smp(u32 index, u64 val); +void smp_boot_setup(void); void smp_setup(void); +void smp_resume(void); int apic_id_is_present(u8 apic_id); // hw/dma.c -- 1.8.3.1

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Re: [SeaBIOS] GeodeVGA is not initialized during SeaBIOS execution
by Kevin O'Connor July 12, 2016

July 12, 2016

On Mon, Jul 11, 2016 at 08:25:14PM +0300, Andrey Korolyov wrote: > Awesome suggestion, turns out that the PCI_COMMAND_IO is not set. > Removing the check entirely would lead to an incomplete PCI > initialization but placing VGA ROM to vgaroms/seavgabios.rom could do > the trick. So, out of curiosity, does Geode SeaVGABIOS work on this board if one of the above is done? I haven't seen a recent confirmation that Geode SeaVGABIOS still works. -Kevin

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Re: [SeaBIOS] GeodeVGA is not initialized during SeaBIOS execution
by Kevin O'Connor July 11, 2016

July 11, 2016

On Mon, Jul 11, 2016 at 02:23:12AM +0300, Andrey Korolyov wrote: > Hi, > > as per Kevin`s suggestion, I am posting initialization log (mixed one) > from initialization of the GeodeLX board. As it could be clearly seen > from the log, VGA option ROM was never called and executed during the > initialization sequence, therefore issue with a lack of video output > during SeaBIOS stage on this board looks somehow logical. [1] suggests > that the problem existed long before, as most users of these boards > are Alix owners who do not care about existence of the video output :) Best guess is this check: u16 cmd = pci_config_readw(pci->bdf, PCI_COMMAND); if (!(cmd & PCI_COMMAND_IO && cmd & PCI_COMMAND_MEMORY)) return 0; in optionroms.c:is_pci_vga() is being triggered. You could see if coreboot is not enabling these PCI flags, temporarily disable the check in seabios, or use "vgaroms/seavgabios.rom" instead of "pci1022,2081.rom" for the seavgabios rom. -Kevin

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