OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL
for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file
"etc/msr_feature_control" to advise bits that should be set in
MSR_IA32_FEATURE_CONTROL. If this file exists, SeaBIOS will set the
advised bits in that MSR.
Signed-off-by: Haozhong Zhang <haozhong.zhang(a)intel.com>
Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com>
---
Changes in v3:
* Move msr_feature_control_setup() to paravirt.c.
Changes in v2:
* Call msr_feature_control_setup() before smp_setup().
* Use wrmsr_smp() instead of wrmsr() on BSP.
* Rename smp_mtrr and smp_mtrr_count to smp_msr and smp_msr_count
as they are not only used for MTRR now.
---
src/fw/paravirt.c | 12 +++++++++++-
src/fw/smp.c | 20 ++++++++++----------
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c
index 8ed4380..73a08f0 100644
--- a/src/fw/paravirt.c
+++ b/src/fw/paravirt.c
@@ -131,6 +131,15 @@ qemu_preinit(void)
dprintf(1, "RamSize: 0x%08x [cmos]\n", RamSize);
}
+#define MSR_IA32_FEATURE_CONTROL 0x0000003a
+
+static void msr_feature_control_setup(void)
+{
+ u64 feature_control_bits = romfile_loadint("etc/msr_feature_control", 0);
+ if (feature_control_bits)
+ wrmsr_smp(MSR_IA32_FEATURE_CONTROL, feature_control_bits);
+}
+
void
qemu_platform_setup(void)
{
@@ -149,8 +158,9 @@ qemu_platform_setup(void)
smm_device_setup();
smm_setup();
- // Initialize mtrr and smp
+ // Initialize mtrr, msr_feature_control and smp
mtrr_setup();
+ msr_feature_control_setup();
smp_setup();
// Create bios tables
diff --git a/src/fw/smp.c b/src/fw/smp.c
index 579acdb..6e706e4 100644
--- a/src/fw/smp.c
+++ b/src/fw/smp.c
@@ -10,7 +10,7 @@
#include "output.h" // dprintf
#include "romfile.h" // romfile_loadint
#include "stacks.h" // yield
-#include "util.h" // smp_setup
+#include "util.h" // smp_setup, msr_feature_control_setup
#include "x86.h" // wrmsr
#define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
@@ -20,20 +20,20 @@
#define APIC_ENABLED 0x0100
-static struct { u32 index; u64 val; } smp_mtrr[32];
-static u32 smp_mtrr_count;
+static struct { u32 index; u64 val; } smp_msr[32];
+static u32 smp_msr_count;
void
wrmsr_smp(u32 index, u64 val)
{
wrmsr(index, val);
- if (smp_mtrr_count >= ARRAY_SIZE(smp_mtrr)) {
+ if (smp_msr_count >= ARRAY_SIZE(smp_msr)) {
warn_noalloc();
return;
}
- smp_mtrr[smp_mtrr_count].index = index;
- smp_mtrr[smp_mtrr_count].val = val;
- smp_mtrr_count++;
+ smp_msr[smp_msr_count].index = index;
+ smp_msr[smp_msr_count].val = val;
+ smp_msr_count++;
}
u32 MaxCountCPUs;
@@ -58,10 +58,10 @@ handle_smp(void)
u8 apic_id = ebx>>24;
dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id);
- // MTRR setup
+ // MTRR and MSR_IA32_FEATURE_CONTROL setup
int i;
- for (i=0; i<smp_mtrr_count; i++)
- wrmsr(smp_mtrr[i].index, smp_mtrr[i].val);
+ for (i=0; i<smp_msr_count; i++)
+ wrmsr(smp_msr[i].index, smp_msr[i].val);
// Set bit on FoundAPICIDs
FoundAPICIDs[apic_id/32] |= (1 << (apic_id % 32));
--
2.9.0