SeaBIOS January 2017

seabios@seabios.org

14 participants
22 discussions

[PATCH 0/3] SeaVGABIOS serial console test
by Kevin O'Connor 05 Sep '17

05 Sep '17

Hi Gerd, I was curious to see what the "sercon" stuff would look like in SeaVGABIOS instead of in SeaBIOS. So, I put together a quick prototype. The code is also at: https://github.com/KevinOConnor/seabios/tree/testing This is just a proof-of-concept thing - I didn't implement any of the useful features you have in your series. Specifically, it doesn't unclutter the serial output, doesn't implement cp437 translations, and doesn't handle multi-byte input. It does does have basic input, output, and split-output handling though. I'm not sure if this is better than a SeaBIOS implementation. I suspect it will be easier to handle vga quirks this way. However, handling exotic serial outputs (eg, mmio and usb based) would be better suited in SeaBIOS. Thoughts? -Kevin Kevin O'Connor (3): sercon: Initial support for VGA emulation over serial port sercon: Add basic keyboard input support sercon: Support "split output" mode Makefile | 2 +- vgasrc/Kconfig | 6 + vgasrc/sercon.c | 356 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/vgabios.c | 15 ++- vgasrc/vgabios.h | 5 + vgasrc/vgaentry.S | 7 ++ vgasrc/vgahw.h | 72 ++++++++++- vgasrc/vgainit.c | 12 +- vgasrc/vgautil.h | 24 ++++ 9 files changed, 482 insertions(+), 17 deletions(-) create mode 100644 vgasrc/sercon.c -- 2.5.5

2 12

varlow/extrastack vs code
by Dr. David Alan Gilbert 27 Feb '17

27 Feb '17

Hi, I turned the debug level up to 4 on our smaller (128k) ROM downstream build and seem to have hit a case where it's been layed out so that the 'ExtraStack' is at the same location as some code (display_uuid) which was causing some very random behaviour; from an objdump disassemble of the rom.o that was produced: ef79d: f3 ab rep stos %eax,%es:(%edi) ef79f: 8d 43 08 lea 0x8(%ebx),%eax ef7a2: b1 10 mov $0x10,%cl ef7a4: 8d 54 24 74 lea 0x74(%esp),%edx ef7a8: e8 50 46 ff ff call e3dfd <memcmp> ef7ad: 85 c0 test %eax,%eax ef7af: 0f 84 33 01 00 00 je ef8e8 <ExtraStack+0x110> ef7b5: 8b 15 0c 23 0f 00 mov 0xf230c,%edx ef7bb: 80 7a 06 02 cmpb $0x2,0x6(%edx) ef7bf: 0f b6 43 17 movzbl 0x17(%ebx),%eax ef7c3: 77 0c ja ef7d1 <StackPos+0x1> ef7c5: 0f 85 80 00 00 00 jne ef84b <ExtraStack+0x73> ef7cb: 80 7a 07 05 cmpb $0x5,0x7(%edx) ef7cf: 76 7a jbe ef84b <ExtraStack+0x73> Note the 'ExtraStack+...' where as a few lines before it's maininit for other jumps, then looking at a sorted output of the rom.o.objdump: 000eddf2 l F .text 000000e0 virtio_scsi_add_lun.constprop.113 000eded2 l F .text 0000080d device_hardware_setup 000ee6df l F .text 00001a17 maininit <------------- 000ef790 g *ABS* 00000000 final_varlow_start 000ef790 g O *ABS* 00000004 BootSequence 000ef794 g O *ABS* 00000001 FloppyDOR 000ef798 g O *ABS* 00000008 LastUSBkey 000ef7a0 g O *ABS* 00000001 Ps2ctr 000ef7a4 g O *ABS* 00000004 RTCusers 000ef7a8 g O *ABS* 00000004 TimerLast 000ef7ac g O *ABS* 00000001 HaveAttemptedReboot 000ef7ad g O *ABS* 00000001 Century 000ef7b0 g O *ABS* 00000010 CDRom_locks 000ef7c0 g O *ABS* 00000010 DefaultDPTE 000ef7d0 g O *ABS* 00000004 StackPos 000ef7d8 g O *ABS* 00000801 ExtraStack <------------- 000effdc g O *ABS* 00000018 Call16Data 000f0000 g *ABS* 00000000 final_readonly_start 000f0000 g *ABS* 00000000 zonefseg_start 000f00f6 g F .text 0000038b dopost 000f0481 g F .text 000001c2 handle_pmm 000f0644 l O .text 00000014 CSWTCH.1353 000f0658 l O .text 00000014 __func__.14607 000f066c l O .text 00000011 __func__.14624 000f0680 l O .text 00000010 __func__.14549 000f0690 l O .text 0000000b __func__.14497 What's supposed to stop that happening? I'd chosen a debug level of 4 since that was the largest it would go without the build complaining it wouldn't fit, so I thought I was safe since something did complain if it got way too big. (This is based off 1.9.1) Dave -- Dr. David Alan Gilbert / dgilbert(a)redhat.com / Manchester, UK

5 39

[PATCH] block: add NVMe boot support
by Julian Stecklina 20 Feb '17

20 Feb '17

This patch enables SeaBIOS to boot from NVMe. Finding namespaces and basic I/O works. Testing has been done in qemu and so far it works with Grub, syslinux, and the FreeBSD loader. You need a recent Qemu (>= October 2016), because older versions have buggy NVMe support. Signed-off-by: Julian Stecklina <jsteckli(a)amazon.com> --- Makefile | 2 +- src/Kconfig | 6 + src/block.c | 4 + src/block.h | 1 + src/hw/nvme-int.h | 199 +++++++++++++++++ src/hw/nvme.c | 622 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/hw/nvme.h | 15 ++ src/hw/pci_ids.h | 1 + 8 files changed, 849 insertions(+), 1 deletion(-) create mode 100644 src/hw/nvme-int.h create mode 100644 src/hw/nvme.c create mode 100644 src/hw/nvme.h diff --git a/Makefile b/Makefile index 3b94ee0..946df7e 100644 --- a/Makefile +++ b/Makefile @@ -43,7 +43,7 @@ SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c optionroms.c \ fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c fw/xen.c \ fw/acpi.c fw/mptable.c fw/pirtable.c fw/smbios.c fw/romfile_loader.c \ hw/virtio-ring.c hw/virtio-pci.c hw/virtio-blk.c hw/virtio-scsi.c \ - hw/tpm_drivers.c + hw/tpm_drivers.c hw/nvme.c SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c DIRS=src src/hw src/fw vgasrc diff --git a/src/Kconfig b/src/Kconfig index 457d082..77ec9c7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -227,6 +227,12 @@ menu "Hardware support" help Support floppy images stored in coreboot flash or from QEMU fw_cfg. + config NVME + depends on DRIVES + bool "NVMe controllers" + default y + help + Support for NVMe disk code. config PS2PORT depends on KEYBOARD || MOUSE diff --git a/src/block.c b/src/block.c index f7280cf..d104f6d 100644 --- a/src/block.c +++ b/src/block.c @@ -20,6 +20,7 @@ #include "hw/usb-uas.h" // uas_process_op #include "hw/virtio-blk.h" // process_virtio_blk_op #include "hw/virtio-scsi.h" // virtio_scsi_process_op +#include "hw/nvme.h" // nvme_process_op #include "malloc.h" // malloc_low #include "output.h" // dprintf #include "stacks.h" // call32 @@ -502,6 +503,7 @@ block_setup(void) megasas_setup(); pvscsi_setup(); mpt_scsi_setup(); + nvme_setup(); } // Fallback handler for command requests not implemented by drivers @@ -571,6 +573,8 @@ process_op_32(struct disk_op_s *op) return virtio_scsi_process_op(op); case DTYPE_PVSCSI: return pvscsi_process_op(op); + case DTYPE_NVME: + return nvme_process_op(op); default: return process_op_both(op); } diff --git a/src/block.h b/src/block.h index 0f15ff9..f03ec38 100644 --- a/src/block.h +++ b/src/block.h @@ -82,6 +82,7 @@ struct drive_s { #define DTYPE_PVSCSI 0x83 #define DTYPE_MPT_SCSI 0x84 #define DTYPE_SDCARD 0x90 +#define DTYPE_NVME 0x91 #define MAXDESCSIZE 80 diff --git a/src/hw/nvme-int.h b/src/hw/nvme-int.h new file mode 100644 index 0000000..873ee71 --- /dev/null +++ b/src/hw/nvme-int.h @@ -0,0 +1,199 @@ +// NVMe datastructures and constants +// +// Copyright 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +#ifndef __NVME_INT_H +#define __NVME_INT_H + +#include "types.h" // u32 +#include "pcidevice.h" // struct pci_device + +/* Data structures */ + +/* The register file of a NVMe host controller. This struct follows the naming + scheme in the NVMe specification. */ +struct nvme_reg { + u64 cap; /* controller capabilities */ + u32 vs; /* version */ + u32 intms; /* interrupt mask set */ + u32 intmc; /* interrupt mask clear */ + u32 cc; /* controller configuration */ + u32 _res0; + u32 csts; /* controller status */ + u32 _res1; + u32 aqa; /* admin queue attributes */ + u64 asq; /* admin submission queue base address */ + u64 acq; /* admin completion queue base address */ +}; + +/* Submission queue entry */ +struct nvme_sqe { + union { + u32 dword[16]; + struct { + u32 cdw0; /* Command DWORD 0 */ + u32 nsid; /* Namespace ID */ + u64 _res0; + u64 mptr; /* metadata ptr */ + + u64 dptr_prp1; + u64 dptr_prp2; + }; + }; +}; + +/* Completion queue entry */ +struct nvme_cqe { + union { + u32 dword[4]; + struct { + u32 cdw0; + u32 _res0; + u16 sq_head; + u16 sq_id; + u16 cid; + u16 status; + }; + }; +}; + +/* The common part of every submission or completion queue. */ +struct nvme_queue { + u32 volatile *dbl; /* doorbell */ + u16 mask; /* length - 1 */ +}; + +struct nvme_cq { + struct nvme_queue common; + struct nvme_cqe *cqe; + + /* We have read upto (but not including) this entry in the queue. */ + u16 head; + + /* The current phase bit the controller uses to indicate that it has written + a new entry. This is inverted after each wrap. */ + unsigned phase : 1; +}; + +struct nvme_sq { + struct nvme_queue common; + struct nvme_sqe *sqe; + + /* Corresponding completion queue. We only support a single SQ per CQ. */ + struct nvme_cq *cq; + + /* The last entry the controller has fetched. */ + u16 head; + + /* The last value we have written to the tail doorbell. */ + u16 tail; +}; + +struct nvme_ctrl { + struct pci_device *pci; + struct nvme_reg volatile *reg; + + u32 doorbell_stride; /* in bytes */ + + struct nvme_sq admin_sq; + struct nvme_cq admin_cq; + + u32 ns_count; + struct nvme_namespace *ns; + + struct nvme_sq io_sq; + struct nvme_cq io_cq; +}; + +struct nvme_namespace { + struct drive_s drive; + struct nvme_ctrl *ctrl; + + u32 ns_id; + + u64 lba_count; /* The total amount of sectors. */ + + u32 block_size; + u32 metadata_size; + + /* Page aligned buffer of size NVME_PAGE_SIZE. */ + char *dma_buffer; +}; + +/* Data structures for NVMe admin identify commands */ + +struct nvme_identify_ctrl { + u16 vid; + u16 ssvid; + char sn[20]; + char mn[40]; + char fr[8]; + + char _boring[516 - 72]; + + u32 nn; /* number of namespaces */ +}; + +struct nvme_identify_ns_list { + u32 ns_id[1024]; +}; + +struct nvme_lba_format { + u16 ms; + u8 lbads; + u8 rp; + u8 res; +}; + +struct nvme_identify_ns { + u64 nsze; + u64 ncap; + u64 nuse; + u8 nsfeat; + u8 nlbaf; + u8 flbas; + + char _boring[128 - 27]; + + struct nvme_lba_format lbaf[16]; +}; + +union nvme_identify { + struct nvme_identify_ns ns; + struct nvme_identify_ctrl ctrl; + struct nvme_identify_ns_list ns_list; +}; + +/* NVMe constants */ + +#define NVME_CAP_CSS_NVME (1ULL << 37) + +#define NVME_CSTS_FATAL (1U << 1) +#define NVME_CSTS_RDY (1U << 0) + +#define NVME_CC_EN (1U << 0) + +#define NVME_SQE_OPC_ADMIN_CREATE_IO_SQ 1U +#define NVME_SQE_OPC_ADMIN_CREATE_IO_CQ 5U +#define NVME_SQE_OPC_ADMIN_IDENTIFY 6U + +#define NVME_SQE_OPC_IO_WRITE 1U +#define NVME_SQE_OPC_IO_READ 2U + +#define NVME_ADMIN_IDENTIFY_CNS_ID_NS 0U +#define NVME_ADMIN_IDENTIFY_CNS_ID_CTRL 1U +#define NVME_ADMIN_IDENTIFY_CNS_GET_NS_LIST 2U + +#define NVME_CQE_DW3_P (1U << 16) + +#define NVME_PAGE_SIZE 4096 + +/* Length for the queue entries. */ +#define NVME_SQE_SIZE_LOG 6 +#define NVME_CQE_SIZE_LOG 4 +_Static_assert(sizeof(struct nvme_sqe) == 1U << NVME_SQE_SIZE_LOG, "invalid queue entry size"); +_Static_assert(sizeof(struct nvme_cqe) == 1U << NVME_CQE_SIZE_LOG, "invalid queue entry size"); + +#endif + +/* EOF */ diff --git a/src/hw/nvme.c b/src/hw/nvme.c new file mode 100644 index 0000000..1266d7f --- /dev/null +++ b/src/hw/nvme.c @@ -0,0 +1,622 @@ +// Low level NVMe disk access +// +// Copyright 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +#include "blockcmd.h" +#include "malloc.h" // malloc_fseq +#include "string.h" // memset +#include "output.h" // dprintf +#include "pci.h" +#include "pcidevice.h" // foreachpci +#include "pci_ids.h" // PCI_CLASS_STORAGE_NVME +#include "pci_regs.h" // PCI_BASE_ADDRESS_0 +#include "util.h" // boot_add_hd +#include "std/disk.h" // DISK_RET_ +#include "util.h" // timer_calc +#include "x86.h" // cpu_relax + +#include "nvme.h" +#include "nvme-int.h" + +/* Sequentially consistent read. */ +static u32 nvme_seq_read(u32 *p) { return *(_Atomic u32 *)p; } + +/* Sequentially consistent writes. We have a volatile version for doorbell registers. */ +static void nvme_seq_writev(u32 volatile *p, u32 v) { *(_Atomic volatile u32 *)p = v; } + +static void * +zalloc_page_aligned_high(u32 size) +{ + void *res = memalign_high(NVME_PAGE_SIZE, size); + if (res) memset(res, 0, size); + return res; +} + +static void +nvme_init_queue_common(struct nvme_ctrl *ctrl, struct nvme_queue *q, u16 q_idx, u16 length) +{ + memset(q, 0, sizeof(*q)); + q->dbl = (u32 volatile *)((char *)ctrl->reg + 0x1000 + q_idx * ctrl->doorbell_stride); + dprintf(3, " q %p q_idx %u dbl %p\n", q, q_idx, q->dbl); + q->mask = length - 1; +} + +static void +nvme_init_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, u16 length, + struct nvme_cq *cq) +{ + nvme_init_queue_common(ctrl, &sq->common, q_idx, length); + sq->sqe = zalloc_page_aligned_high(sizeof(*sq->sqe) * length); + dprintf(3, "sq %p q_idx %u sqe %p\n", sq, q_idx, sq->sqe); + sq->cq = cq; + sq->head = 0; + sq->tail = 0; +} + +static void +nvme_init_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx, u16 length) +{ + nvme_init_queue_common(ctrl, &cq->common, q_idx, length); + cq->cqe = zalloc_page_aligned_high(sizeof(*cq->cqe) * length); + + cq->head = 0; + + /* All CQE phase bits are initialized to zero. This means initially we wait + for the host controller to set these to 1. */ + cq->phase = 1; +} + +static int +nvme_poll_cq(struct nvme_cq *cq) +{ + u32 dw3 = nvme_seq_read(&cq->cqe[cq->head].dword[3]); + return (!!(dw3 & NVME_CQE_DW3_P) == cq->phase); +} + +static int +nvme_is_cqe_success(struct nvme_cqe const *cqe) +{ + return (cqe->status & 0xFF) >> 1 == 0; +} + +static struct nvme_cqe +nvme_consume_cqe(struct nvme_sq *sq) +{ + struct nvme_cq *cq = sq->cq; + + if (!nvme_poll_cq(cq)) { + panic("nvme: can't consume cqe when not ready!\n"); + } + + struct nvme_cqe *cqe = &cq->cqe[cq->head]; + u16 cq_next_head = (cq->head + 1) & cq->common.mask; + dprintf(4, "cq %p head %u -> %u\n", cq, cq->head, cq_next_head); + if (cq_next_head < cq->head) { + dprintf(3, "cq %p wrap\n", cq); + cq->phase = ~cq->phase; + } + cq->head = cq_next_head; + + /* Update the submission queue head. */ + if (cqe->sq_head != sq->head) { + sq->head = cqe->sq_head; + dprintf(4, "sq %p advanced to %u\n", sq, cqe->sq_head); + } + + /* Tell the controller that we consumed the completion. */ + nvme_seq_writev(cq->common.dbl, cq->head); + + return *cqe; +} + +static struct nvme_cqe +nvme_timeout_cqe(void) +{ + struct nvme_cqe r; + + /* 0xFF is a vendor specific status code != success. Should be okay for + indicating failure. */ + memset(&r, 0xFF, sizeof(r)); + return r; +} + +static struct nvme_cqe +nvme_wait(struct nvme_sq *sq) +{ + static const unsigned nvme_timeout = 500 /* ms */; + u32 to = timer_calc(nvme_timeout); + while (!nvme_poll_cq(sq->cq)) { + cpu_relax(); + + if (timer_check(to)) { + warn_timeout(); + return nvme_timeout_cqe(); + } + } + + return nvme_consume_cqe(sq); +} + +/* Returns the next submission queue entry (or NULL if the queue is full). It + also fills out Command Dword 0 and clears the rest. */ +static struct nvme_sqe * +nvme_get_next_sqe(struct nvme_sq *sq, u8 opc, void *metadata, void *data) +{ + if (((sq->head + 1) & sq->common.mask) == sq->tail) { + dprintf(3, "submission queue is full"); + return NULL; + } + + struct nvme_sqe *sqe = &sq->sqe[sq->tail]; + dprintf(4, "sq %p next_sqe %u\n", sq, sq->tail); + + memset(sqe, 0, sizeof(*sqe)); + sqe->cdw0 = opc | (sq->tail << 16 /* CID */); + sqe->mptr = (u32)metadata; + sqe->dptr_prp1 = (u32)data; + + if (sqe->dptr_prp1 & (NVME_PAGE_SIZE - 1)) { + panic("data buffer not page aligned: %p\n", data); + } + + return sqe; +} + +/* Call this after you've filled out an sqe that you've got from nvme_get_next_sqe. */ +static void +nvme_commit_sqe(struct nvme_sq *sq) +{ + dprintf(4, "sq %p commit_sqe %u\n", sq, sq->tail); + sq->tail = (sq->tail + 1) & sq->common.mask; + nvme_seq_writev(sq->common.dbl, sq->tail); +} + +/* The caller needs to free the returned pointer, because this is the 80s and we + can't use unique_ptr. */ +static union nvme_identify * +nvme_admin_identify(struct nvme_ctrl *ctrl, u8 cns, u32 nsid) +{ + union nvme_identify *identify_buf = zalloc_page_aligned_high(4096); + if (!identify_buf) { + panic("NVMe couldn't allocate identify buffer"); + } + + struct nvme_sqe *cmd_identify = nvme_get_next_sqe(&ctrl->admin_sq, NVME_SQE_OPC_ADMIN_IDENTIFY, + NULL, identify_buf); + if (!cmd_identify) { panic("admin queue full\n"); } + + cmd_identify->nsid = nsid; + cmd_identify->dword[10] = cns; + + nvme_commit_sqe(&ctrl->admin_sq); + + struct nvme_cqe cqe = nvme_wait(&ctrl->admin_sq); + + if (!nvme_is_cqe_success(&cqe)) { + free(identify_buf); + return NULL; + } + + return identify_buf; +} + +static struct nvme_identify_ctrl * +nvme_admin_identify_ctrl(struct nvme_ctrl *ctrl) +{ + union nvme_identify *identify_buf = nvme_admin_identify(ctrl, NVME_ADMIN_IDENTIFY_CNS_ID_CTRL, 0); + /* C question: Is it safe to skip the nullptr check here? */ + return identify_buf ? &identify_buf->ctrl : NULL; +} + +static struct nvme_identify_ns_list * +nvme_admin_identify_get_ns_list(struct nvme_ctrl *ctrl) +{ + union nvme_identify *identify_buf = nvme_admin_identify(ctrl, NVME_ADMIN_IDENTIFY_CNS_GET_NS_LIST, 0); + return identify_buf ? &identify_buf->ns_list : NULL; +} + +static struct nvme_identify_ns * +nvme_admin_identify_ns(struct nvme_ctrl *ctrl, u32 ns_id) +{ + union nvme_identify *identify_buf = nvme_admin_identify(ctrl, NVME_ADMIN_IDENTIFY_CNS_ID_NS, ns_id); + return identify_buf ? &identify_buf->ns : NULL; +} + +static void +nvme_probe_ns(struct nvme_ctrl *ctrl, struct nvme_namespace *ns, u32 ns_id) +{ + ns->ctrl = ctrl; + ns->ns_id = ns_id; + + struct nvme_identify_ns *id = nvme_admin_identify_ns(ctrl, ns_id); + if (!id) { + dprintf(2, "NVMe couldn't identify namespace %u.\n", ns_id); + goto free_buffer; + } + + u8 current_lba_format = id->flbas & 0xF; + if (current_lba_format > id->nlbaf) { + dprintf(2, "NVMe NS %u: current LBA format %u is beyond what the namespace supports (%u)?\n", + ns_id, current_lba_format, id->nlbaf + 1); + goto free_buffer; + } + + ns->lba_count = id->nsze; + + struct nvme_lba_format *fmt = &id->lbaf[current_lba_format]; + + ns->block_size = 1U << fmt->lbads; + ns->metadata_size = fmt->ms; + + if (ns->block_size > NVME_PAGE_SIZE) { + panic("Cannot DMA a single block from our buffer: %u vs %u", ns->block_size, NVME_PAGE_SIZE); + } + + ns->drive.cntl_id = ns - ctrl->ns; + ns->drive.removable = 0; + ns->drive.type = DTYPE_NVME; + ns->drive.blksize = ns->block_size; + ns->drive.sectors = ns->lba_count; + + ns->dma_buffer = zalloc_page_aligned_high(NVME_PAGE_SIZE); + + char *desc = znprintf(MAXDESCSIZE, "NVMe NS %u: %llu MiB (%llu %u-byte blocks + %u-byte metadata)\n", + ns_id, (ns->lba_count * ns->block_size) >> 20, ns->lba_count, ns->block_size, + ns->metadata_size); + + dprintf(3, "%s", desc); + boot_add_hd(&ns->drive, desc, bootprio_find_pci_device(ctrl->pci)); + + free_buffer: + free (id); + } + +/* Returns 0 on success. */ +static int +nvme_create_io_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx) +{ + nvme_init_cq(ctrl, cq, q_idx, NVME_PAGE_SIZE / sizeof(struct nvme_cqe)); + struct nvme_sqe *cmd_create_cq = nvme_get_next_sqe(&ctrl->admin_sq, NVME_SQE_OPC_ADMIN_CREATE_IO_CQ, + NULL, cq->cqe); + if (!cmd_create_cq) { + return -1; + } + + cmd_create_cq->dword[10] = (cq->common.mask << 16) | (q_idx >> 1); + cmd_create_cq->dword[11] = 1 /* physically contiguous */; + + nvme_commit_sqe(&ctrl->admin_sq); + + struct nvme_cqe cqe = nvme_wait(&ctrl->admin_sq); + + if (!nvme_is_cqe_success(&cqe)) { + dprintf(2, "create io cq failed: %08x %08x %08x %08x\n", + cqe.dword[0], cqe.dword[1], cqe.dword[2], cqe.dword[3]); + + return -1; + } + + return 0; +} + +/* Returns 0 on success. */ +static int +nvme_create_io_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, struct nvme_cq *cq) +{ + nvme_init_sq(ctrl, sq, q_idx, NVME_PAGE_SIZE / sizeof(struct nvme_cqe), cq); + struct nvme_sqe *cmd_create_sq = nvme_get_next_sqe(&ctrl->admin_sq, NVME_SQE_OPC_ADMIN_CREATE_IO_SQ, + NULL, sq->sqe); + if (!cmd_create_sq) { + return -1; + } + + cmd_create_sq->dword[10] = (sq->common.mask << 16) | (q_idx >> 1); + cmd_create_sq->dword[11] = (q_idx >> 1) << 16 | 1 /* physically contiguous */; + dprintf(3, "sq %p create dword10 %08x dword11 %08x\n", sq, cmd_create_sq->dword[10], cmd_create_sq->dword[11]); + + nvme_commit_sqe(&ctrl->admin_sq); + + struct nvme_cqe cqe = nvme_wait(&ctrl->admin_sq); + + if (!nvme_is_cqe_success(&cqe)) { + dprintf(2, "create io sq failed: %08x %08x %08x %08x\n", + cqe.dword[0], cqe.dword[1], cqe.dword[2], cqe.dword[3]); + return -1; + } + + return 0; +} + +/* Reads count sectors into buf. Returns DISK_RET_*. The buffer cannot cross + page boundaries. */ +static int +nvme_io_readwrite(struct nvme_namespace *ns, u64 lba, char *buf, u16 count, int write) +{ + if ((u32)buf & 0x3) panic("buf %p is not DWORD aligned", buf); + + if (((u32)buf & ~(NVME_PAGE_SIZE - 1)) + != (((u32)buf + ns->block_size * count - 1) & ~(NVME_PAGE_SIZE - 1))) { + panic("IO read crosses page boundary: buf %p bs %u count %u", buf, ns->block_size, count); + } + + struct nvme_sqe *io_read = nvme_get_next_sqe(&ns->ctrl->io_sq, + write ? NVME_SQE_OPC_IO_WRITE : NVME_SQE_OPC_IO_READ, + NULL, buf); + io_read->nsid = ns->ns_id; + io_read->dword[10] = (u32)lba; + io_read->dword[11] = (u32)(lba >> 32); + io_read->dword[12] = (1U << 31 /* limited retry */) | (count - 1); + + nvme_commit_sqe(&ns->ctrl->io_sq); + + struct nvme_cqe cqe = nvme_wait(&ns->ctrl->io_sq); + + if (!nvme_is_cqe_success(&cqe)) { + dprintf(2, "read io: %08x %08x %08x %08x\n", + cqe.dword[0], cqe.dword[1], cqe.dword[2], cqe.dword[3]); + + return DISK_RET_EBADTRACK; + } + + return DISK_RET_SUCCESS; +} + + +static int +nvme_create_io_queues(struct nvme_ctrl *ctrl) +{ + if (nvme_create_io_cq(ctrl, &ctrl->io_cq, 3)) + return -1; + + if (nvme_create_io_sq(ctrl, &ctrl->io_sq, 2, &ctrl->io_cq)) + return -1; + + return 0; +} + +/* Waits for CSTS.RDY to match rdy. Returns 0 on success. */ +static int +nvme_wait_csts_rdy(struct nvme_ctrl *ctrl, unsigned rdy) +{ + u32 const max_to = 500 /* ms */ * ((ctrl->reg->cap >> 24) & 0xFFU); + u32 to = timer_calc(max_to); + u32 csts; + + while (rdy != ((csts = ctrl->reg->csts) & NVME_CSTS_RDY)) { + cpu_relax(); + + if (csts & NVME_CSTS_FATAL) { + dprintf(3, "NVMe fatal error during controller shutdown\n"); + return -1; + } + + if (timer_check(to)) { + warn_timeout(); + return -1; + } + } + + return 0; +} + +static void +nvme_controller_init(struct nvme_ctrl *ctrl) +{ + pci_enable_busmaster(ctrl->pci); + + /* Turn the controller off. */ + ctrl->reg->cc = 0; + if (nvme_wait_csts_rdy(ctrl, 0)) { + dprintf(2, "NVMe fatal error during controller shutdown\n"); + return; + } + + ctrl->doorbell_stride = 4U << ((ctrl->reg->cap >> 32) & 0xF); + + nvme_init_cq(ctrl, &ctrl->admin_cq, 1, NVME_PAGE_SIZE / sizeof(struct nvme_cqe)); + nvme_init_sq(ctrl, &ctrl->admin_sq, 0, NVME_PAGE_SIZE / sizeof(struct nvme_sqe), &ctrl->admin_cq); + + ctrl->reg->aqa = ctrl->admin_cq.common.mask << 16 | ctrl->admin_sq.common.mask; + + /* Create the admin queue pair */ + if (!ctrl->admin_sq.sqe || !ctrl->admin_cq.cqe) goto out_of_memory; + + ctrl->reg->asq = (u32)ctrl->admin_sq.sqe; + ctrl->reg->acq = (u32)ctrl->admin_cq.cqe; + + dprintf(3, " admin submission queue: %p\n", ctrl->admin_sq.sqe); + dprintf(3, " admin completion queue: %p\n", ctrl->admin_cq.cqe); + + ctrl->reg->cc = NVME_CC_EN | (NVME_CQE_SIZE_LOG << 20) | (NVME_SQE_SIZE_LOG << 16 /* IOSQES */); + if (nvme_wait_csts_rdy(ctrl, 1)) { + dprintf(2, "NVMe fatal error while enabling controller\n"); + return; + } + /* The admin queue is set up and the controller is ready. Let's figure out + what namespaces we have. */ + + struct nvme_identify_ctrl *identify = nvme_admin_identify_ctrl(ctrl); + + if (!identify) { + dprintf(2, "NVMe couldn't identify controller.\n"); + goto failed; + } + + /* TODO Print model/serial info. */ + dprintf(3, "NVMe has %u namespace%s.\n", + identify->nn, (identify->nn == 1) ? "" : "s"); + + ctrl->ns_count = identify->nn; + free(identify); + + if ((ctrl->ns_count == 0) || nvme_create_io_queues(ctrl)) { + /* No point to continue, if the controller says it doesn't have + namespaces or we couldn't create I/O queues. */ + goto failed; + } + + ctrl->ns = malloc_fseg(sizeof(*ctrl->ns) * ctrl->ns_count); + if (!ctrl->ns) goto out_of_memory; + memset(ctrl->ns, 0, sizeof(*ctrl->ns) * ctrl->ns_count); + + struct nvme_identify_ns_list *ns_list = nvme_admin_identify_get_ns_list(ctrl); + if (!ns_list) { + dprintf(2, "NVMe couldn't get namespace list.\n"); + goto failed; + } + + /* Populate namespace IDs */ + int ns_idx; + for (ns_idx = 0; + ns_idx < ARRAY_SIZE(ns_list->ns_id) + && ns_idx < ctrl->ns_count + && ns_list->ns_id[ns_idx]; + ns_idx++) { + nvme_probe_ns(ctrl, &ctrl->ns[ns_idx], ns_list->ns_id[ns_idx]); + } + + free(ns_list); + + /* If for some reason the namespace list gives us fewer namespaces, we just go along. */ + if (ns_idx != ctrl->ns_count) { + dprintf(2, "NVMe namespace list has only %u namespaces?\n", ns_idx); + ctrl->ns_count = ns_idx; + } + + dprintf(3, "NVMe initialization complete!\n"); + return; + + out_of_memory: + warn_noalloc(); + failed: + free(ctrl->admin_sq.sqe); + free(ctrl->admin_cq.cqe); + return; +} + +/* Initialize an NVMe controller and detect its drives. */ +static void +nvme_controller_setup(struct pci_device *pci) +{ + if (create_bounce_buf() < 0) + return; + + struct nvme_reg volatile *reg = pci_enable_membar(pci, PCI_BASE_ADDRESS_0); + if (!reg) + return; + + u32 version = reg->vs; + dprintf(3, "Found NVMe controller with version %u.%u.%u.\n", + version >> 16, (version >> 8) & 0xFF, version & 0xFF); + dprintf(3, " Capabilities %016llx\n", reg->cap); + + if (version < 0x00010100U) { + dprintf(3, "Need at least 1.1.0! Skipping.\n"); + return; + } + + if (~reg->cap & NVME_CAP_CSS_NVME) { + dprintf(3, "Controller doesn't speak NVMe command set. Skipping.\n"); + return; + } + + struct nvme_ctrl *ctrl = malloc_fseg(sizeof(*ctrl)); + if (!ctrl) { + warn_noalloc(); + return; + } + + memset(ctrl, 0, sizeof(*ctrl)); + + ctrl->reg = reg; + ctrl->pci = pci; + + nvme_controller_init(ctrl); +} + +// Locate and init NVMe controllers +static void +nvme_scan(void) +{ + // Scan PCI bus for ATA adapters + struct pci_device *pci; + + foreachpci(pci) { + if (pci->class != PCI_CLASS_STORAGE_NVME) + continue; + if (pci->prog_if != 2 /* as of NVM 1.0e */) { + dprintf(3, "Found incompatble NVMe: prog-if=%02x\n", pci->prog_if); + continue; + } + + nvme_controller_setup(pci); + } +} + +static int +nvme_cmd_readwrite(struct nvme_namespace *ns, struct disk_op_s *op, int write) +{ + int res = DISK_RET_SUCCESS; + u16 const max_blocks = NVME_PAGE_SIZE / ns->block_size; + + if (write) { + panic("XXX Writes are implemented, but not tested." + " Remove this panic, if you are sure what you are doing!"); + } + + for (u16 i = 0; i < op->count || res != DISK_RET_SUCCESS;) { + u16 const blocks_remaining = op->count - i; + u16 const blocks = blocks_remaining < max_blocks ? blocks_remaining : max_blocks; + char * const op_buf = op->buf_fl + i * ns->block_size; + + if (write) { + memcpy(ns->dma_buffer, op_buf, blocks * ns->block_size); + } + + res = nvme_io_readwrite(ns, op->lba + i, ns->dma_buffer, blocks, write); + dprintf(3, "ns %u %s lba %llu+%u: %d\n", ns->ns_id, write ? "write" : "read", + op->lba + i, blocks, res); + + if (!write && res == DISK_RET_SUCCESS) { + memcpy(op_buf, ns->dma_buffer, blocks * ns->block_size); + } + + i += blocks; + } + + return res; +} + +int +nvme_process_op(struct disk_op_s *op) +{ + if (!CONFIG_NVME) + return DISK_RET_SUCCESS; + + struct nvme_namespace *ns = container_of(op->drive_gf, struct nvme_namespace, drive); + + switch (op->command) { + case CMD_READ: + case CMD_WRITE: + return nvme_cmd_readwrite(ns, op, op->command == CMD_WRITE); + default: + dprintf(2, "NVMe disk op %u not implemented\n", op->command); + return DISK_RET_EBADTRACK; + } +} + +void +nvme_setup(void) +{ + ASSERT32FLAT(); + if (!CONFIG_NVME) + return; + + dprintf(3, "init nvme\n"); + nvme_scan(); +} + +/* Local Variables: */ +/* indent-tabs-mode: nil */ +/* c-basic-offset: 4 */ +/* End: */ diff --git a/src/hw/nvme.h b/src/hw/nvme.h new file mode 100644 index 0000000..1555dc7 --- /dev/null +++ b/src/hw/nvme.h @@ -0,0 +1,15 @@ +// External interfaces for low level NVMe support +// +// Copyright 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +#ifndef __NVME_H +#define __NVME_H + +#include "block.h" // struct disk_op_s + +void nvme_setup(void); +int nvme_process_op(struct disk_op_s *op); + +#endif + +/* EOF */ diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index cdf9b3c..4ac73b4 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -18,6 +18,7 @@ #define PCI_CLASS_STORAGE_SATA 0x0106 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 #define PCI_CLASS_STORAGE_SAS 0x0107 +#define PCI_CLASS_STORAGE_NVME 0x0108 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 -- 2.7.4

4 8

coreboot and `Timeout at i8042_flush:71!`
by Paul Menzel 11 Feb '17

11 Feb '17

Dear SeaBIOS folks, coreboots board status repository has some SeaBIOS warnings, and I believe the keyboard doesn’t work in that case. ``` $ git grep 'Timeout at i8042_flush' origin/master -- origin/master:amd/lamar/4.0-9540-gae5ab60/2015-04-30T02:12:19Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:amd/olivehill/4.0-7005-gb9a0809/2014-10-08T13:44:17Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:amd/olivehillplus/4.0-6942-g4177db5/2014-09-19T19:38:48Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:gizmosphere/gizmo/4.0-9564-g58649b0/2015-05-03T07:14:33Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:google/panther/4.0-9491-g64c7791/2015-04-23T21:31:14Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:google/panther/4.1-340-gb38b0f2/2015-08-25T18:38:10Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/coreboot_console.txt:|7f6bc000| WARNING - Timeout at i8042_flush:71! origin/master:hp/2760p/4.5-906-g3fb6e6e-dirty/2017-01-27T03_04_14Z/coreboot_console.txt:|7feca000| WARNING - Timeout at i8042_flush:71! origin/master:hp/2760p/4.5-911-g9510156/2017-01-28T14_47_33Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:hp/2760p/4.5-913-g0f70fbd/2017-01-29T02_16_08Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/coreboot_console.txt:|7ba9a000| WARNING - Timeout at i8042_flush:71! origin/master:intel/minnowmax/4.2-429-g4013469/2015-11-30T20_21_41Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:intel/minnowmax/4.2-429-g4013469/2015-11-30T20_21_41Z/tests/cbmem-console.log:WARNING - Timeout at i8042_flush:71! origin/master:intel/minnowmax/4.5-306-g00ad7ff/2016-11-17T17_00_43Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:intel/minnowmax/4.5-306-g00ad7ff/2016-11-17T17_00_43Z/tests/cbmem-console.log:WARNING - Timeout at i8042_flush:71! origin/master:pcengines/alix2d/4.0-6723-ga0a3727-dirty/2014-08-15T23:01:34Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:pcengines/alix2d/4.0-6723-ga0a3727/2014-08-15T01:44:46Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:pcengines/apu1/4.4-422-g9aba60e/2016-06-05T08_06_37Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:pcengines/apu2/4.5-801-gfeb4ef6/2017-01-11T16_15_42Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! origin/master:siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/coreboot_console.txt:WARNING - Timeout at i8042_flush:71! ``` I also experience this sometimes on a Lenovo X60, when I load the SeaBIOS ELF file from GRUB with the commands below. ``` > chainloader (cbfsdisk)/img/seabios > boot ``` Every time, the keyboard doesn’t work – on the Lenovo X60 it’s connected over the PS/2 port – the error message `Timeout at i8042_flush:71!` can be seen. Note, that it’s unlikely to be a timing issue, as the keyboard works in the GRUB payload *before*. Any idea, what causes the problem, and is there a way to fix it? Thanks, Paul

2 6

Boot menu key does not work with config options threads set to 2
by Paul Menzel 01 Feb '17

01 Feb '17

Dear SeaBIOS folks, On the ASRock E350M1 with coreboot and SeaBIOS, setting the runtime config option `threads` to 2, I am unable to press the boot menu key (ESC). [1] > By default, SeaBIOS will parallelize hardware initialization during bootup to reduce boot time. Multiple hardware devices can be initialized in parallel between vga initialization and option rom initialization. One can set this file to a value of zero to force hardware initialization to run serially. Alternatively, one can set this file to 2 to enable early hardware initialization that runs in parallel with vga, option rom initialization, and the boot menu. My rotating hard drive is pretty slow, and SeaBIOS is waiting for that. Not adding `etc/threads` to CBFS, pressing the key works, and the boot menu is displayed. Is that the expected behavior? Kind regards, Paul [1] https://www.seabios.org/Runtime_config

3 3

[PATCH 1/2] fw/acpi: Build MADT the way commodity BIOSes do
by Filippo Sironi 01 Feb '17

01 Feb '17

When running Linux on an Intel machine with a commodity BIOS, CPUs are numbered starting from 0 and the first half refers to the first logical CPU on each core while the second half refers to the second logical CPU on each core. As an example, on machine with 2 sockets, 4 cores per socket, and 2 logical CPUs per core, CPUs would be numbered: * 0 1 2 3 - first logical CPU on each core of socket 0 * 4 5 6 7 - first logical CPU on each core of socket 1 * 8 9 10 11 - second logical CPU on each core of socket 0 * 12 13 14 15 - second logical CPU on each core of socket 1 With seabios (prior to this patch), CPU 0 would be the first logical CPU on core 0 of socket 0, CPU 1 would be the second logical CPU on core 0 of socket 0, and so on. This is due to the fact that processor_id and local_apic_id are assigned with the same value when building MADT. Exhaust the most-significant 7 bits of the 8-bit APIC ID and then come back to the least-significant bit when assigning local_apic_id, since the least-significant bit identifies the second logical CPU on a core. If HTT isn't available, keep the previous behavior. Signed-off-by: Filippo Sironi <sironi(a)amazon.de> --- src/fw/acpi.c | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/src/fw/acpi.c b/src/fw/acpi.c index 8bc2ca6..864c247 100644 --- a/src/fw/acpi.c +++ b/src/fw/acpi.c @@ -158,13 +158,53 @@ build_madt(void) memset(madt, 0, madt_size); madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR); madt->flags = cpu_to_le32(1); + u32 eax, ebx, ecx, edx; + cpuid(1, &eax, &ebx, &ecx, &edx); + int htt = 0; + if (!eax) { + dprintf(1, "No cpuid\n"); + } else { + htt = !!(edx & (1 << 28)); + /* assuming at most 2 logical CPUs per core */ + if (htt) + dprintf(4, "Found HTT feature\n"); + } struct madt_processor_apic *apic = (void*)&madt[1]; int i; for (i=0; i<MaxCountCPUs; i++) { apic->type = APIC_PROCESSOR; apic->length = sizeof(*apic); apic->processor_id = i; - apic->local_apic_id = i; + if (htt) { + /* + * In a system with 2 packages, 4 cores per package, and 2 CPUs per + * core we want to achieve the following coupling: + * CPU# APIC ID + * 0 0 [first socket, first logical CPUs] + * 1 2 + * 2 4 + * 3 6 + * 4 8 [second socket, first logical CPUs] + * 5 10 + * 6 12 + * 7 14 + * 8 1 [first socket, second logical CPUs] + * 9 3 + * 10 5 + * 11 7 + * 12 9 [second socket, second logical CPUs] + * 13 11 + * 14 13 + * 15 15 + * where the least-significant bit of the APIC ID identifies the + * first (0) or second (1) logical CPU in a core. + */ + apic->local_apic_id = i * 2; + if (apic->local_apic_id >= MaxCountCPUs) + apic->local_apic_id -= MaxCountCPUs - 1; + } else { + apic->local_apic_id = i; + } if (apic_id_is_present(apic->local_apic_id)) apic->flags = cpu_to_le32(1); else -- 2.7.4

5 11

Dealing with fallback and normal coreboot images
by Paul Menzel 29 Jan '17

29 Jan '17

Dear SeaBIOS folks, coreboot allows to prefix images to add different romstage, ramstage, and payloads, and depending on the behavior during boot, choose a certain one. Commonly *normal* and *fallback* are used as prefixes, while the bootblock code loads the *normal* image first, but if there is a failure, commonly after three tries, boots the fallback image. SeaBIOS takes runtime configuration values always from `etc/`. That way, only one configuration can be used for different coreboot builds. What could be a solution for that problem? Also allow `fallback/etc/`, and `normal/etc`? Kind regards, Paul

2 1

[PATCH] vgasrc: Increase debug level
by Paul Menzel 29 Jan '17

29 Jan '17

Date: Fri, 20 Jan 2017 16:52:44 +0100 You only want this information for debugging. As it also slows down the boot considerably, as, for example, for every character of the GRUB menu, something is sent over the serial console. Therefore, increase the debugging level to 9. Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- vgasrc/vgabios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vgasrc/vgabios.h b/vgasrc/vgabios.h index 3d5bbfe..e2edec0 100644 --- a/vgasrc/vgabios.h +++ b/vgasrc/vgabios.h @@ -73,7 +73,7 @@ static inline int vga_emulate_text(void) { // Debug settings #define DEBUG_VGA_POST 1 -#define DEBUG_VGA_10 3 +#define DEBUG_VGA_10 9 // vgabios.c int vga_bpp(struct vgamode_s *vmode_g); -- 2.7.4

2 1

[PATCH v2 0/2] QEMU: Add capability to write back fw_cfg address to QEMU
by ben＠skyportsystems.com 27 Jan '17

27 Jan '17

From: Ben Warren <ben(a)skyportsystems.com> This patch set adds the capability to write to QEMU across the DMA link and adds a higher-level command to allocate a fw_cfg file and write its address back to another, writeable fw_cfg file. The initial use case is for Windows VM Generation ID, where QEMU needs to change the contents of fw_cfg data at runtime, while still having BIOS allocate and manage the memory. v1->v2: separated patch into two functional units changed so writes only occur over the DMA interface fixed coding style removed change to romfile struct definition (removed new write_back method) Ben Warren (2): QEMU DMA: Add DMA write capability QEMU fw_cfg: Add command to write back address of file src/fw/paravirt.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ src/fw/paravirt.h | 3 +++ src/fw/romfile_loader.c | 38 ++++++++++++++++++++++++++++++++++++++ src/fw/romfile_loader.h | 23 ++++++++++++++++++++--- 4 files changed, 110 insertions(+), 3 deletions(-) -- 2.7.4

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Re: [SeaBIOS] [PATCH] QEMU DMA: Add ability to write back to fw_cfg file
by Kevin O'Connor 23 Jan '17

23 Jan '17

On Thu, Jan 19, 2017 at 10:20:50PM -0800, ben(a)skyportsystems.com wrote: > From: Ben Warren <ben(a)skyportsystems.com> > > This adds a new command to the DMA protocol. The command allows the > memory allocation of a fw_cfg file by BIOS and subsequent return of > the allocated address to QEMU. The initial use case is for Windows VM > Generation ID, where QEMU needs to change the contents of fw_cfg > data at runtime, while still having BIOS allocate and manage the memory. Thanks - see my comments below. [...] > --- a/src/fw/paravirt.c > +++ b/src/fw/paravirt.c > @@ -253,6 +253,20 @@ qemu_cfg_read(void *buf, int len) > } > > static void > +qemu_cfg_write(void *buf, int len) > +{ > + if (len == 0) { > + return; > + } > + > + if (qemu_cfg_dma_enabled()) { > + qemu_cfg_dma_transfer(buf, len, QEMU_CFG_DMA_CTL_WRITE); > + } else { > + outsb(PORT_QEMU_CFG_DATA, buf, len); > + } > +} > + > +static void > qemu_cfg_skip(int len) > { > if (len == 0) { > @@ -280,6 +294,19 @@ qemu_cfg_read_entry(void *buf, int e, int len) > } > } > > +static void > +qemu_cfg_write_entry(void *buf, int e, int len) > +{ > + if (qemu_cfg_dma_enabled()) { > + u32 control = (e << 16) | QEMU_CFG_DMA_CTL_SELECT > + | QEMU_CFG_DMA_CTL_WRITE; > + qemu_cfg_dma_transfer(buf, len, control); > + } else { > + qemu_cfg_select(e); > + qemu_cfg_write(buf, len); > + } > +} > + > struct qemu_romfile_s { > struct romfile_s file; > int select, skip; > @@ -303,6 +330,24 @@ qemu_cfg_read_file(struct romfile_s *file, void *dst, u32 maxlen) > return file->size; > } > > +static int > +qemu_cfg_write_file(void *src, struct romfile_s *file, u32 maxlen) > +{ > + if (file->size < maxlen) > + return -1; > + struct qemu_romfile_s *qfile; > + qfile = container_of(file, struct qemu_romfile_s, file); > + if (qfile->skip == 0) { > + /* Do it in one transfer */ > + qemu_cfg_write_entry(src, qfile->select, file->size); > + } else { > + qemu_cfg_select(qfile->select); > + qemu_cfg_skip(qfile->skip); > + qemu_cfg_write(src, file->size); > + } > + return file->size; > +} I'd prefer if we could break this patch into two parts - one part to add the write interface to fw_cfg and one part to add ALLOCATE_RET_ADDR. I'm fine with both interfaces, but the QEMU parts still need to be committed prior to committing to SeaBIOS. Having the patch in separate parts will make it both easier to review and commit at their appropriate times. > + > static void > qemu_romfile_add(char *name, int select, int skip, int size) > { > @@ -317,6 +362,7 @@ qemu_romfile_add(char *name, int select, int skip, int size) > qfile->select = select; > qfile->skip = skip; > qfile->file.copy = qemu_cfg_read_file; > + qfile->file.write_back = qemu_cfg_write_file; > romfile_add(&qfile->file); > } I don't think it is worthwhile to extend the romfile mechanism with a write_back() method. Instead, I'd export qemu_cfg_write_file(), extend it to verify the passed in romfile is a fw_cfg file (file->copy == qemu_cfg_read_file), and change the callers to call it directly. > > diff --git a/src/fw/paravirt.h b/src/fw/paravirt.h > index d8eb7c4..479eaf9 100644 > --- a/src/fw/paravirt.h > +++ b/src/fw/paravirt.h > @@ -43,6 +43,7 @@ static inline int runningOnKVM(void) { > #define QEMU_CFG_DMA_CTL_READ 0x02 > #define QEMU_CFG_DMA_CTL_SKIP 0x04 > #define QEMU_CFG_DMA_CTL_SELECT 0x08 > +#define QEMU_CFG_DMA_CTL_WRITE 0x10 > > // QEMU_CFG_DMA ID bit > #define QEMU_CFG_VERSION_DMA 2 > diff --git a/src/fw/romfile_loader.c b/src/fw/romfile_loader.c > index f4b17ff..945572f 100644 > --- a/src/fw/romfile_loader.c > +++ b/src/fw/romfile_loader.c > @@ -127,6 +127,38 @@ err: > warn_internalerror(); > } > > +static void romfile_loader_return_addr(struct romfile_loader_entry_s *entry, > + struct romfile_loader_files *files) > +{ > + struct romfile_loader_file *alloc_file; > + struct romfile_loader_file *addr_file; > + u64 addr; > + int ret; > + > + alloc_file = romfile_loader_find(entry->alloc_ret_file, files); > + addr_file = romfile_loader_find(entry->alloc_ret_addr_file, files); > + > + if (!alloc_file || !addr_file || !alloc_file->data || !addr_file->data || > + addr_file->file->size < sizeof(addr)) > + goto err; > + > + /* Get the address of the just-allocated file > + * and stuff it in the address file */ > + memcpy(&addr, &alloc_file->data, sizeof(addr)); > + addr = cpu_to_le64(addr); > + memcpy(addr_file->data, &addr, sizeof(addr)); > + > + if (!addr_file->file->write_back) > + goto err; > + > + ret = addr_file->file->write_back(&addr, addr_file->file, sizeof(addr)); > + if (ret != sizeof(addr)) > + goto err; > + return; > +err: > + warn_internalerror(); > +} > + > int romfile_loader_execute(const char *name) > { > struct romfile_loader_entry_s *entry; > @@ -161,6 +193,11 @@ int romfile_loader_execute(const char *name) > break; > case ROMFILE_LOADER_COMMAND_ADD_CHECKSUM: > romfile_loader_add_checksum(entry, files); > + break; > + case ROMFILE_LOADER_COMMAND_ALLOCATE_RET_ADDR: > + romfile_loader_allocate(entry, files); > + romfile_loader_return_addr(entry, files); > + break; > default: > /* Skip commands that we don't recognize. */ > break; > diff --git a/src/fw/romfile_loader.h b/src/fw/romfile_loader.h > index 15eab2a..ea161e8 100644 > --- a/src/fw/romfile_loader.h > +++ b/src/fw/romfile_loader.h > @@ -51,15 +51,32 @@ struct romfile_loader_entry_s { > u32 cksum_length; > }; > > + /* > + * COMMAND_ALLOCATE_RETURN_ADDR - allocate a table from @alloc_file > + * subject to @alloc_ret_align alignment (must be power of 2) > + * and @alloc_ret_zone (can be HIGH or FSEG) requirements. > + * Additionally, return the address of the allocation in > + * @addr_file. > + * > + * This may be used instead of COMMAND_ALLOCATE Minor nit - a tab snuck in here. > + */ > + struct { > + char alloc_ret_file[ROMFILE_LOADER_FILESZ]; > + u32 alloc_ret_align; > + u8 alloc_ret_zone; > + char alloc_ret_addr_file[ROMFILE_LOADER_FILESZ]; > + }; > + > /* padding */ > char pad[124]; > }; > }; > > enum { > - ROMFILE_LOADER_COMMAND_ALLOCATE = 0x1, > - ROMFILE_LOADER_COMMAND_ADD_POINTER = 0x2, > - ROMFILE_LOADER_COMMAND_ADD_CHECKSUM = 0x3, > + ROMFILE_LOADER_COMMAND_ALLOCATE = 0x1, > + ROMFILE_LOADER_COMMAND_ADD_POINTER = 0x2, > + ROMFILE_LOADER_COMMAND_ADD_CHECKSUM = 0x3, > + ROMFILE_LOADER_COMMAND_ALLOCATE_RET_ADDR = 0x4, > }; > > enum { > diff --git a/src/romfile.h b/src/romfile.h > index c6d62a1..8694cc1 100644 > --- a/src/romfile.h > +++ b/src/romfile.h > @@ -9,6 +9,7 @@ struct romfile_s { > char name[128]; > u32 size; > int (*copy)(struct romfile_s *file, void *dest, u32 maxlen); > + int (*write_back)(void *src, struct romfile_s *file, u32 maxlen); > }; > void romfile_add(struct romfile_s *file); > struct romfile_s *romfile_findprefix(const char *prefix, struct romfile_s *prev); -Kevin

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SeaBIOS January 2017