SeaBIOS January 2017

seabios@seabios.org

14 participants
22 discussions

Re: [SeaBIOS] [PATCH] block: add NVMe boot support
by Stecklina, Julian 22 Jan '17

22 Jan '17

Kevin, On Jan 21, 2017 09:32, Kevin O'Connor <kevin(a)koconnor.net> wrote: The copyright would need to say the file is licensed under the LGPLv3. Preference would be to use what the other files have: // This file may be distributed under the terms of the GNU LGPLv3 license. I'll post an updated version. If you have any other comments, I'd be glad to address them as well. Julian

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[PATCH] QEMU DMA: Add ability to write back to fw_cfg file
by ben＠skyportsystems.com 20 Jan '17

20 Jan '17

From: Ben Warren <ben(a)skyportsystems.com> This adds a new command to the DMA protocol. The command allows the memory allocation of a fw_cfg file by BIOS and subsequent return of the allocated address to QEMU. The initial use case is for Windows VM Generation ID, where QEMU needs to change the contents of fw_cfg data at runtime, while still having BIOS allocate and manage the memory. Signed-off-by: Ben Warren <ben(a)skyportsystems.com> --- src/fw/paravirt.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ src/fw/paravirt.h | 1 + src/fw/romfile_loader.c | 37 +++++++++++++++++++++++++++++++++++++ src/fw/romfile_loader.h | 23 ++++++++++++++++++++--- src/romfile.h | 1 + 5 files changed, 105 insertions(+), 3 deletions(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 6de70f6..f7bf422 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -253,6 +253,20 @@ qemu_cfg_read(void *buf, int len) } static void +qemu_cfg_write(void *buf, int len) +{ + if (len == 0) { + return; + } + + if (qemu_cfg_dma_enabled()) { + qemu_cfg_dma_transfer(buf, len, QEMU_CFG_DMA_CTL_WRITE); + } else { + outsb(PORT_QEMU_CFG_DATA, buf, len); + } +} + +static void qemu_cfg_skip(int len) { if (len == 0) { @@ -280,6 +294,19 @@ qemu_cfg_read_entry(void *buf, int e, int len) } } +static void +qemu_cfg_write_entry(void *buf, int e, int len) +{ + if (qemu_cfg_dma_enabled()) { + u32 control = (e << 16) | QEMU_CFG_DMA_CTL_SELECT + | QEMU_CFG_DMA_CTL_WRITE; + qemu_cfg_dma_transfer(buf, len, control); + } else { + qemu_cfg_select(e); + qemu_cfg_write(buf, len); + } +} + struct qemu_romfile_s { struct romfile_s file; int select, skip; @@ -303,6 +330,24 @@ qemu_cfg_read_file(struct romfile_s *file, void *dst, u32 maxlen) return file->size; } +static int +qemu_cfg_write_file(void *src, struct romfile_s *file, u32 maxlen) +{ + if (file->size < maxlen) + return -1; + struct qemu_romfile_s *qfile; + qfile = container_of(file, struct qemu_romfile_s, file); + if (qfile->skip == 0) { + /* Do it in one transfer */ + qemu_cfg_write_entry(src, qfile->select, file->size); + } else { + qemu_cfg_select(qfile->select); + qemu_cfg_skip(qfile->skip); + qemu_cfg_write(src, file->size); + } + return file->size; +} + static void qemu_romfile_add(char *name, int select, int skip, int size) { @@ -317,6 +362,7 @@ qemu_romfile_add(char *name, int select, int skip, int size) qfile->select = select; qfile->skip = skip; qfile->file.copy = qemu_cfg_read_file; + qfile->file.write_back = qemu_cfg_write_file; romfile_add(&qfile->file); } diff --git a/src/fw/paravirt.h b/src/fw/paravirt.h index d8eb7c4..479eaf9 100644 --- a/src/fw/paravirt.h +++ b/src/fw/paravirt.h @@ -43,6 +43,7 @@ static inline int runningOnKVM(void) { #define QEMU_CFG_DMA_CTL_READ 0x02 #define QEMU_CFG_DMA_CTL_SKIP 0x04 #define QEMU_CFG_DMA_CTL_SELECT 0x08 +#define QEMU_CFG_DMA_CTL_WRITE 0x10 // QEMU_CFG_DMA ID bit #define QEMU_CFG_VERSION_DMA 2 diff --git a/src/fw/romfile_loader.c b/src/fw/romfile_loader.c index f4b17ff..945572f 100644 --- a/src/fw/romfile_loader.c +++ b/src/fw/romfile_loader.c @@ -127,6 +127,38 @@ err: warn_internalerror(); } +static void romfile_loader_return_addr(struct romfile_loader_entry_s *entry, + struct romfile_loader_files *files) +{ + struct romfile_loader_file *alloc_file; + struct romfile_loader_file *addr_file; + u64 addr; + int ret; + + alloc_file = romfile_loader_find(entry->alloc_ret_file, files); + addr_file = romfile_loader_find(entry->alloc_ret_addr_file, files); + + if (!alloc_file || !addr_file || !alloc_file->data || !addr_file->data || + addr_file->file->size < sizeof(addr)) + goto err; + + /* Get the address of the just-allocated file + * and stuff it in the address file */ + memcpy(&addr, &alloc_file->data, sizeof(addr)); + addr = cpu_to_le64(addr); + memcpy(addr_file->data, &addr, sizeof(addr)); + + if (!addr_file->file->write_back) + goto err; + + ret = addr_file->file->write_back(&addr, addr_file->file, sizeof(addr)); + if (ret != sizeof(addr)) + goto err; + return; +err: + warn_internalerror(); +} + int romfile_loader_execute(const char *name) { struct romfile_loader_entry_s *entry; @@ -161,6 +193,11 @@ int romfile_loader_execute(const char *name) break; case ROMFILE_LOADER_COMMAND_ADD_CHECKSUM: romfile_loader_add_checksum(entry, files); + break; + case ROMFILE_LOADER_COMMAND_ALLOCATE_RET_ADDR: + romfile_loader_allocate(entry, files); + romfile_loader_return_addr(entry, files); + break; default: /* Skip commands that we don't recognize. */ break; diff --git a/src/fw/romfile_loader.h b/src/fw/romfile_loader.h index 15eab2a..ea161e8 100644 --- a/src/fw/romfile_loader.h +++ b/src/fw/romfile_loader.h @@ -51,15 +51,32 @@ struct romfile_loader_entry_s { u32 cksum_length; }; + /* + * COMMAND_ALLOCATE_RETURN_ADDR - allocate a table from @alloc_file + * subject to @alloc_ret_align alignment (must be power of 2) + * and @alloc_ret_zone (can be HIGH or FSEG) requirements. + * Additionally, return the address of the allocation in + * @addr_file. + * + * This may be used instead of COMMAND_ALLOCATE + */ + struct { + char alloc_ret_file[ROMFILE_LOADER_FILESZ]; + u32 alloc_ret_align; + u8 alloc_ret_zone; + char alloc_ret_addr_file[ROMFILE_LOADER_FILESZ]; + }; + /* padding */ char pad[124]; }; }; enum { - ROMFILE_LOADER_COMMAND_ALLOCATE = 0x1, - ROMFILE_LOADER_COMMAND_ADD_POINTER = 0x2, - ROMFILE_LOADER_COMMAND_ADD_CHECKSUM = 0x3, + ROMFILE_LOADER_COMMAND_ALLOCATE = 0x1, + ROMFILE_LOADER_COMMAND_ADD_POINTER = 0x2, + ROMFILE_LOADER_COMMAND_ADD_CHECKSUM = 0x3, + ROMFILE_LOADER_COMMAND_ALLOCATE_RET_ADDR = 0x4, }; enum { diff --git a/src/romfile.h b/src/romfile.h index c6d62a1..8694cc1 100644 --- a/src/romfile.h +++ b/src/romfile.h @@ -9,6 +9,7 @@ struct romfile_s { char name[128]; u32 size; int (*copy)(struct romfile_s *file, void *dest, u32 maxlen); + int (*write_back)(void *src, struct romfile_s *file, u32 maxlen); }; void romfile_add(struct romfile_s *file); struct romfile_s *romfile_findprefix(const char *prefix, struct romfile_s *prev); -- 2.10.1 (Apple Git-78)

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[PATCH] ahci: Set upper 32-bit registers to zero
by Ladi Prosek 17 Jan '17

17 Jan '17

If the HBA supports 64-bit addressing, the registers may contain non-zero values, for example after reboot as a leftover from the OS driving the adapter. Signed-off-by: Ladi Prosek <lprosek(a)redhat.com> --- src/hw/ahci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 261a7d2..2eee192 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -361,6 +361,11 @@ ahci_port_alloc(struct ahci_ctrl_s *ctrl, u32 pnr) ahci_port_writel(ctrl, pnr, PORT_LST_ADDR, (u32)port->list); ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR, (u32)port->fis); + if (ctrl->caps & HOST_CAP_64) { + ahci_port_writel(ctrl, pnr, PORT_LST_ADDR_HI, 0); + ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR_HI, 0); + } + return port; } -- 2.7.4

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 12 Jan '17

12 Jan '17

On Thu, Jan 12, 2017 at 04:53:32PM +0200, Евгени Димитров wrote: > On Thu, Jan 12, 2017 at 4:45 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > The additional debugging reports the controller is running and not > > reporting an error (which is in addition to the transfer descriptor > > reporting that it is also running without error). I'm not sure what > > is going on. Can you try disabling CONFIG_MALLOC_UPPERMEMORY and > > retry? > > That did it. Do you think it's safe to just leave this option off? Yes, it's safe. Some chipsets wont do DMA to the memory region between 0xc0000-0x100000. It looks like you have one of those boards. This can also be specified in the coreboot build - see src/mainboard/intel/mohonpeak/config_seabios and src/mainboard/intel/mohonpeak/Kconfig for an example of how to do that. -Kevin

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 12 Jan '17

12 Jan '17

On Wed, Jan 11, 2017 at 09:23:00AM +0200, Евгени Димитров wrote: > On Tue, Jan 10, 2017 at 7:14 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > On Mon, Jan 09, 2017 at 09:31:22AM +0200, Евгени Димитров wrote: > > > On Fri, Jan 6, 2017 at 4:46 PM, Kevin O'Connor <kevin(a)koconnor.net> > > wrote: > > > > Are you trying to boot from the "Multimedia Card Reader" or from a > > > > regular USB flash drive? If you're not booting from the card reader, > > > > does the patch below help? > > > > > > I was trying to boot from whatever USB devices I can get my hands on. > > > Ultimately my goal is to boot from a regular flash drive. The patch > > doesn't > > > help. > > > > I'm not sure what is happening - it looks like the controller is > > shutting down, but it's unclear why. What do you get with the patch > > below? The additional debugging reports the controller is running and not reporting an error (which is in addition to the transfer descriptor reporting that it is also running without error). I'm not sure what is going on. Can you try disabling CONFIG_MALLOC_UPPERMEMORY and retry? -Kevin

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 11 Jan '17

11 Jan '17

On Mon, Jan 09, 2017 at 09:31:22AM +0200, Евгени Димитров wrote: > On Fri, Jan 6, 2017 at 4:46 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > Are you trying to boot from the "Multimedia Card Reader" or from a > > regular USB flash drive? If you're not booting from the card reader, > > does the patch below help? > > I was trying to boot from whatever USB devices I can get my hands on. > Ultimately my goal is to boot from a regular flash drive. The patch doesn't > help. I'm not sure what is happening - it looks like the controller is shutting down, but it's unclear why. What do you get with the patch below? -Kevin --- a/src/hw/usb-ehci.c +++ b/src/hw/usb-ehci.c @@ -519,6 +519,9 @@ ehci_wait_td(struct ehci_pipe *pipe, struct ehci_qtd *td, u32 end) ehci_reset_pipe(pipe); struct usb_ehci_s *cntl = container_of( GET_LOWFLAT(pipe->pipe.cntl), struct usb_ehci_s, usb); + if (!MODESEGMENT) + dprintf(1, "ehci usbcmd=%08x usbsts=%08x\n" + , cntl->regs->usbcmd, cntl->regs->usbsts); ehci_waittick(cntl); return -1; }

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 09 Jan '17

09 Jan '17

On Fri, Jan 06, 2017 at 09:22:46AM +0200, Евгени Димитров wrote: > On Thu, Jan 5, 2017 at 6:29 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > On Thu, Jan 05, 2017 at 09:44:14AM +0200, Евгени Димитров wrote: > > > On Wed, Jan 4, 2017 at 4:52 PM, Kevin O'Connor <kevin(a)koconnor.net> > > wrote: > > > > > > > On Wed, Jan 04, 2017 at 03:57:33PM +0200, Евгени Димитров wrote: > > > > > Hi, > > > > > > > > > > I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When > > > > > trying to boot from an USB device I get the following error: > > > > > > > > > > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > > > > > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > > > > > ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 > > > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 > > > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 > > > > > WARNING - Timeout at ehci_wait_td:516! > > > > > ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 > > td=0x00006b40 > > > > > status=d0d80 > > > > > USB transmission failed > > > > > Unable to configure USB MSC drive. > > > > > phys_free f6030 (detail=0x0f7688a0) > > > > > Unable to configure USB MSC device. > > > > > > > > Did you disable threads in seabios (either via the kconfig option or > > > > via the /etc/threads runtime option)? It's not recommended to disable > > > > threads, and the USB code is less capable of handling timeouts when > > > > threads are disabled. Can you retry (and send the log) with threads > > > > enabled. > > > > > > > > If that fails, can you also try disabling CONFIG_USB_EHCI in Kconfig > > > > and send that log as well. > > > I get the same error with threads enabled. Disabling ehci did not help > > > either. Logs are attached as requested. > > > > It looks like the USB device is successfully identified and > > configured, but when sending the "inquiry" command to the drive behind > > the USB interface the connection halts. Not sure why that would be - > > it could be something with the controller, but it's odd that it > > happens with both the ohci and ehci controllers. > > > > If you boot to linux (using some other bootable device) what does > > 'lsusb' and 'lsusb -t' report? Have you tested with a different type > > of usb drive? > > > > -Kevin > > > > USB works on Linux. And yes I have tried a bunch of USB drives. All of them > failed with the same error. > > root@OpenWrt:/# lsusb > Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub > Bus 001 Device 002: ID 0011:7788 > Bus 001 Device 003: ID 058f:6377 Alcor Micro Corp. Multimedia Card Reader > Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub > root@OpenWrt:/# lsusb -t > /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=ohci-pci/4p, 12M > /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=ehci-pci/4p, 480M > |__ Port 1: Dev 3, If 0, Class=Mass Storage, Driver=, 480M > |__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=, 480M Are you trying to boot from the "Multimedia Card Reader" or from a regular USB flash drive? If you're not booting from the card reader, does the patch below help? -Kevin --- a/src/hw/usb-msc.c +++ b/src/hw/usb-msc.c @@ -203,6 +203,8 @@ usb_msc_setup(struct usbdevice_s *usbdev) goto fail; int maxlun = usb_msc_maxlun(usbdev->defpipe); + if (maxlun) + goto fail; int lun, pipesused = 0; for (lun = 0; lun < maxlun + 1; lun++) { int ret = usb_msc_lun_setup(inpipe, outpipe, usbdev, lun);

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 06 Jan '17

06 Jan '17

On Thu, Jan 05, 2017 at 09:44:14AM +0200, Евгени Димитров wrote: > On Wed, Jan 4, 2017 at 4:52 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > On Wed, Jan 04, 2017 at 03:57:33PM +0200, Евгени Димитров wrote: > > > Hi, > > > > > > I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When > > > trying to boot from an USB device I get the following error: > > > > > > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > > > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > > > ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 > > > WARNING - Timeout at ehci_wait_td:516! > > > ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 td=0x00006b40 > > > status=d0d80 > > > USB transmission failed > > > Unable to configure USB MSC drive. > > > phys_free f6030 (detail=0x0f7688a0) > > > Unable to configure USB MSC device. > > > > Did you disable threads in seabios (either via the kconfig option or > > via the /etc/threads runtime option)? It's not recommended to disable > > threads, and the USB code is less capable of handling timeouts when > > threads are disabled. Can you retry (and send the log) with threads > > enabled. > > > > If that fails, can you also try disabling CONFIG_USB_EHCI in Kconfig > > and send that log as well. > I get the same error with threads enabled. Disabling ehci did not help > either. Logs are attached as requested. It looks like the USB device is successfully identified and configured, but when sending the "inquiry" command to the drive behind the USB interface the connection halts. Not sure why that would be - it could be something with the controller, but it's odd that it happens with both the ohci and ehci controllers. If you boot to linux (using some other bootable device) what does 'lsusb' and 'lsusb -t' report? Have you tested with a different type of usb drive? -Kevin

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 05 Jan '17

05 Jan '17

On Wed, Jan 04, 2017 at 03:57:33PM +0200, Евгени Димитров wrote: > Hi, > > I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When > trying to boot from an USB device I get the following error: > > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 > WARNING - Timeout at ehci_wait_td:516! > ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 td=0x00006b40 > status=d0d80 > USB transmission failed > Unable to configure USB MSC drive. > phys_free f6030 (detail=0x0f7688a0) > Unable to configure USB MSC device. Did you disable threads in seabios (either via the kconfig option or via the /etc/threads runtime option)? It's not recommended to disable threads, and the USB code is less capable of handling timeouts when threads are disabled. Can you retry (and send the log) with threads enabled. If that fails, can you also try disabling CONFIG_USB_EHCI in Kconfig and send that log as well. -Kevin

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USB timeout on ALIX.2C2 (CS5536)
by Евгени Димитров 04 Jan '17

04 Jan '17

Hi, I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When trying to boot from an USB device I get the following error: Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 WARNING - Timeout at ehci_wait_td:516! ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 td=0x00006b40 status=d0d80 USB transmission failed Unable to configure USB MSC drive. phys_free f6030 (detail=0x0f7688a0) Unable to configure USB MSC device. Google found a thread from 2012 [1] where someone had the same problem with this particular chipset. Unfortunately he was unable to resolve the issue. Attached you will find the complete logs from both Coreboot and SeaBIOS. [1] https://www.coreboot.org/pipermail/coreboot/2012-October/071629.html

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SeaBIOS January 2017