On Sun, Feb 21, 2010 at 04:18:38PM -0700, Brandon Bennett wrote:
> > On Sat, Feb 20, 2010 at 9:05 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote:
> >> Should a kernel fail during boot, I'd suspect it doesn't like one of
> >> the apm/pcibios callbacks, or it doesn't like one of the
> >> smbios/mptable/acpi tables. You could try compiling the SeaBIOS code
> >> (see http://seabios.org/Download ) and increasing the debugging by
> >> modifying src/config.h. Specifically, you could increase
> >> CONFIG_DEBUG_LEVEL, and set DEBUG_HDL_pcibios32 and DEBUG_HDL_apm to
> >> 1. Also, you could try disabling some of the features to see if that
> >> prevents the fault (eg, disabling CONFIG_ACPI / CONFIG_SMBIOS /
> >> CONFIG_MPTABLE).
> >
>
> I have narrowed it down to SMBIOS. If I disable CONFIG_SMBIOS the
> image boots up fine.
Gleb, have you seen this thread?
Some of the recent changes to smbios that look like possible culprits
are:
Make SMBIOS table pass MS SVVP test
Use MaxCountCPUs during building of per cpu tables.
Add malloc_high/fseg() and rework bios table creation to use them.
There were other changes, but the comments indicate they were only
ports of changes already in bochs. I suppose it's also possible the
lack of smbios is turning off some other feature in the guest (eg,
acpi) that's the real culprit.
-Kevin
Without this BIOS fails to remap 0xf0000 memory from ROM to RAM so writes
to F-segment modify ROM content instead of memory copy. Since QEMU does
not reloads ROMs during reset on next boot modified copy of BIOS is used.
Signed-off-by: Gleb Natapov <gleb(a)redhat.com>
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 933ad86..0bf435d 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -99,10 +99,6 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
int i, r;
uint32_t smram, addr;
- if (kvm_enabled()) {
- /* FIXME: Support remappings and protection changes. */
- return;
- }
update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
for(i = 0; i < 12; i++) {
r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
--
Gleb.
Hi Stefan,
I'm CC'ing the mailing list.
On Wed, Nov 24, 2010 at 11:45:17AM -0500, Stefan Berger wrote:
> Hi Kevin,
>
> while I am porting the BIOS code for TCG support to SeaBIOS, I am
> wondering about the following:
>
> 'When' is it recommendable to switch from 16 bit to 32bit.
To be honest, this has never really been done before in SeaBIOS, so I
think we'll have to figure this out as we go. Since you need to
access full memory, it looks like it will be required to jump into
32bit mode.
>I am
> asking because the interface I am implementing allows callers to
> pass input and output data structures using es:di and ds:si, with es
> and ds allowed to be loaded with anything possible. So my strategy
> in the Bochs BIOS was to switch to 32 bit even before calling the
> interrupt handler, there doing the case statement for branching into
> the actual functions (switch (regs->al)) and passing 32 bit pointers
> converted from es:di and ds:si to the functions doing the work and
> reading from those memory locations.
This sounds okay to me - it should be possible to implement
handle_1abb(regs) which does a call32(tcg32_1abb, regs). It's
possible to do all the pointer conversion while in 32bit mode.
>The 'thing' is also that
> several ones of the functions that can be called through the
> interrupt interface are also called from the implemented functions.
> Example:
>
> Functions A,B,C can be called via the interrupt handler.
>
> Function B also calls A.
> Function C also calls B.
This shouldn't really be an issue. The build should take care of
this.
>
> This is due to the hierarchical nature of the functions. Also, while
> for example B calls A, B fills a data structure (on the stack) that
> it passes to A. A of course can get the same data structure from the
> user calling the interrupt interface. So, by switching to 32 bit
> mode and converting to 32 bit pointers early I could previously
> avoid a lot of headaches with the segment registers in 16 bit mode
> and reading the data from wherever they may be. Would you have any
> concerns about switching to 32 bit mode early, so that the interrupt
> handler and anything subsequent runs in 32 bit mode?
I can't say for sure what will make sense without seeing the code
first, but it sounds okay to me.
-Kevin
>
> Regards,
> Stefan
>
>
>
Trimming CC list, adding seabios list.
On Sat, Nov 27, 2010 at 09:04:24PM +0200, Gleb Natapov wrote:
> On Sat, Nov 27, 2010 at 01:40:12PM -0500, Kevin O'Connor wrote:
> > On Sat, Nov 27, 2010 at 08:15:42PM +0200, Gleb Natapov wrote:
> > > Qemu does not know that Seabios needs optionrom to boot from a device.
> > > It knows even less about bcvs in option rom. Qemu knows about device
> > > itself, not how firmware boots from it.
> >
> > If the user wants to boot from a device and that device has an
> > optionrom, then it's a safe bet that the optionrom is needed to boot
> > from it.
> >
> Suppose we add SCSI support to Seabios and suppose SCSI card Seabios can
> natively boot from has optionrom. What Seabios will do in such situation
> and how qemu can know it? Besides qemu support tries to be firmware
> agnostic.
In such a situation, under my proposal, users wouldn't be able to
specify a default boot from their scsi drive until after qemu was also
upgraded to know seabios could boot native scsi. (Or, they'd only be
able to do it by adding in a command-line option.)
> > In any case, I'd rather have qemu know which devices seabios can boot
> > then have seabios try to figure out what rom to run from a device
> > path.
> You run all of them just like you do now. Information you get from qemu is
> only used for sorting BCV/BEV entries. BCV/BEV that does not have
> corespondent boot path in boot order list is put at the end.
If qemu sends in "/pci@i0cf8/scsi@3/disk@0,0" or
"/pci@i0cf8/ethernet@4/ethernet-phy@0" it will expect seabios to boot
from the appropriate device. In both cases, seabios would need to run
a rom in order to fulfill that request. Trying to figure out which
rom is quite painful. That's why I'd prefer to see qemu instead pass
in something like "/pci@i0cf8/rom@3/bcv@0" or "/pci@i0cf8/rom@4/bev".
That is, if the machine needs to boot via a rom I'd prefer qemu state
that explicitly.
BTW, in the situation where seabios has native device support (eg,
ATA), I don't have any concerns. (The names are a bit verbose, but
that's not really an issue.)
> > > BTW are you actually aware of any option rom with multiple BCVs and, if
> > > yes, how those BCVs differ?
> >
> > Multiple BCVs - yes. A SCSI card will define a BCV for each attached
> > drive. I don't have a scsi card myself, but the support was added by
> > a user who ran into the problem first hand.
> Optionrom is static. How number of BCVs can depend on number of attached
> drives?
Not sure what you mean by "Optionrom is static". SeaBIOS unlocks the
memory, and the optionrom can and will modify itself with additional
PNP headers so that it can list multiple BCVs - one for each drive.
In particular, gPXE uses self modification to relocate parts of itself
into high ram.
-Kevin
dev-i440fx.c contains functions related to the 440FX and PIIX. Those for the PIIX
should also apply to the ICH (e.g. piix_ide_init). Should they be moved to dev-piix_ich.c?
Sebastian
On Thu, Nov 25, 2010 at 08:18:45PM +0000, adq wrote:
> On 25 November 2010 11:28, Isaku Yamahata <yamahata(a)valinux.co.jp> wrote:
> > On Wed, Nov 24, 2010 at 02:08:16PM +0000, adq wrote:
> >> > Interesting. I was also thinking that maybe we can leverage overriding mechanisms that are already available. Maybe it's possible to squeeze the HPET node into an SSDT. Maybe we need to override the whole DSDT from the command line.
> >>
> >> We'll definitely need to override the DSDT for the applesmc device. I
> >> was thinking something along the lines of an additional DSDT binary
> >> supplied with QEMU for use when emulating apple hardware as you
> >> suggest.
> >
> > The patches for qemu and seabios have been floating around.
> > I wrote them for Q35 chipset support, but no one has gotten interested in it.
> > But now, you are there. I'm willing to rebase/resend them.
>
> I'd definitely be interested to see those!
Here is qemu part. I rebased and just compiled it.
>From df45b74ca7217d40981cd8895fb1b270fb8039ec Mon Sep 17 00:00:00 2001
Message-Id: <df45b74ca7217d40981cd8895fb1b270fb8039ec.1290775119.git.yamahata(a)valinux.co.jp>
In-Reply-To: <cover.1290775119.git.yamahata(a)valinux.co.jp>
References: <cover.1290775119.git.yamahata(a)valinux.co.jp>
From: Isaku Yamahata <yamahata(a)valinux.co.jp>
Date: Fri, 26 Nov 2010 21:25:26 +0900
Subject: [PATCH 1/1] acpi: add option, load_header, for -acpitable to load acpi header
This patch adds load_header option to -acpitable to load acpi
table which includes acpi header.
With this option and with seabios patches, alternative dsdt table
can be passed to BIOS.
Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp>
---
hw/acpi.c | 26 +++++++++++++++++++++++---
qemu-options.hx | 2 ++
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/hw/acpi.c b/hw/acpi.c
index 8071e7b..fe9bede 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -47,6 +47,7 @@ static int acpi_checksum(const uint8_t *data, int len)
int acpi_table_add(const char *t)
{
static const char *dfl_id = "QEMUQEMU";
+ bool load_header = false;
char buf[1024], *p, *f;
struct acpi_table_header acpi_hdr;
unsigned long val;
@@ -54,6 +55,17 @@ int acpi_table_add(const char *t)
struct acpi_table_header *acpi_hdr_p;
size_t off;
+ if (strncmp(t, "load_header", strlen("load_header")) == 0) {
+ /* the files includes acpi header to load.
+ * the acpi header options, sig, rev, ... will be ignored.
+ */
+ load_header = true;
+ t += strlen("load_header");
+ if (*t == ',') {
+ t++;
+ }
+ }
+
memset(&acpi_hdr, 0, sizeof(acpi_hdr));
if (get_param_value(buf, sizeof(buf), "sig", t)) {
@@ -110,7 +122,11 @@ int acpi_table_add(const char *t)
buf[0] = '\0';
}
- length = sizeof(acpi_hdr);
+ if (load_header) {
+ length = 0;
+ } else {
+ length = sizeof(acpi_hdr);
+ }
f = buf;
while (buf[0]) {
@@ -140,8 +156,12 @@ int acpi_table_add(const char *t)
*(uint16_t*)p = cpu_to_le32(length);
p += sizeof(uint16_t);
- memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
- off = sizeof(acpi_hdr);
+ if (load_header) {
+ off = 0;
+ } else {
+ off = sizeof(acpi_hdr);
+ memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
+ }
f = buf;
while (buf[0]) {
diff --git a/qemu-options.hx b/qemu-options.hx
index 4d99a58..c30eb2a 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -981,9 +981,11 @@ ETEXI
DEF("acpitable", HAS_ARG, QEMU_OPTION_acpitable,
"-acpitable [sig=str][,rev=n][,oem_id=str][,oem_table_id=str][,oem_rev=n][,asl_compiler_id=str][,asl_compiler_rev=n][,data=file1[:file2]...]\n"
+ "-acpitable [load_header][,data=file1[:file2]...]\n"
" ACPI table description\n", QEMU_ARCH_I386)
STEXI
@item -acpitable [sig=@var{str}][,rev=@var{n}][,oem_id=@var{str}][,oem_table_id=@var{str}][,oem_rev=@var{n}] [,asl_compiler_id=@var{str}][,asl_compiler_rev=@var{n}][,data=@var{file1}[:@var{file2}]...]
+@item -acpitable [load_header][,data=@var{file1}[:@var{file2}]...]
@findex -acpitable
Add ACPI table with specified header fields and context from specified files.
ETEXI
--
1.7.1.1
--
yamahata
The attached patch implements support for the transparent call of
functions in 32 bit space from 16 bit code and allows up to 6 parameters
being passed to a 32 bit function. 3 of the parameters are passed via
registers, the other ones via the stack. More parameters can be
supported but would require additional code (afaik, there is not call
for 'ret + %ecx' or equivalent replacement for 'ret + n' with dynamic n)
The core of the patch is in upcall.S where the assembly function is
added that handles the transitioning and the passing of the parameters.
Each function in the 32 bit space that is supposed to be callable from
16 bit space requires an entry in upcall_protos.h, describing its index
in the function call table, the numbers of parameters it takes and the
parameter types themselves. These function entries are then differently
expanded using #defines in the various files from which they are
included and help to build function calls (the stubs in 16 bit space),
the function call table in 32 bit space and declarations of prototypes
to catch mismatch of parameters.
16 bit code that calls the 32 bit function is putting all parameters
onto the stack but the #defines for 16 bit mode cause the function
<function name>_upcall to be called, which is an assembly macro towards
the end of upcall.S and prepares one more parameter in ebx to be passed
to 'upcall'. The ebx register here holds the offset into the function
call table in the lower 16 bits and the number of bytes that were put
onto the stack when the function was called. The latter is necessary to
fix up the stack in 'upcall' when parameters are passed via the stack so
that the original caller sees the stack as if it had called the 32 bit
function directly.
One test function test_highbios is being added that part 2 will then
call from 16 bit space.
Signed-off-by: Stefan Berger <stefanb(a)us.ibm.com>
---
Makefile | 8 +-
src/post.c | 4 +
src/romlayout.S | 1
src/upcall.S | 191
++++++++++++++++++++++++++++++++++++++++++++++++++++
src/upcall.c | 22 +++++
src/upcall.h | 28 +++++++
src/upcall_16bit.c | 5 +
src/upcall_protos.h | 14 +++
8 files changed, 269 insertions(+), 4 deletions(-)
Index: seabios/src/upcall.c
===================================================================
--- /dev/null
+++ seabios/src/upcall.c
@@ -0,0 +1,22 @@
+#include "config.h" // CONFIG_*
+#include "util.h"
+#include "types.h"
+#include "upcall.h"
+
+int
+test_highbios(u8 a, u16 b, u32 c, u8 d, u16 e, int f)
+{
+ dprintf(1,"test at %p\n",test_highbios);
+ dprintf(1,"a=%d,b=%d,c=%d,d=%d,e=%d,f=%d\n",a,b,c,d,e,f);
+ return a*b;
+}
+
+
+#define FUNC(IDX, NUMPARMS, RETTYPE, NAME, PARMS ...) \
+ [IDX] = NAME,
+
+void *function_table[] = {
+#include "upcall_protos.h"
+};
+
+#undef FUNC
Index: seabios/src/upcall.h
===================================================================
--- /dev/null
+++ seabios/src/upcall.h
@@ -0,0 +1,28 @@
+#ifndef UPCALL_H
+#define UPCALL_H
+
+/* the actual jump table */
+extern void *function_table[];
+
+# ifdef SIXTEENBIT
+
+# define FUNC(IDX, NUMPARMS, RETTYPE, NAME, PARMS...) \
+ RETTYPE NAME ## _upcall(PARMS);
+
+# else
+
+# define FUNC(IDX, NUMPARMS, RETTYPE, NAME, PARMS ...) \
+ RETTYPE NAME(PARMS);
+
+# endif
+
+#include "upcall_protos.h"
+#undef FUNC
+
+/*
+ * holds the pointer where the function_table has been relocated to in
+ * the 'high bios' in 32 bit
+ */
+extern void *function_table_ptr VAR16VISIBLE;
+
+#endif /* UPCALL_H */
Index: seabios/src/upcall.S
===================================================================
--- /dev/null
+++ seabios/src/upcall.S
@@ -0,0 +1,191 @@
+; .code16gcc
+
+// The maximum number of call parameters we can handle
+// First 3 are passed via registers, the rest via stack
+#define MAX_FUNC_ARGS 6
+#define MAX_ARG_BYTES ((MAX_FUNC_ARGS - 3) * 4)
+
+// Call a 32 bit function from 16bit mode via a stub in 16bit mode.
+// Clobbers: ecx
+// Result: eax
+ DECLFUNC upcall
+upcall:
+
+#define CHUNK0 ( 4 ) /* for the already pushed %ebx in the macro */
+
+ pushl %esi // protect
+
+ pushl %edx // 2nd parameter
+ pushl %eax // 1st parameter (will hold result)
+ pushl %ecx // 3rd parameter (clobbered)
+
+ pushf
+#define CHUNK1 (5 * 4)
+
+ // Disable irqs (and clear direction flag)
+ cli
+ cld
+
+ // Disable nmi
+ movl $CMOS_RESET_CODE|NMI_DISABLE_BIT, %eax
+ outb %al, $PORT_CMOS_INDEX
+ inb $PORT_CMOS_DATA, %al
+
+ // enable a20
+ inb $PORT_A20, %al
+ orb $A20_ENABLE_BIT, %al
+ outb %al, $PORT_A20
+
+ push %ds
+ push %es
+ push %esp
+#define CHUNK2 (2 * 2 + 1 * 4)
+
+ // assume ss = 0
+ and $0xffff, %esp
+
+ // Set segment descriptors
+ lidtw %cs:pmode_IDT_info
+ lgdtw %cs:rombios32_gdt_48
+
+ // Enable protected mode
+ movl %cr0, %eax
+ orl $CR0_PE, %eax
+ movl %eax, %cr0
+
+ ljmpl $SEG32_MODE32_CS, $(BUILD_BIOS_ADDR + 1f)
+
+ .code32
+1:
+ // init data segments
+ movl $SEG32_MODE32_DS, %eax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %fs
+ movw %ax, %gs
+
+ // remember function index and num stack parms
+ pushl %ebx
+#define CHUNK3 ( 4 )
+
+ // remember stackpointer to help against 'ret + n'
+ movl %esp, %esi
+
+#if MAX_ARG_BYTES > 0
+ // Copy 32 bit aguments from original 16 bit call
+ movl $MAX_ARG_BYTES/4, %ecx
+2:
+ pushl MAX_ARG_BYTES + CHUNK3 + CHUNK2 + CHUNK1 + CHUNK0(%esp)
+ loop 2b
+#endif
+
+ // call function in call table
+ mov (BUILD_BIOS_ADDR + function_table_ptr), %eax
+
+ // add offset into table
+ and $0xffff, %ebx
+ add %eax, %ebx
+
+ // load registers for register passing
+ movl MAX_ARG_BYTES + CHUNK3 + CHUNK2 +12(%esp), %edx
+ movl MAX_ARG_BYTES + CHUNK3 + CHUNK2 + 8(%esp), %eax
+ movl MAX_ARG_BYTES + CHUNK3 + CHUNK2 + 4(%esp), %ecx
+
+ // call function
+ call *(%ebx)
+
+ // Result to ecx
+ movl %eax, %ecx
+
+ // load expected stack with all parameters undone
+ movl %esi, %esp
+
+ // get previous ebx holding expected size of stack parms in upper
+ // 16 bit
+ popl %edx
+ shrl $16, %edx
+
+ // Return to real mode
+ ljmpw $SEG32_MODE16_CS, $3f
+
+ .code16gcc
+3:
+ // Disable protected mode
+ movl %cr0, %eax
+ andl $~CR0_PE, %eax
+ movl %eax, %cr0
+
+ // far jump to flush CPU queue after transition to real mode
+ ljmpw $SEG_BIOS, $4f
+
+4:
+ // restore IDT to normal real-mode defaults
+ lidtw %cs:rmode_IDT_info
+
+ // Clear segment registers
+ xorw %ax, %ax
+ movw %ax, %fs
+ movw %ax, %gs
+ movw %ax, %ss
+
+ popl %esp
+ pop %es
+ pop %ds
+ popf
+
+ // result to eax
+ mov %ecx, %eax
+ // expected size of stack parms into ecx
+ mov %edx, %ecx
+
+ addl $8, %esp // skip ecx, eax
+ popl %edx
+ popl %esi
+
+ popl %ebx // pushed by Upcall macro
+
+ // caller expects us to undo stack parameters
+ cmpl $0x0, %ecx
+ jne 5f
+ retl // for 0,1,2,3 parameters
+
+5:
+ cmpl $0x4, %ecx
+ jne 6f
+ retl $0x4 // for 4 parameters
+
+6:
+ cmpl $0x8, %ecx
+ jne 7f
+ retl $0x8 // for 5 parameters
+
+7:
+#if MAX_FUNC_ARGS > 6
+# error Need explicit code here to handle more parameters
+#endif
+ retl $0xc // for 6 parameters
+
+
+// The upcall macro loads ebx with the offset of the function call
+// (in the function_table) into the lower 16 bits and loads the size of the
+// parameters on the stack (beyond 3 parameters) into the upper 16 bits.
+ .macro doUpcall funcname idx numargs
+ DECLFUNC \funcname
+\funcname:
+ pushl %ebx
+.if \numargs > 3
+ movl $(\idx << 2 + (\numargs-3) << 18),%ebx
+.else
+ movl $(\idx << 2), %ebx
+.endif
+ jmp upcall
+ .endm
+
+ .code16gcc
+#define FUNC(IDX, NUMPARMS, RETTYPE, NAME, PARMS ...) \
+ doUpcall NAME ## _upcall IDX NUMPARMS
+
+#include "upcall_protos.h"
+
+#undef FUNC
Index: seabios/src/upcall_protos.h
===================================================================
--- /dev/null
+++ seabios/src/upcall_protos.h
@@ -0,0 +1,12 @@
+/* this file is included by multiple files and expands the #defines
+ differently each time */
+
+#ifdef SIXTEENBIT
+
+/* all function names below must be expanded with _upcall */
+
+# define test_highbios test_highbios_upcall
+
+#endif
+
+FUNC(0, 6, int , test_highbios, u8 a, u16 b, u32 c,u8 d, u16 e, int f)
Index: seabios/src/upcall_16bit.c
===================================================================
--- /dev/null
+++ seabios/src/upcall_16bit.c
@@ -0,0 +1,5 @@
+#include "config.h" // CONFIG_*
+#include "types.h"
+
+/* anchor to high bios */
+void *function_table_ptr VAR16VISIBLE = NULL;
Index: seabios/src/romlayout.S
===================================================================
--- seabios.orig/src/romlayout.S
+++ seabios/src/romlayout.S
@@ -19,6 +19,7 @@
#include "cmos.h" // CMOS_RESET_CODE
#include "../out/asm-offsets.h" // BREGS_*
#include "entryfuncs.S" // ENTRY_*
+#include "upcall.S"
/****************************************************************
Index: seabios/src/post.c
===================================================================
--- seabios.orig/src/post.c
+++ seabios/src/post.c
@@ -24,6 +24,7 @@
#include "paravirt.h" // qemu_cfg_port_probe
#include "ps2port.h" // ps2port_setup
#include "virtio-blk.h" // virtio_blk_setup
+#include "upcall.h" // function_table
/****************************************************************
@@ -307,6 +308,9 @@ reloc_init(void)
dprintf(1, "Relocating init from %p to %p (size %d)\n"
, code32init_start, dest, initsize);
s32 delta = dest - (void*)code32init_start;
+
+ function_table_ptr = (void *)&function_table + delta;
+
memcpy(dest, code32init_start, initsize);
updateRelocs(dest, _reloc_abs_start, _reloc_abs_end, delta);
updateRelocs(dest, _reloc_rel_start, _reloc_rel_end, -delta);
Index: seabios/Makefile
===================================================================
--- seabios.orig/Makefile
+++ seabios/Makefile
@@ -16,11 +16,11 @@ SRCBOTH=misc.c pmm.c stacks.c output.c u
pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \
usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c \
virtio-ring.c virtio-pci.c virtio-blk.c apm.c
-SRC16=$(SRCBOTH) system.c disk.c font.c
+SRC16=$(SRCBOTH) system.c disk.c font.c upcall_16bit.c
SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \
acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \
lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \
- pci_region.c
+ pci_region.c upcall.c
SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c
cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \
@@ -39,11 +39,11 @@ COMMONCFLAGS += $(call cc-option,$(CC),-
COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector-all,)
CFLAGS32FLAT = $(COMMONCFLAGS) -g -DMODE16=0 -DMODESEGMENT=0
-CFLAGSSEG = $(COMMONCFLAGS) -DMODESEGMENT=1 -fno-defer-pop \
+CFLAGSSEG = $(COMMONCFLAGS) -DMODESEGMENT=1 -DSIXTEENBIT -fno-defer-pop \
$(call
cc-option,$(CC),-fno-jump-tables,-DMANUAL_NO_JUMP_TABLE) \
$(call cc-option,$(CC),-fno-tree-switch-conversion,)
CFLAGS32SEG = $(CFLAGSSEG) -DMODE16=0 -g
-CFLAGS16INC = $(CFLAGSSEG) -DMODE16=1 \
+CFLAGS16INC = $(CFLAGSSEG) -DMODE16=1 -DSIXTEENBIT \
$(call cc-option,$(CC),--param
large-stack-frame=4,-fno-inline)
CFLAGS16 = $(CFLAGS16INC) -g
