SeaBIOS December 2009

seabios@seabios.org

15 participants
28 discussions

Re: [SeaBIOS] [PATCH] Seabios: Fix PkgLength calculation for the SSDT.
by Kevin O'Connor 09 Feb '10

09 Feb '10

On Mon, Dec 14, 2009 at 10:25:14AM +0100, Magnus Christensson wrote: >>> --- a/src/acpi.c >>> +++ b/src/acpi.c >>> @@ -464,10 +464,12 @@ build_ssdt(void) >>> // build processor scope header >>> *(ssdt_ptr++) = 0x10; // ScopeOp >>> if (cpu_length<= 0x3e) { >>> + /* Handle 1-4 CPUs with one byte encoding */ >>> *(ssdt_ptr++) = cpu_length + 1; >>> } else { >>> - *(ssdt_ptr++) = 0x7F; >>> - *(ssdt_ptr++) = (cpu_length + 2)>> 6; >>> + /* Handle 5-314 CPUs with two byte encoding */ >>> + *(ssdt_ptr++) = 0x40 | ((cpu_length + 1)& 0xf); >>> + *(ssdt_ptr++) = (cpu_length + 1)>> 4; >>> >> Should be cpu_length + 2 as far as I can tell. The current code is >> definitely broken. >> > Right. That should be cpu_length +2 in the else-part. Can you resend the patch with the change? Thanks, -Kevin

4 5

Recent patches committed
by Kevin O'Connor 30 Dec '09

30 Dec '09

The latest SeaBIOS git should now have all pending patches committed. If I've missed anything, please let me know. -Kevin

1 0

[PATCH] Don't reserve %ebx in code32seg chunk.
by Kevin O'Connor 29 Dec '09

29 Dec '09

It occurred to me that reserving %ebx is unnecessary because gcc can calculate the code offset when it needs it. This patch is on top of the 32bit PCI BIOS series. -Kevin diff --git a/Makefile b/Makefile index a5fd63d..b71d1a1 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,7 @@ CFLAGS32FLAT = $(COMMONCFLAGS) -g -DMODE16=0 -DMODESEGMENT=0 CFLAGSSEG = $(COMMONCFLAGS) -DMODESEGMENT=1 -fno-defer-pop \ $(call cc-option,$(CC),-fno-jump-tables,-DMANUAL_NO_JUMP_TABLE) \ $(call cc-option,$(CC),-fno-tree-switch-conversion,) -CFLAGS32SEG = $(CFLAGSSEG) -DMODE16=0 +CFLAGS32SEG = $(CFLAGSSEG) -DMODE16=0 -g CFLAGS16INC = $(CFLAGSSEG) -DMODE16=1 \ $(call cc-option,$(CC),--param large-stack-frame=4,) CFLAGS16 = $(CFLAGS16INC) -g diff --git a/src/biosvar.h b/src/biosvar.h index eb34286..db6783e 100644 --- a/src/biosvar.h +++ b/src/biosvar.h @@ -263,18 +263,28 @@ get_ebda_ptr() #if MODE16 == 0 && MODESEGMENT == 1 // In 32bit segmented mode %cs may not be readable and the code may be // relocated. The entry code sets up %gs with a readable segment and -// %ebx with the base code offset. +// the code offset can be determined by get_global_offset(). #define GLOBAL_SEGREG GS -#define GLOBAL_OFFSET __CodeOffset +static inline u32 __attribute_const get_global_offset(void) { + u32 ret; + asm(" calll 1f\n" + "1:popl %0\n" + " subl $1b, %0" + : "=r"(ret)); + return ret; +} #else #define GLOBAL_SEGREG CS -#define GLOBAL_OFFSET 0 +static inline u32 __attribute_const get_global_offset(void) { + return 0; +} #endif static inline u16 get_global_seg() { return GET_SEG(GLOBAL_SEGREG); } -#define GET_GLOBAL(var) \ - GET_VAR(GLOBAL_SEGREG, *(typeof(&(var)))((void*)&(var) + GLOBAL_OFFSET)) +#define GET_GLOBAL(var) \ + GET_VAR(GLOBAL_SEGREG, *(typeof(&(var)))((void*)&(var) \ + + get_global_offset())) #define SET_GLOBAL(var, val) do { \ ASSERT32FLAT(); \ (var) = (val); \ diff --git a/src/pcibios.c b/src/pcibios.c index 91b7655..2425a65 100644 --- a/src/pcibios.c +++ b/src/pcibios.c @@ -157,7 +157,8 @@ handle_1ab10e(struct bregs *regs) // Memcpy pir table slots to dest buffer. memcpy_far(buf_seg, buf_far - , get_global_seg(), (void*)(pirtable_g->slots) + GLOBAL_OFFSET + , get_global_seg() + , (void*)(pirtable_g->slots) + get_global_offset() , pirsize); // XXX - bochs bios sets bx to (1 << 9) | (1 << 11) diff --git a/src/romlayout.S b/src/romlayout.S index afdefed..43af112 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -390,9 +390,6 @@ pcibios32_entry: pushl %edi pushw %es pushw %ds - calll 1f // Setup %ebx to be code base -1: popl %ebx - subl $1b, %ebx movl %ds, %eax // Move %ds to %gs movl %eax, %gs movl %ss, %eax // Move %ss to %ds diff --git a/src/types.h b/src/types.h index cc64cba..cfa47fe 100644 --- a/src/types.h +++ b/src/types.h @@ -65,7 +65,6 @@ extern void __force_link_error__only_in_16bit() __attribute__ ((noreturn)); #define ASSERT16() do { } while (0) #define ASSERT32FLAT() __force_link_error__only_in_32bit_flat() #elif MODESEGMENT == 1 -register u32 __CodeOffset asm ("ebx") __VISIBLE; # define VISIBLE16 # define VISIBLE32FLAT # define VISIBLE32SEG __VISIBLE @@ -122,6 +121,7 @@ register u32 __CodeOffset asm ("ebx") __VISIBLE; #define noinline __attribute__((noinline)) #define __always_inline inline __attribute__((always_inline)) +#define __attribute_const __attribute__((__const__)) #define __stringify_1(x) #x #define __stringify(x) __stringify_1(x)

1 0

[PATCH] enumerate all PCI buses in mptable
by Gleb Natapov 29 Dec '09

29 Dec '09

Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/src/mptable.c b/src/mptable.c index 6e02524..206e131 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -65,19 +65,27 @@ mptable_init(void) } int entrycount = cpu - cpus; - /* isa bus */ struct mpt_bus *bus = (void*)cpu; - memset(bus, 0, sizeof(*bus)); - bus->type = MPT_TYPE_BUS; - bus->busid = 1; - memcpy(bus->bustype, "ISA ", sizeof(bus->bustype)); - entrycount++; + int bdf, max, lastbus = -1; + foreachpci(bdf, max) { + int curbus = pci_bdf_to_bus(bdf); + if (curbus == lastbus) + continue; + lastbus = curbus; + memset(bus, 0, sizeof(*bus)); + bus->type = MPT_TYPE_BUS; + bus->busid = curbus; + memcpy(bus->bustype, "PCI ", sizeof(bus->bustype)); + bus++; + entrycount++; + } - bus++; + /* isa bus */ + int isabusid; memset(bus, 0, sizeof(*bus)); bus->type = MPT_TYPE_BUS; - bus->busid = 0; - memcpy(bus->bustype, "PCI ", sizeof(bus->bustype)); + isabusid = bus->busid = lastbus + 1; + memcpy(bus->bustype, "ISA ", sizeof(bus->bustype)); entrycount++; /* ioapic */ @@ -93,7 +101,7 @@ mptable_init(void) /* irqs */ struct mpt_intsrc *intsrcs = (void*)&ioapic[1], *intsrc = intsrcs; - int bdf, max, dev = -1; + int dev = -1; unsigned short mask = 0, pinmask; foreachpci(bdf, max) { @@ -113,7 +121,7 @@ mptable_init(void) intsrc->type = MPT_TYPE_INTSRC; intsrc->irqtype = 0; /* INT */ intsrc->irqflag = 1; /* active high */ - intsrc->srcbus = 0; /* PCI bus */ + intsrc->srcbus = pci_bdf_to_bus(bdf); /* PCI bus */ intsrc->srcbusirq = (dev << 2) | (pin - 1); intsrc->dstapic = ioapic_id; intsrc->dstirq = irq; @@ -127,7 +135,7 @@ mptable_init(void) intsrc->type = MPT_TYPE_INTSRC; intsrc->irqtype = 0; /* INT */ intsrc->irqflag = 0; /* conform to bus spec */ - intsrc->srcbus = 1; /* ISA bus */ + intsrc->srcbus = isabusid; /* ISA bus */ intsrc->srcbusirq = i; intsrc->dstapic = ioapic_id; intsrc->dstirq = i; @@ -147,7 +155,7 @@ mptable_init(void) intsrc->type = MPT_TYPE_LOCAL_INT; intsrc->irqtype = 3; /* ExtINT */ intsrc->irqflag = 0; /* PO, EL default */ - intsrc->srcbus = 1; /* ISA */ + intsrc->srcbus = isabusid; /* ISA */ intsrc->srcbusirq = 0; intsrc->dstapic = 0; /* BSP == APIC #0 */ intsrc->dstirq = 0; /* LINTIN0 */ @@ -157,7 +165,7 @@ mptable_init(void) intsrc->type = MPT_TYPE_LOCAL_INT; intsrc->irqtype = 1; /* NMI */ intsrc->irqflag = 0; /* PO, EL default */ - intsrc->srcbus = 1; /* ISA */ + intsrc->srcbus = isabusid; /* ISA */ intsrc->srcbusirq = 0; intsrc->dstapic = 0; /* BSP == APIC #0 */ intsrc->dstirq = 1; /* LINTIN1 */ -- Gleb.

2 1

[PATCH 0/3] Support 32bit PCI BIOS calls
by Kevin O'Connor 29 Dec '09

29 Dec '09

This patch series adds support for 32bit PCI BIOS calls to SeaBIOS. Currently, the SeaBIOS binary is composed of two big chunks of data - the 16bit code (irq handlers) and the 32bit "flat mode" code (post and boot). This patch adds a third chunk for 32bit segmented code. This new code chunk uses explicit segment memory accesses like the 16bit code does, but is compiled in 32bit mode. I ran into one unexpected complication with this support - the PCI BIOS functions need to support position independent code, as the code and data segment base can vary. Unfortunately, using GCC's -fpic option doesn't work, because that also implies building a GOT/PLT which isn't desired and conflicts with segment accesses. To work around the issue, I reserve %ebx in the 32bit segmented code as a base offset and make sure all global variable accesses are relative to it. There are three patches - much of it is just renames to support the new code chunk. -Kevin

1 2

[PATCH 2/3] Only add "addr32" to memory accesses that require them
by Kevin O'Connor 29 Dec '09

29 Dec '09

Only add "addr32" to memory accesses that require them. Extract out addr32 to a parameter to the READx/WRITEx_SEG macros. diff --git a/src/farptr.h b/src/farptr.h index 3cc4170..0bd9248 100644 --- a/src/farptr.h +++ b/src/farptr.h @@ -14,81 +14,81 @@ extern u16 __segment_ES, __segment_CS, __segment_DS, __segment_SS; extern u16 __segment_FS, __segment_GS; // Low level macros for reading/writing memory via a segment selector. -#define READ8_SEG(SEG, value, var) \ - __asm__("addr32 movb %%" #SEG ":%1, %b0" : "=Qi"(value) \ +#define READ8_SEG(prefix, SEG, value, var) \ + __asm__(prefix "movb %%" #SEG ":%1, %b0" : "=Qi"(value) \ : "m"(var), "m"(__segment_ ## SEG)) -#define READ16_SEG(SEG, value, var) \ - __asm__("addr32 movw %%" #SEG ":%1, %w0" : "=ri"(value) \ +#define READ16_SEG(prefix, SEG, value, var) \ + __asm__(prefix "movw %%" #SEG ":%1, %w0" : "=ri"(value) \ : "m"(var), "m"(__segment_ ## SEG)) -#define READ32_SEG(SEG, value, var) \ - __asm__("addr32 movl %%" #SEG ":%1, %0" : "=ri"(value) \ +#define READ32_SEG(prefix, SEG, value, var) \ + __asm__(prefix "movl %%" #SEG ":%1, %0" : "=ri"(value) \ : "m"(var), "m"(__segment_ ## SEG)) -#define READ64_SEG(SEG, value, var) do { \ +#define READ64_SEG(prefix, SEG, value, var) do { \ union u64_u32_u __value; \ union u64_u32_u *__r64_ptr = (union u64_u32_u *)&(var); \ - READ32_SEG(SEG, __value.hi, __r64_ptr->hi); \ - READ32_SEG(SEG, __value.lo, __r64_ptr->lo); \ + READ32_SEG(prefix, SEG, __value.hi, __r64_ptr->hi); \ + READ32_SEG(prefix, SEG, __value.lo, __r64_ptr->lo); \ *(u64*)&(value) = __value.val; \ } while (0) -#define WRITE8_SEG(SEG, var, value) \ - __asm__("addr32 movb %b1, %%" #SEG ":%0" : "=m"(var) \ +#define WRITE8_SEG(prefix, SEG, var, value) \ + __asm__(prefix "movb %b1, %%" #SEG ":%0" : "=m"(var) \ : "Q"(value), "m"(__segment_ ## SEG)) -#define WRITE16_SEG(SEG, var, value) \ - __asm__("addr32 movw %w1, %%" #SEG ":%0" : "=m"(var) \ +#define WRITE16_SEG(prefix, SEG, var, value) \ + __asm__(prefix "movw %w1, %%" #SEG ":%0" : "=m"(var) \ : "r"(value), "m"(__segment_ ## SEG)) -#define WRITE32_SEG(SEG, var, value) \ - __asm__("addr32 movl %1, %%" #SEG ":%0" : "=m"(var) \ +#define WRITE32_SEG(prefix, SEG, var, value) \ + __asm__(prefix "movl %1, %%" #SEG ":%0" : "=m"(var) \ : "r"(value), "m"(__segment_ ## SEG)) -#define WRITE64_SEG(SEG, var, value) do { \ +#define WRITE64_SEG(prefix, SEG, var, value) do { \ union u64_u32_u __value; \ union u64_u32_u *__w64_ptr = (union u64_u32_u *)&(var); \ typeof(var) __value_tmp = (value); \ __value.val = *(u64*)&__value_tmp; \ - WRITE32_SEG(SEG, __w64_ptr->hi, __value.hi); \ - WRITE32_SEG(SEG, __w64_ptr->lo, __value.lo); \ + WRITE32_SEG(prefix, SEG, __w64_ptr->hi, __value.hi); \ + WRITE32_SEG(prefix, SEG, __w64_ptr->lo, __value.lo); \ } while (0) -// Low level macros for getting/setting a segment register. -#define __SET_SEG(SEG, value) \ - __asm__("movw %w1, %%" #SEG : "=m"(__segment_ ## SEG) \ - : "rm"(value)) -#define __GET_SEG(SEG) ({ \ - u16 __seg; \ - __asm__("movw %%" #SEG ", %w0" : "=rm"(__seg) \ - : "m"(__segment_ ## SEG)); \ - __seg;}) - // Macros for automatically choosing the appropriate memory size // access method. extern void __force_link_error__unknown_type(); -#define __GET_VAR(seg, var) ({ \ +#define __GET_VAR(prefix, seg, var) ({ \ typeof(var) __val; \ if (sizeof(__val) == 1) \ - READ8_SEG(seg, __val, var); \ + READ8_SEG(prefix, seg, __val, var); \ else if (sizeof(__val) == 2) \ - READ16_SEG(seg, __val, var); \ + READ16_SEG(prefix, seg, __val, var); \ else if (sizeof(__val) == 4) \ - READ32_SEG(seg, __val, var); \ + READ32_SEG(prefix, seg, __val, var); \ else if (sizeof(__val) == 8) \ - READ64_SEG(seg, __val, var); \ + READ64_SEG(prefix, seg, __val, var); \ else \ __force_link_error__unknown_type(); \ __val; }) -#define __SET_VAR(seg, var, val) do { \ - if (sizeof(var) == 1) \ - WRITE8_SEG(seg, var, (val)); \ - else if (sizeof(var) == 2) \ - WRITE16_SEG(seg, var, (val)); \ - else if (sizeof(var) == 4) \ - WRITE32_SEG(seg, var, (val)); \ - else if (sizeof(var) == 8) \ - WRITE64_SEG(seg, var, (val)); \ - else \ - __force_link_error__unknown_type(); \ +#define __SET_VAR(prefix, seg, var, val) do { \ + if (sizeof(var) == 1) \ + WRITE8_SEG(prefix, seg, var, (val)); \ + else if (sizeof(var) == 2) \ + WRITE16_SEG(prefix, seg, var, (val)); \ + else if (sizeof(var) == 4) \ + WRITE32_SEG(prefix, seg, var, (val)); \ + else if (sizeof(var) == 8) \ + WRITE64_SEG(prefix, seg, var, (val)); \ + else \ + __force_link_error__unknown_type(); \ } while (0) +// Low level macros for getting/setting a segment register. +#define __SET_SEG(SEG, value) \ + __asm__("movw %w1, %%" #SEG : "=m"(__segment_ ## SEG) \ + : "rm"(value)) +#define __GET_SEG(SEG) ({ \ + u16 __seg; \ + __asm__("movw %%" #SEG ", %w0" : "=rm"(__seg) \ + : "m"(__segment_ ## SEG)); \ + __seg;}) + // Macros for accessing a variable in another segment. (They // automatically update the %es segment and then make the appropriate // access.) @@ -127,8 +127,8 @@ extern void __force_link_error__unknown_type(); // Definitions when using segmented mode. #define GET_FARVAR(seg, var) __GET_FARVAR((seg), (var)) #define SET_FARVAR(seg, var, val) __SET_FARVAR((seg), (var), (val)) -#define GET_VAR(seg, var) __GET_VAR(seg, (var)) -#define SET_VAR(seg, var, val) __SET_VAR(seg, (var), (val)) +#define GET_VAR(seg, var) __GET_VAR("", seg, (var)) +#define SET_VAR(seg, var, val) __SET_VAR("", seg, (var), (val)) #define SET_SEG(SEG, value) __SET_SEG(SEG, (value)) #define GET_SEG(SEG) __GET_SEG(SEG) #define GET_FLATPTR(ptr) __GET_FLATPTR(ptr) diff --git a/src/pmm.c b/src/pmm.c index a72167b..d05cc6f 100644 --- a/src/pmm.c +++ b/src/pmm.c @@ -14,8 +14,13 @@ #if MODESEGMENT // The 16bit pmm entry points runs in "big real" mode, and can // therefore read/write to the 32bit malloc variables. -#define GET_PMMVAR(var) GET_FARVAR(0, (var)) -#define SET_PMMVAR(var, val) SET_FARVAR(0, (var), (val)) +#define GET_PMMVAR(var) ({ \ + SET_SEG(ES, 0); \ + __GET_VAR("addr32 ", ES, (var)); }) +#define SET_PMMVAR(var, val) do { \ + SET_SEG(ES, 0); \ + __SET_VAR("addr32 ", ES, (var), (val)); \ + } while (0) #else #define GET_PMMVAR(var) (var) #define SET_PMMVAR(var, val) do { (var) = (val); } while (0)

1 0

[PATCH] Don't overallocate mptable
by Kevin O'Connor 27 Dec '09

27 Dec '09

This patch causes the mptable to be built in temporary memory and then copied into the f-segment after it is complete. This makes better use of the limited space in the f-segment, and it makes it less likely an overflow will occur (eg, due to many PCI irq entries). -Kevin diff --git a/src/mptable.c b/src/mptable.c index 2409fcf..20c3d63 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -20,30 +20,12 @@ mptable_init(void) dprintf(3, "init MPTable\n"); - // Allocate memory - int length = (sizeof(struct mptable_config_s) - + sizeof(struct mpt_cpu) * MaxCountCPUs - + sizeof(struct mpt_bus) * 2 - + sizeof(struct mpt_ioapic) - + sizeof(struct mpt_intsrc) * 34); - struct mptable_config_s *config = malloc_fseg(length); - struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating)); - if (!config || !floating) { - dprintf(1, "No room for MPTABLE!\n"); - free(config); - free(floating); + // Config structure in temp area. + struct mptable_config_s *config = malloc_tmphigh(32*1024); + if (!config) { + dprintf(1, "No space for temp mptable\n"); return; } - - /* floating pointer structure */ - memset(floating, 0, sizeof(*floating)); - floating->signature = MPTABLE_SIGNATURE; - floating->physaddr = (u32)config; - floating->length = 1; - floating->spec_rev = 4; - floating->checksum -= checksum(floating, sizeof(*floating)); - - // Config structure. memset(config, 0, sizeof(*config)); config->signature = MPCONFIG_SIGNATURE; config->spec = 4; @@ -115,6 +97,8 @@ mptable_init(void) unsigned short mask = 0, pinmask; foreachpci(bdf, max) { + if (pci_bdf_to_bus(bdf) > 0) + break; int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN); int irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE); if (pin == 0) @@ -183,10 +167,32 @@ mptable_init(void) entrycount++; // Finalize config structure. + int length = (void*)intsrc - (void*)config; config->entrycount = entrycount; - config->length = (void*)intsrc - (void*)config; - config->checksum -= checksum(config, config->length); + config->length = length; + config->checksum -= checksum(config, length); + + // Allocate final memory locations + struct mptable_config_s *finalconfig = malloc_fseg(length); + struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating)); + if (!finalconfig || !floating) { + dprintf(1, "No room for MPTABLE!\n"); + free(config); + free(finalconfig); + free(floating); + return; + } + memcpy(finalconfig, config, length); + free(config); + + /* floating pointer structure */ + memset(floating, 0, sizeof(*floating)); + floating->signature = MPTABLE_SIGNATURE; + floating->physaddr = (u32)finalconfig; + floating->length = 1; + floating->spec_rev = 4; + floating->checksum -= checksum(floating, sizeof(*floating)); dprintf(1, "MP table addr=%p MPC table addr=%p size=%d\n", - floating, config, config->length); + floating, finalconfig, length); }

2 7

Next steps
by Kevin O'Connor 26 Dec '09

26 Dec '09

Here are my thoughts on upcoming enhancements that should go into SeaBIOS: * Merge recent patches. Most are simple fixes. The only big change is the ATA DMA support. * Add 32bit PCI BIOS support. SeaBIOS has lots of 32bit code, but the 32bit PCI BIOS support requires use of segmented 32bit mode - so, it's a bit of a pain to add. Right now, there are two main parts of seabios that are linked together in the final compile stage - the 16bit code and 32bit flat mode code. To support 32bit PCI, there will need to be three parts (16bit, 32bit flat, and 32bit segmented). This will also involve changing a bunch of "#if MODE16" tests to a new "#if MODESEGMENTS". This will make the final binary a bit bigger (eg, there will be another copy of dprintf). While doing this, it makes sense to convert the 32bit APM code to work the same way (right now 32bit APM just transitions to 16bit mode and calls the 16bit APM code). * Make CONFIG_THREAD_OPTIONROMS the default. This experimental feature allows SeaBIOS hardware init (eg, usb, ata, ps2) to run in parallel with option rom execution. It can speed boot time on real hardware. It's probably not much use for qemu, but I think it makes sense to run as much of the same code on coreboot and qemu as possible. There is a risk here of third-party option roms being confused by the preemption code - however, that should be a small risk and only testing will determine it. * Add int1589 support. This call facilitates entering 32bit mode via the bios. Bochs BIOS recently added support for it. It should be straight forward to add to SeaBIOS - the 'struct bregs' should have everything needed to restore state and directly return to the caller in 32bit mode. * Finish USB keyboard support - add auto-repeat, add LED support, add support for usb hubs. USB keyboard works today (at least on qemu and my Via hardware), but it's not fully fleshed out. These remaining items should be completed. Longer term items: * Possibly add in DMA for packet commands, and possibly add support for PATA timing code. The DMA on packet commands should be straight forward. Support for PATA timing can noticeably increase transfer speeds on these drives, but it requires per-chipset ide initialization code. That would require a lookup table based on the PCI ids of the ide controller to code capable of setting up the proper timing. * USB booting? This support is definitely needed, but there has been some debate on whether adding to SeaBIOS makes the most sense. My experience with ATA DMA indicates that EHCI support will also be a requirement. Any other items? -Kevin

1 0

[PATCH] Allocate smbios in temp space and copy into final location.
by Kevin O'Connor 26 Dec '09

26 Dec '09

Reduce memory needed in the reserved high memory area. diff --git a/src/smbios.c b/src/smbios.c index b812fce..870afbe 100644 --- a/src/smbios.c +++ b/src/smbios.c @@ -17,10 +17,14 @@ smbios_entry_point_init(u16 max_structure_size, u16 number_of_structures) { struct smbios_entry_point *ep = malloc_fseg(sizeof(*ep)); - if (! ep) { - dprintf(1, "No space for smbios entry table!\n"); + void *finaltable = malloc_high(structure_table_length); + if (!ep || !finaltable) { + dprintf(1, "No space for smbios tables!\n"); + free(ep); + free(finaltable); return; } + memcpy(finaltable, structure_table_address, structure_table_length); memcpy(ep->anchor_string, "_SM_", 4); ep->length = 0x1f; @@ -32,7 +36,7 @@ smbios_entry_point_init(u16 max_structure_size, memcpy(ep->intermediate_anchor_string, "_DMI_", 5); ep->structure_table_length = structure_table_length; - ep->structure_table_address = (u32)structure_table_address; + ep->structure_table_address = (u32)finaltable; ep->number_of_structures = number_of_structures; ep->smbios_bcd_revision = 0x24; @@ -40,7 +44,7 @@ smbios_entry_point_init(u16 max_structure_size, ep->intermediate_checksum -= checksum((void*)ep + 0x10, ep->length - 0x10); - dprintf(1, "SMBIOS ptr=%p table=%p\n", ep, structure_table_address); + dprintf(1, "SMBIOS ptr=%p table=%p\n", ep, finaltable); } #define load_str_field_with_default(type, field, def) \ @@ -362,6 +366,8 @@ smbios_init_type_127(void *start) return start + 2; } +#define TEMPSMBIOSSIZE (32 * 1024) + void smbios_init(void) { @@ -370,14 +376,15 @@ smbios_init(void) dprintf(3, "init SMBIOS tables\n"); - char *start = malloc_high(2048); // XXX - determine real size + char *start = malloc_tmphigh(TEMPSMBIOSSIZE); if (! start) { - dprintf(1, "No memory for smbios tables\n"); + dprintf(1, "No memory for temp smbios table\n"); return; } u32 nr_structs = 0, max_struct_size = 0; - char *q, *p = start, *end = start + 2048 - sizeof(struct smbios_type_127); + char *q, *p = start; + char *end = start + TEMPSMBIOSSIZE - sizeof(struct smbios_type_127); #define add_struct(type, args...) \ do { \ @@ -425,4 +432,5 @@ smbios_init(void) #undef add_struct smbios_entry_point_init(max_struct_size, p - start, start, nr_structs); + free(start); }

1 0

[PATCH] MPTable pci bus
by Kevin O'Connor 26 Dec '09

26 Dec '09

Order the bus descriptions in ascending order by busid as per MPTable spec. Current code only works with pci bus 0, so add a sanity check in case foreachpci were to return a higher bus. -Kevin diff --git a/src/mptable.c b/src/mptable.c index 6e02524..6b47b28 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -65,19 +65,19 @@ mptable_init(void) } int entrycount = cpu - cpus; - /* isa bus */ + /* buses */ struct mpt_bus *bus = (void*)cpu; memset(bus, 0, sizeof(*bus)); bus->type = MPT_TYPE_BUS; - bus->busid = 1; - memcpy(bus->bustype, "ISA ", sizeof(bus->bustype)); + bus->busid = 0; + memcpy(bus->bustype, "PCI ", sizeof(bus->bustype)); entrycount++; bus++; memset(bus, 0, sizeof(*bus)); bus->type = MPT_TYPE_BUS; - bus->busid = 0; - memcpy(bus->bustype, "PCI ", sizeof(bus->bustype)); + bus->busid = 1; + memcpy(bus->bustype, "ISA ", sizeof(bus->bustype)); entrycount++; /* ioapic */ @@ -97,6 +97,9 @@ mptable_init(void) unsigned short mask = 0, pinmask; foreachpci(bdf, max) { + if (pci_bdf_to_bus(bdf) > 0) + // Code currently only handles bus 0. + break; int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN); int irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE); if (pin == 0)

1 0

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS December 2009