SeaBIOS June 2014

seabios@seabios.org

14 participants
29 discussions

[PATCH v3] hw/pci: reserve IO and mem for pci express downstream ports with no devices attached

by Marcel Apfelbaum

Commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830 hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached introduced support for hot-plugging devices behind pci-2-pci bridges. Extend hotplug support also for pci express downstream ports. Signed-off-by: Marcel Apfelbaum <marcel.a(a)redhat.com> --- v2 -> v3: Addressed Michael S. Tsirkin comments: - Refactored pci_bus_hotplug_support function. - Removed PCI_EXP_FLAGS_TYPE_SHIFT macro. v1 -> v2: Wrong prefix on first patch. src/fw/pciinit.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 0ad548f..fd5dfb9 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -636,6 +636,36 @@ pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev, return entry; } +static int pci_bus_hotplug_support(struct pci_bus *bus) +{ + u8 pcie_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_EXP); + u8 shpc_cap; + + if (pcie_cap) { + u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf, + pcie_cap + PCI_EXP_FLAGS); + u8 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >> + (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1)); + u8 downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) || + (port_type == PCI_EXP_TYPE_ROOT_PORT); + /* + * PCI Express SPEC, 7.8.2: + * Slot Implemented – When Set, this bit indicates that the Link + * HwInit associated with this Port is connected to a slot (as + * compared to being connected to a system-integrated device or + * being disabled). + * This bit is valid for Downstream Ports. This bit is undefined + * for Upstream Ports. + */ + u16 slot_implemented = pcie_flags & PCI_EXP_FLAGS_SLOT; + + return downstream_port && slot_implemented; + } + + shpc_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC); + return !!shpc_cap; +} + static int pci_bios_check_devices(struct pci_bus *busses) { dprintf(1, "PCI: check devices\n"); @@ -678,7 +708,7 @@ static int pci_bios_check_devices(struct pci_bus *busses) continue; struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)]; int type; - u8 shpc_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_SHPC); + int hotplug_support = pci_bus_hotplug_support(s); for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align = (type == PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; @@ -687,7 +717,7 @@ static int pci_bios_check_devices(struct pci_bus *busses) if (pci_region_align(&s->r[type]) > align) align = pci_region_align(&s->r[type]); u64 sum = pci_region_sum(&s->r[type]); - if (!sum && shpc_cap) + if (!sum && hotplug_support) sum = align; /* reserve min size for hot-plug */ u64 size = ALIGN(sum, align); int is64 = pci_bios_bridge_region_is64(&s->r[type], -- 1.8.3.1

7 years, 10 months

expecting string instruction after `rep' with latest SeaBIOS

by Ian Campbell

Building the seabios defconfig on a 64-bit Debian Wheezy system I'm seeing: Compiling (16bit) out/romlayout.o src/romlayout.S: Assembler messages: src/romlayout.S:285: Error: expecting string instruction after `rep' make: *** [out/romlayout.o] Error 1 That line is: // Acquire lock and take ownership of shared stack 1: rep nop I've also checked the preprocessed version and the nop isn't being disappeared or anything like that. This is with 083ee297ef88d "ohci: Update usb command timeouts to use usb_xfer_time()". I don't see it with the rel-1.7.5 tag. git bisect has fingered 0673b7870063a ""smp: Replace QEMU SMP init assembler code with C; run only in 32bit mode.", which makes sense since it made those additions to romlayout.S Other than a compiler bug I can't think what might be going on. Debian Wheezy has gcc 4.7.2 and binutils 2.22. Ian.

7 years, 10 months

[PATCH] bootmenu: Skip wait for keypress with less than one item

by Paul Menzel

Date: Mon, 23 Jun 2014 22:24:23 +0200 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/boot.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/boot.c b/src/boot.c index 5837ad0..ed8f5e2 100644 --- a/src/boot.c +++ b/src/boot.c @@ -486,6 +486,10 @@ interactive_bootmenu(void) , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); } + if (maxmenu < 2) + printf("Autoselect only entry.\n") + return; + // Get key press for (;;) { scan_code = get_keystroke(1000); -- 2.0.0

7 years, 11 months

Re: [SeaBIOS] [PATCH 1/4] xhci: Update the times for usb command timeouts.

by Matt DeVillier

On 6/22/2014 5:04 AM, Kevin O'Connor wrote: > On Sat, Jun 21, 2014 at 01:24:24PM -0500, Matt DeVillier wrote: >> On 6/21/2014 1:22 PM, Kevin O'Connor wrote: >>> The above is fine. Can you also post 'lsusb -t' and 'lsusb -v' output >>> for the device? I'll take a look later tonight. >> does it need to be from the same SeaBIOS build? I'd imagine not >> since the device works in the OS either way. But if so I'll need to >> recompile/reflash first since I have a working one loaded now > No - the lsusb reports info on the device - it shouldn't matter what > version of seabios is in use. Can you post the full seabios log as > well? > > Please CC the seabios mailing list on the response. > > -Kevin Kevin, here's the cbmem snipped for the USB3 flash drive: SeaBIOS (version rel-1.7.5-6-g0fce84e-20140611-MattDevo) init usb XHCI init on dev 00:14.0: regs @ 0xe0700000, 13 ports, 32 slots, 32 byte contexts XHCI protocol USB 2.00, 9 ports (offset 1), def 3018 XHCI protocol USB 3.00, 4 ports (offset 10), def 1000 XHCI extcap 0xc1 @ e0708040 XHCI extcap 0xc0 @ e0708070 XHCI extcap 0x1 @ e0708460 XHCI extcap 0xa @ e0708480 configure_xhci: resetting configure_xhci: setup 16 scratch pad buffers xhci_hub_detect port #1: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #2: 0x000206e1, powered, pls 7, speed 1 [Full] xhci_hub_reset port #2: 0x000206e1, powered, pls 7, speed 1 [Full] XHCI port #2: 0x00200603, powered, enabled, pls 0, speed 1 [Full] set_address 0x000ef720 xhci_alloc_pipe: usbdev 0x7f664290, ring 0x7f6aeb00, slotid 0, epid 1 xhci_cmd_enable_slot: xhci_process_events: status change port #2 xhci_process_events: status change port #4 xhci_process_events: status change port #11 xhci_process_events: status change port #2 xhci_alloc_pipe: enable slot: got slotid 1 xhci_cmd_address_device: slotid 1 xhci_update_pipe: usbdev 0x7f664290, ring 0x7f6aeb00, slotid 1, epid 1 config_usb: 0x7f6aec20 device rev=0200 cls=00 sub=00 proto=00 size=8 xhci_update_pipe: usbdev 0x7f664290, ring 0x7f6aeb00, slotid 1, epid 1 usb_hid_setup 0x7f6aec20 xhci_alloc_pipe: usbdev 0x7f664290, ring 0x000ef400, slotid 0, epid 3 xhci_cmd_configure_endpoint: slotid 1, add 0x9, del 0x0 USB keyboard initialized xhci_hub_detect port #3: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #4: 0x000206e1, powered, pls 7, speed 1 [Full] xhci_hub_reset port #4: 0x000206e1, powered, pls 7, speed 1 [Full] XHCI port #4: 0x00200603, powered, enabled, pls 0, speed 1 [Full] set_address 0x000ef720 xhci_alloc_pipe: usbdev 0x7f664290, ring 0x7f6ae900, slotid 0, epid 1 xhci_cmd_enable_slot: xhci_process_events: status change port #4 xhci_alloc_pipe: enable slot: got slotid 2 xhci_cmd_address_device: slotid 2 xhci_update_pipe: usbdev 0x7f664290, ring 0x7f6ae900, slotid 2, epid 1 config_usb: 0x7f6aea20 device rev=0110 cls=e0 sub=01 proto=01 size=64 xhci_update_pipe: usbdev 0x7f664290, ring 0x7f6ae900, slotid 2, epid 1 xhci_update_pipe: reconf ctl endpoint pkt size: 8 -> 64 xhci_cmd_evaluate_context: slotid 2, add 0x2, del 0x0 xhci_hub_detect port #5: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #6: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #7: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #8: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #9: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #10: 0x000802a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #11: 0x00281203, powered, enabled, pls 0, speed 4 [Super] XHCI port #11: 0x00281203, powered, enabled, pls 0, speed 4 [Super] set_address 0x000ef720 xhci_alloc_pipe: usbdev 0x7f664290, ring 0x7f69de00, slotid 0, epid 1 xhci_cmd_enable_slot: xhci_alloc_pipe: enable slot: got slotid 3 xhci_cmd_address_device: slotid 3 xhci_update_pipe: usbdev 0x7f664290, ring 0x7f69de00, slotid 3, epid 1 config_usb: 0x7f69df20 device rev=0300 cls=00 sub=00 proto=00 size=512 xhci_update_pipe: usbdev 0x7f664290, ring 0x7f69de00, slotid 3, epid 1 xhci_alloc_pipe: usbdev 0x7f664290, ring 0x000ef200, slotid 0, epid 3 xhci_cmd_configure_endpoint: slotid 3, add 0x9, del 0x0 xhci_alloc_pipe: usbdev 0x7f664290, ring 0x000ef000, slotid 0, epid 4 xhci_cmd_configure_endpoint: slotid 3, add 0x11, del 0x0 Searching bootorder for: /pci@i0cf8/usb@14/storage@b/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@14/usb-*@b USB MSC vendor='UFD 3.0' product='Silicon-Power16G' rev='PMAP' type=0 removable=1 WARNING - Timeout at xhci_event_wait:394! xhci_send_bulk: bulk xfer failed (cc -1) USB transmission failed xhci_send_bulk: bulk xfer failed (cc 3) USB transmission failed Unable to configure USB MSC drive. Unable to configure USB MSC device. ... -Matt

7 years, 11 months

Re: [SeaBIOS] [PATCH 1/4] xhci: Update the times for usb command timeouts.

by Matt DeVillier

7 years, 11 months

[PATCH 0/4] Unify and fix USB command timeouts.

by Kevin O'Connor

The SeaBIOS USB drivers all have different timeouts for USB commands. The USB specification does specify maximum command times (section 9.2.6). In particular, it states that all commands are expected to complete within 5 seconds. This series unifies the command timeouts across the drivers. Generally, the timeout is increased to 5 seconds for all commands. This fixes an issue reported by some users of USB flash drives on XHCI controllers (the xhci controller had a 1 second bulk timeout). The control command timeouts are also increased to 5 seconds except for the set_address command. This is reduced to 150ms (spec caps device to 50ms) to prevent 5 second hangs should a port report a device that isn't actually there. Once the driver starts talking to a device it would be very unusual to timeout on a command, so there shouldn't be any problem with a limit of five seconds. -Kevin Kevin O'Connor (4): xhci: Update the times for usb command timeouts. ehci: Update usb command timeouts to use usb_xfer_time() uhci: Update usb command timeouts to use usb_xfer_time() ohci: Update usb command timeouts to use usb_xfer_time() src/hw/usb-ehci.c | 11 ++++++----- src/hw/usb-ohci.c | 7 +++---- src/hw/usb-uhci.c | 13 ++++++------- src/hw/usb-xhci.c | 4 ++-- src/hw/usb.c | 13 +++++++++++++ src/hw/usb.h | 5 +++++ 6 files changed, 35 insertions(+), 18 deletions(-) -- 1.9.3

7 years, 11 months

Re: [SeaBIOS] [PATCH 1/4] xhci: Update the times for usb command timeouts.

by Kevin O'Connor

On Sat, Jun 21, 2014 at 08:46:05PM +0200, Idwer Vollering wrote: > 2014-06-21 20:22 GMT+02:00 Kevin O'Connor <kevin(a)koconnor.net>: > > On Sat, Jun 21, 2014 at 01:15:25PM -0500, Matt DeVillier wrote: > >> On 6/21/2014 1:08 PM, Kevin O'Connor wrote: > (cut) > > I'm experiencing similar trouble booting off native XHCI hardware: > > SeaBIOS (version rel-1.7.5-20-g67fd42c-dirty-20140617_200600-ubuntu) > init usb > XHCI init on dev 00:10.0: regs @ 0xf0248000, 4 ports, 32 slots, 32 byte contexts > XHCI extcap 0x1 @ f0248500 > XHCI protocol USB 3.00, 2 ports (offset 1), def 0 > XHCI protocol USB 2.00, 2 ports (offset 3), def 0 > configure_xhci: resetting > xhci_hub_detect port #1: 0x000002a0, powered, pls 5, speed 0 [ - ] > xhci_hub_detect port #2: 0x000002a0, powered, pls 5, speed 0 [ - ] > xhci_hub_detect port #3: 0x000002a0, powered, pls 5, speed 0 [ - ] > xhci_hub_detect port #4: 0x000202e1, powered, pls 7, speed 0 [ - ] > xhci_hub_reset port #4: 0x000202e1, powered, pls 7, speed 0 [ - ] > XHCI port #4: 0x00200e03, powered, enabled, pls 0, speed 3 [High] > set_address 0x000ef720 > xhci_alloc_pipe: usbdev 0xbf0d37f0, ring 0xbf11fb00, slotid 0, epid 1 > xhci_cmd_enable_slot: > xhci_process_events: status change port #4 > xhci_process_events: status change port #2 > xhci_process_events: status change port #4 > xhci_alloc_pipe: enable slot: got slotid 1 > xhci_cmd_address_device: slotid 1 > WARNING - Timeout at xhci_event_wait:394! So, this looks different from Matt's report. What appears to be happening in the above is that the device shows up originally as a high speed device (see "[High]" above). However, when the set_address command is sent to it, it appears that the device effectively disconnects and then reconnects as a super speed device (see "change port #2" and "change port #4" above - port 2==port 4 - see ("offset 1" / "offset 3" above)). You can try increasing the xchi_event_wait timeout which fixes Matt's issue, but I think we tried this on your hardware before with no luck. SeaBIOS isn't coded to support new devices being attached dynamically, and this is really the limitation here. It's not so much an XHCI issue as it is a dynamic connection thing (SeaBIOS checks port 2, finds nothing, goes on to check port 4, finds a device there, that device goes away, a new device shows up on port 2, but SeaBIOS has already checked port 2 and wont check it again). It's possible to make this work in SeaBIOS, but it would require some restructuring of the USB code. Can you check if this happens to all super speed devices on your controller or just this device? Is the device bootable with the factory BIOS? I'm not sure if it's worthwhile to add lots of code if this is just limited to a single quirky device. -Kevin

7 years, 11 months

Re: [SeaBIOS] [PATCH 1/4] xhci: Update the times for usb command timeouts.

by Kevin O'Connor

7 years, 11 months

Re: [SeaBIOS] [PATCH 1/4] xhci: Update the times for usb command timeouts.

by Kevin O'Connor

On Sat, Jun 21, 2014 at 01:15:25PM -0500, Matt DeVillier wrote: > On 6/21/2014 1:08 PM, Kevin O'Connor wrote: > > On Sat, Jun 21, 2014 at 12:20:21PM -0500, Matt DeVillier wrote: > >> I still have issues with various USB sticks not being detected at > >> boot due to the xhci_event_wait() call in xhci_cmd_submit() which > >> still has a timeout of 1000ms (vs 5000 for the ones affected by this > >> patch). Manually setting it to 5000 fixes the issues with all the > >> USB flash devices I've tested (which had a problem at 1000ms) > > Thanks Matt. Can you post the SeaBIOS log with one of these devices? > > Can do - what would you like the logging level set to? Currently > have it set to 3, which produces the following: > > xhci_hub_reset port #2: 0x00020ae1, powered, pls 7, speed 2 [Low] > XHCI port #2: 0x00200a03, powered, enabled, pls 0, speed 2 [Low] > set_address 0x000ef720 > xhci_alloc_pipe: usbdev 0x7f7378d0, ring 0x7f781b00, slotid 0, epid 1 > xhci_cmd_enable_slot: > xhci_process_events: status change port #2 > xhci_process_events: status change port #3 > xhci_process_events: status change port #4 > xhci_process_events: status change port #2 > xhci_alloc_pipe: enable slot: got slotid 1 > xhci_cmd_address_device: slotid 1 > xhci_update_pipe: usbdev 0x7f7378d0, ring 0x7f781b00, slotid 1, epid 1 > config_usb: 0x7f781c20 > device rev=0110 cls=00 sub=00 proto=00 size=8 > xhci_update_pipe: usbdev 0x7f7378d0, ring 0x7f781b00, slotid 1, epid 1 > WARNING - Timeout at xhci_event_wait:394! > xhci_control: control xfer failed (cc -1) The above is fine. Can you also post 'lsusb -t' and 'lsusb -v' output for the device? I'll take a look later tonight. -Kevin

7 years, 11 months

[Qemu-devel] [PATCH] hw/pci: reserve IO and mem for pci express downstream ports with no devices attached

by Marcel Apfelbaum

commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830 hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached introduced support for hot-plugging devices behind pci-2-pci bridges. Extend hotplug support also for pci express downstream ports. Signed-off-by: Marcel Apfelbaum <marcel.a(a)redhat.com> --- src/fw/pciinit.c | 23 +++++++++++++++++++++-- src/hw/pci_regs.h | 2 ++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 0ad548f..edb3fe9 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -636,6 +636,25 @@ pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev, return entry; } +static int pci_bus_hotplug_support(struct pci_bus *bus) +{ + u8 shpc_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC); + u8 pcie_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_EXP); + int downstream_port = 0; + int slot_implemented = 0; + + if (pcie_cap) { + u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf, + pcie_cap + PCI_EXP_FLAGS); + u16 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >> + PCI_EXP_FLAGS_TYPE_SHIFT) & 0xf; + downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) || + (port_type == PCI_EXP_TYPE_ROOT_PORT); + slot_implemented = !!(pcie_flags & PCI_EXP_FLAGS_SLOT); + } + return shpc_cap || (downstream_port && slot_implemented); +} + static int pci_bios_check_devices(struct pci_bus *busses) { dprintf(1, "PCI: check devices\n"); @@ -678,7 +697,7 @@ static int pci_bios_check_devices(struct pci_bus *busses) continue; struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)]; int type; - u8 shpc_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_SHPC); + int hotplug_support = pci_bus_hotplug_support(s); for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align = (type == PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; @@ -687,7 +706,7 @@ static int pci_bios_check_devices(struct pci_bus *busses) if (pci_region_align(&s->r[type]) > align) align = pci_region_align(&s->r[type]); u64 sum = pci_region_sum(&s->r[type]); - if (!sum && shpc_cap) + if (!sum && hotplug_support) sum = align; /* reserve min size for hot-plug */ u64 size = ALIGN(sum, align); int is64 = pci_bios_bridge_region_is64(&s->r[type], diff --git a/src/hw/pci_regs.h b/src/hw/pci_regs.h index e5effd4..6a71569 100644 --- a/src/hw/pci_regs.h +++ b/src/hw/pci_regs.h @@ -426,6 +426,8 @@ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ +#define PCI_EXP_FLAGS_TYPE_SHIFT 4 + /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) -- 1.8.3.1

7 years, 11 months

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SeaBIOS June 2014