May 2020 - SeaBIOS - mail.coreboot.org

[PATCH v3 0/5] Make seabios linkable with lld

by Fangrui Song

This patch series make seabios linkable with lld. This is beneficial for FreeBSD ports as well https://svnweb.freebsd.org/ports/head/misc/seabios/Makefile as they can drop an LLD_UNSAFE As a maintainer of lld ELF, I have triaged numerous pieces of software. seabios is the only one making use of This drops the only instance https://sourceware.org/bugzilla/show_bug.cgi?id=12726 1, 2, 3 and 4 are really independent and can be applied in arbitrary order. 5 depends on 4. I originally combined 4 and 5 and that was why I don't think a patch series made sense. Fangrui Song (5): romlayout.S: Add missing SHF_ALLOC flag to .fixedaddr.\addr Make rom16.o linkable with lld Makefile: Change ET_EXEC to ET_REL so that lld can link bios.bin.elf romlayout32flag.lds: Use `. +=` instead of `. =` test-build.sh: Delete unneeded LD capability test Makefile | 4 ++++ scripts/layoutrom.py | 13 ++++++++++--- scripts/test-build.sh | 42 +----------------------------------------- src/romlayout.S | 2 +- 4 files changed, 16 insertions(+), 45 deletions(-) -- 2.26.0.292.g33ef6b2f38-goog

1 week, 6 days

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Boot order?

by Mogens Jensen

First posted this question to coreboot mailing list, but on second thought, I think this is the right place. I have experimentet with coreboot on my CompuLab Intense PC (Ivy Bridge) for some time, and I think everything is working now, with Intel ME disabled. Although, I have some troubles with boot selection. I'm currently running coreboot [4cea00a64] with default SeaBIOS payload [v1.13.0] and a bootorder file. The boot device search order is this: 1. USB 2.0 device 2. USB 3.0 device 3. SATA devices (in order: 2.5″ internal, mSATA, eSATA, FACE module) During testing I have been running the system from a USB 3.0 flash disk. This worked as expected and system would automatically select this device during boot/reboot. I then wanted to use the internal 2.5" SATA disk, so I installed an OS and confirmed it working by manually selecting the SATA disk in boot menu. I then removed boot sector from flash disk, reboot and expected that the system would now automatically boot from internal SATA disk, but this happened instead: === Booting from Hard Disk... Boot failed: not a bootable disk Booting from Floppy... Boot failed: not a bootable disk No bootable device. Retrying in 60 seconds. === Not sure what is going on with "Floppy". No such thing exists on the system. If I remove flash disk from USB port before power on, the system will boot correctly from internal SATA disk. Is this correct behaviour? I would expect that it should not matter that flash disk is inserted in USB port, as long as no boot sector is present on the device. If this is NOT correct behaviour, then what could be the problem here? Thanks in advance. Regards, Mogens Jensen

1 month, 2 weeks

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[PATCH] pci: fix mmconfig support

by Gerd Hoffmann

The MODESEGMENT condition is backwards, with the effect that mmconfig mode is not used to configure pci bars during POST. Oops. Fix it. The only real mode pci config space access seems to come from the ipxe option rom initialiation. Which happens to work via mmconfig because it runs in big real mode so this went unnoticed ... Fixes: 6a3b59ab9c7d ("pci: add mmconfig support") Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/hw/pci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index d9dbf313965c..3df1dae41d2b 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -28,7 +28,7 @@ static u32 ioconfig_cmd(u16 bdf, u32 addr) void pci_config_writel(u16 bdf, u32 addr, u32 val) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { writel(mmconfig_addr(bdf, addr), val); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -38,7 +38,7 @@ void pci_config_writel(u16 bdf, u32 addr, u32 val) void pci_config_writew(u16 bdf, u32 addr, u16 val) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { writew(mmconfig_addr(bdf, addr), val); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -48,7 +48,7 @@ void pci_config_writew(u16 bdf, u32 addr, u16 val) void pci_config_writeb(u16 bdf, u32 addr, u8 val) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { writeb(mmconfig_addr(bdf, addr), val); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -58,7 +58,7 @@ void pci_config_writeb(u16 bdf, u32 addr, u8 val) u32 pci_config_readl(u16 bdf, u32 addr) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { return readl(mmconfig_addr(bdf, addr)); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -68,7 +68,7 @@ u32 pci_config_readl(u16 bdf, u32 addr) u16 pci_config_readw(u16 bdf, u32 addr) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { return readw(mmconfig_addr(bdf, addr)); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -78,7 +78,7 @@ u16 pci_config_readw(u16 bdf, u32 addr) u8 pci_config_readb(u16 bdf, u32 addr) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { return readb(mmconfig_addr(bdf, addr)); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); -- 2.18.4

1 month, 2 weeks

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[PATCH] boot: Fix logic for boot menu display

by Matt DeVillier

Commit c61193d3 [boot: Extend `etc/show-boot-menu`...] changed the logic surrounding the use of show_boot_menu incorrectly, leading the boot menu to be skipped by default with no way to override. Correct the logic error so that show_boot_menu works as documented. Test: build/boot SeaBIOS, verify boot menu option shown by default. Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/boot.c b/src/boot.c index 994b592f..58c13add 100644 --- a/src/boot.c +++ b/src/boot.c @@ -697,7 +697,7 @@ interactive_bootmenu(void) // XXX - show available drives? u64 show_boot_menu = romfile_loadint("etc/show-boot-menu", 1); - if (! CONFIG_BOOTMENU || show_boot_menu != 0) + if (! CONFIG_BOOTMENU || show_boot_menu == 0) return; // skip menu if only one boot device and no TPM -- 2.25.1

1 month, 2 weeks

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[PATCH] ps2: Disable keyboard and mouse before flushing the queue

by Paul Menzel

From: Stefan Reinauer <reinauer(a)chromium.org> If SeaBIOS is run as a payload via coreboot (and presumably as a CSM), then it's possible the keyboard or mouse will still be enabled. This can lead to data being queued even after the flush function attempts to clear the queue. Disabling the keyboard/mouse prior to flushing is pretty standard in DOS programming so it's not surprising that it's needed here. I believe this problem manifests with the Chromebook Pixel. People have reported that sometimes the 'ESC to Select Boot Devices' doesn't work. I can reproduce this faithfully by holding 'Ctrl-L' in the firmware screen during SeaBIOS initialization. I can't test this fix on an actual Pixel because I don't know how to update SeaBIOS but I have tested the patch under QEMU. BUG=none TEST=Boot into SeaBIOS, press ESC, see it working. Change-Id: I4e74a559e86539730f4fda1d429612c759da16ee Signed-off-by: Anthony Liguori <aliguori(a)us.ibm.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49212 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Cc: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/hw/ps2port.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hw/ps2port.c b/src/hw/ps2port.c index 9b099e8..c99ea54 100644 --- a/src/hw/ps2port.c +++ b/src/hw/ps2port.c @@ -58,6 +58,12 @@ static int i8042_flush(void) { dprintf(7, "i8042_flush\n"); + + /* Disable the keyboard and mouse to prevent additional data from + * being queued. */ + outb(0xad, PORT_PS2_STATUS); + outb(0xa7, PORT_PS2_STATUS); + int i; for (i=0; i<I8042_BUFFER_SIZE; i++) { u8 status = inb(PORT_PS2_STATUS); -- 2.27.0.rc0

1 month, 2 weeks

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There is still a kind of PS/2 keyboard issue.

by Keith Hui

Paul's recent dialogue about PS/2 keyboard in SeaBIOS reminds me that I am also suffering PS/2 keyboard issues on three mainboards that I am having with coreboot/SeaBIOS combo and need to ask here. The boards are P2B-LS, P3B-F and P8Z77-M all from Asus. The last one I'm doing a new port that is currently under review at coreboot. On those boards I almost never got PS/2 keyboard to work before my Linux kernel (4.4.14, soon 5.4.x) finishes booting and I get login prompt. Only on P3B-F it would work intermittently earlier. USB keyboards always worked right away. The PS/2 Keyboards I'm using are two pieces of classic: IBM Model M and the first Microsoft Natural. I am using SeaBIOS 1.13.0 which already carries commit dbf9dd27f which described and should have fixed the issue I'm having. I also tried tweaking with the PS/2 keyboard "spinup" timeout from 0 to 500 to 2500 to 3500ms with no noticeable difference. Now I'm stumped. Thanks Keith

1 month, 2 weeks

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[PATCH] ps2port: adjust init routine to fix PS/2 keyboard issues

by Paul Menzel

From: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri, 12 Aug 2016 14:21:58 -0500 PS/2 keyboards on Chromebooks with upstream coreboot + SeaBIOS often fail to init properly / register keystrokes. Modify ps2port init to match that of TianoCore, which doesn't have said issues. Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- Upstream from https://github.com/MrChromebox/SeaBIOS/ src/hw/ps2port.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/src/hw/ps2port.c b/src/hw/ps2port.c index 88b1059..2c334c0 100644 --- a/src/hw/ps2port.c +++ b/src/hw/ps2port.c @@ -465,6 +465,14 @@ ps2_keyboard_setup(void *data) if (ret) return; + // Disable KB/mouse interfaces + ret = i8042_command(I8042_CMD_KBD_DISABLE, NULL); + if (ret) + return; + ret = i8042_command(I8042_CMD_AUX_DISABLE, NULL); + if (ret) + return; + // Controller self-test. u8 param[2]; ret = i8042_command(I8042_CMD_CTL_TEST, param); @@ -475,6 +483,11 @@ ps2_keyboard_setup(void *data) return; } + // KB write CMD + ret = i8042_command(I8042_CMD_CTL_WCTR, NULL); + if (ret) + return; + // Controller keyboard test. ret = i8042_command(I8042_CMD_KBD_TEST, param); if (ret) @@ -505,11 +518,6 @@ ps2_keyboard_setup(void *data) return; } - /* Disable keyboard */ - ret = ps2_kbd_command(ATKBD_CMD_RESET_DIS, NULL); - if (ret) - return; - // Set scancode command (mode 2) param[0] = 0x02; ret = ps2_kbd_command(ATKBD_CMD_SSCANSET, param); -- 2.25.1

1 month, 2 weeks

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[PATCH] cdrom: Demote `scsi_is_ready` return print to debug level

by Paul Menzel

Printing the return value of `scsi_is_ready()` is a debug message, so change the log level from 1 to 5. Booting from DVD/CD... Device reports MEDIUM NOT PRESENT scsi_is_ready returned -1 Boot failed: Could not read from CDROM (code 0003) Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/cdrom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cdrom.c b/src/cdrom.c index 577d69d..a77671a 100644 --- a/src/cdrom.c +++ b/src/cdrom.c @@ -142,7 +142,7 @@ cdrom_boot(struct drive_s *drive) int ret = scsi_is_ready(&dop); if (ret) - dprintf(1, "scsi_is_ready returned %d\n", ret); + dprintf(5, "scsi_is_ready returned %d\n", ret); // Read the Boot Record Volume Descriptor u8 buffer[CDROM_SECTOR_SIZE]; -- 2.26.2

1 month, 2 weeks

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[PATCH v2 1/3] boot: Extend `etc/show-boot-menu` to configure skipping boot menu with only one device

by Paul Menzel

Concerns were raised, that skipping the boot menu, if only one device is present, might make debugging issues more difficult. So, extend the current runtime configuration option `etc/show-boot-menu` to enable this feature by setting it to 2. Fixes: 29ee1fb8 ("Skip boot menu and timeout with only one boot device") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- docs/Runtime_config.md | 2 +- src/boot.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 6747e2a..5795382 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -173,7 +173,7 @@ There are several additional configuration options available in the | Filename | Description |---------------------|--------------------------------------------------- -| show-boot-menu | Controls the display of the boot menu. Set to 0 to disable the boot menu. +| show-boot-menu | Controls the display of the boot menu. Valid values are 0: Disable the boot menu, 1: Display boot menu unconditionally, 2: Skip boot menu if only one device is present. The default is 1. | boot-menu-message | Customize the text boot menu message. Normally, when in text mode SeaBIOS will report the string "\\nPress ESC for boot menu.\\n\\n". This field allows the string to be changed. (This is a string field, and is added as a file containing the raw string.) | boot-menu-key | Controls which key activates the boot menu. The value stored is the DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set, be sure to also customize the **boot-menu-message** field above. | boot-menu-wait | Amount of time (in milliseconds) to wait at the boot menu prompt before selecting the default boot. diff --git a/src/boot.c b/src/boot.c index cc87b1d..a395347 100644 --- a/src/boot.c +++ b/src/boot.c @@ -685,12 +685,13 @@ void interactive_bootmenu(void) { // XXX - show available drives? + u64 show_boot_menu = romfile_loadint("etc/show-boot-menu", 1); - if (! CONFIG_BOOTMENU || !romfile_loadint("etc/show-boot-menu", 1)) + if (! CONFIG_BOOTMENU || show_boot_menu != 0) return; // skip menu if only one boot device and no TPM - if ((NULL == BootList.first->next) && !tpm_can_show_menu()) { + if ((show_boot_menu == 2) && (NULL == BootList.first->next) && !tpm_can_show_menu()) { printf("\n"); return; } -- 2.26.2

1 month, 2 weeks

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[PATCH] rewrap Makefile lines.

by Gerd Hoffmann

Rewrap SRCBOTH and SRC32FLAT variables in Makefile to keep line length below 80 chars. No functional change. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- Makefile | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/Makefile b/Makefile index efb3b9361270..c20be15783cf 100644 --- a/Makefile +++ b/Makefile @@ -28,22 +28,24 @@ IASL:=iasl LD32BIT_FLAG:=-melf_i386 # Source files -SRCBOTH=misc.c stacks.c output.c string.c block.c cdrom.c disk.c mouse.c kbd.c \ - system.c serial.c sercon.c clock.c resume.c pnpbios.c vgahooks.c pcibios.c \ - apm.c cp437.c \ - hw/pci.c hw/timer.c hw/rtc.c hw/dma.c hw/pic.c hw/ps2port.c hw/serialio.c \ - hw/usb.c hw/usb-uhci.c hw/usb-ohci.c hw/usb-ehci.c \ - hw/usb-hid.c hw/usb-msc.c hw/usb-uas.c \ - hw/blockcmd.c hw/floppy.c hw/ata.c hw/ramdisk.c \ - hw/lsi-scsi.c hw/esp-scsi.c hw/megasas.c hw/mpt-scsi.c +SRCBOTH=misc.c stacks.c output.c string.c block.c cdrom.c disk.c \ + mouse.c kbd.c system.c serial.c sercon.c clock.c resume.c \ + pnpbios.c vgahooks.c pcibios.c apm.c cp437.c hw/pci.c hw/timer.c \ + hw/rtc.c hw/dma.c hw/pic.c hw/ps2port.c hw/serialio.c hw/usb.c \ + hw/usb-uhci.c hw/usb-ohci.c hw/usb-ehci.c hw/usb-hid.c \ + hw/usb-msc.c hw/usb-uas.c hw/blockcmd.c hw/floppy.c hw/ata.c \ + hw/ramdisk.c hw/lsi-scsi.c hw/esp-scsi.c hw/megasas.c \ + hw/mpt-scsi.c SRC16=$(SRCBOTH) -SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c optionroms.c \ - pmm.c font.c boot.c bootsplash.c jpeg.c bmp.c tcgbios.c sha1.c \ - hw/pcidevice.c hw/ahci.c hw/pvscsi.c hw/usb-xhci.c hw/usb-hub.c hw/sdcard.c \ - fw/coreboot.c fw/lzmadecode.c fw/multiboot.c fw/csm.c fw/biostables.c \ - fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c fw/xen.c \ - fw/acpi.c fw/mptable.c fw/pirtable.c fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c \ - hw/virtio-ring.c hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ +SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c \ + optionroms.c pmm.c font.c boot.c bootsplash.c jpeg.c bmp.c \ + tcgbios.c sha1.c hw/pcidevice.c hw/ahci.c hw/pvscsi.c \ + hw/usb-xhci.c hw/usb-hub.c hw/sdcard.c fw/coreboot.c \ + fw/lzmadecode.c fw/multiboot.c fw/csm.c fw/biostables.c \ + fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c \ + fw/mtrr.c fw/xen.c fw/acpi.c fw/mptable.c fw/pirtable.c \ + fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c hw/virtio-ring.c \ + hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ hw/tpm_drivers.c hw/nvme.c SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c DIRS=src src/hw src/fw vgasrc -- 2.18.4

1 month, 3 weeks

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SeaBIOS May 2020