April 2013 - SeaBIOS - mail.coreboot.org

[PATCH] tools/kconfig/{m,n}conf.c: Fix typo »This interface let*s*«

by Paul Menzel

Date: Mon, 4 Mar 2013 12:56:56 +0100 When Kconfig was introduced in SeaBIOS with commit a4c5daf0e2545361fadcad3015e10f8b23e53926 Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Mon Jan 24 22:13:58 2011 -0500 Initial commit of Kconfig build tool. this typo was copied from Kconfig in Linux v2.6.38-rc2. In the meantime Linux commit »kconfig: nconf: rewrite help texts« (0b616500) [1] rewrote the texts for `nconf.c` – which might be ported too to SeaBIOS – and the typo was fixed there. But it is still present in `mconf.c` as of Linux 3.8. [1] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id... --- tools/kconfig/mconf.c | 2 +- tools/kconfig/nconf.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/kconfig/mconf.c b/tools/kconfig/mconf.c index d433c7a..2a24c42 100644 --- a/tools/kconfig/mconf.c +++ b/tools/kconfig/mconf.c @@ -25,7 +25,7 @@ static const char mconf_readme[] = N_( "Overview\n" "--------\n" -"This interface let you select features and parameters for the build.\n" +"This interface lets you select features and parameters for the build.\n" "Features can either be built-in, modularized, or ignored. Parameters\n" "must be entered in as decimal or hexadecimal numbers or text.\n" "\n" diff --git a/tools/kconfig/nconf.c b/tools/kconfig/nconf.c index db56377..bb797c9 100644 --- a/tools/kconfig/nconf.c +++ b/tools/kconfig/nconf.c @@ -15,7 +15,7 @@ static const char nconf_readme[] = N_( "Overview\n" "--------\n" -"This interface let you select features and parameters for the build.\n" +"This interface lets you select features and parameters for the build.\n" "Features can either be built-in, modularized, or ignored. Parameters\n" "must be entered in as decimal or hexadecimal numbers or text.\n" "\n" -- 1.7.10.4

6 years, 2 months

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[PATCHv2] pci: load memory window setup from host

by Michael S. Tsirkin

Load memory window setup for pci from host. This makes it possible for host to make sure setup matches hardware exactly: especially important for when ACPI tables are loaded from host. This will also make it easier to add more chipsets down the road. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- Changes from v1: - fix bug in 64 bit range check - address Kevin's comments: move file load into pciinit.c dont reorder initialization sizeof style fix src/pciinit.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 75 insertions(+), 16 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index bb9355f..a4a5bf5 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -13,6 +13,7 @@ #include "config.h" // CONFIG_* #include "memmap.h" // add_e820 #include "paravirt.h" // RamSize +#include "byteorder.h" // le64_to_cpu #include "dev-q35.h" /* PM Timer ticks per second (HZ) */ @@ -61,6 +62,13 @@ struct pci_bus { struct pci_device *bus_dev; }; +struct pci_mem { + u64 start32; + u64 end32; + u64 start64; + u64 end64; +}; + static u32 pci_bar(struct pci_device *pci, int region_num) { if (region_num != PCI_ROM_SLOT) { @@ -361,6 +369,8 @@ static void pci_enable_default_vga(void) void i440fx_mem_addr_setup(struct pci_device *dev, void *arg) { + if (arg) + /* use supplied memory */; if (RamSize <= 0x80000000) pcimem_start = 0x80000000; else if (RamSize <= 0xc0000000) @@ -383,8 +393,9 @@ void mch_mem_addr_setup(struct pci_device *dev, void *arg) pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower); add_e820(addr, size, E820_RESERVED); - /* setup pci i/o window (above mmconfig) */ - pcimem_start = addr + size; + /* unless done already, setup pci i/o window (above mmconfig) */ + if (!arg) + pcimem_start = addr + size; pci_slot_get_irq = mch_pci_slot_get_irq; } @@ -397,11 +408,11 @@ static const struct pci_device_id pci_platform_tbl[] = { PCI_DEVICE_END }; -static void pci_bios_init_platform(void) +static void pci_bios_init_platform(struct pci_mem *mem) { struct pci_device *pci; foreachpci(pci) { - pci_init_device(pci_platform_tbl, pci, NULL); + pci_init_device(pci_platform_tbl, pci, mem); } } @@ -762,10 +773,14 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) } } -static void pci_bios_map_devices(struct pci_bus *busses) +static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem) { if (pci_bios_init_root_regions(busses)) { struct pci_region r64_mem, r64_pref; + + if (mem && mem->start64 >= mem->end64) + panic("PCI: out of 32bit address space\n"); + r64_mem.list = NULL; r64_pref.list = NULL; pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM], @@ -781,14 +796,27 @@ static void pci_bios_map_devices(struct pci_bus *busses) u64 align_mem = pci_region_align(&r64_mem); u64 align_pref = pci_region_align(&r64_pref); - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); - r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); - pcimem64_start = r64_mem.base; - pcimem64_end = r64_pref.base + sum_pref; + if (mem) { + /* + * Non prefetcheable memory at start of the window, + * prefetcheable memory at the end. + * This way OS has the maximum flexibility for + * allocating the rest of the memory. + */ + r64_mem.base = ALIGN(mem->start64, align_mem); + r64_pref.base = ALIGN_DOWN(mem->end64 - sum_pref + 1, align_pref); + if (sum_pref && r64_pref.base < r64_mem.base + sum_mem) + panic("PCI: out of 64bit address space\n"); + } else { + r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); + r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); + pcimem64_start = r64_mem.base; + pcimem64_end = r64_pref.base + sum_pref; + } pci_region_map_entries(busses, &r64_mem); pci_region_map_entries(busses, &r64_pref); - } else { + } else if (!mem) { // no bars mapped high -> drop 64bit window (see dsdt) pcimem64_start = 0; } @@ -801,11 +829,28 @@ static void pci_bios_map_devices(struct pci_bus *busses) } } +static +struct pci_mem *pci_mem_get(void) +{ + int psize; + struct pci_mem *mem = romfile_loadfile("etc/pci-info", &psize); + if (!mem) + return NULL; + if (psize < sizeof(*mem)) { + free(mem); + return NULL; + } + mem->start32 = le64_to_cpu(mem->start32); + mem->end32 = le64_to_cpu(mem->end32); + mem->start64 = le64_to_cpu(mem->start64); + mem->end64 = le64_to_cpu(mem->end64); + return mem; +} + /**************************************************************** * Main setup code ****************************************************************/ - void pci_setup(void) { @@ -823,25 +868,39 @@ pci_setup(void) dprintf(1, "=== PCI device probing ===\n"); pci_probe_devices(); - pcimem_start = RamSize; - pci_bios_init_platform(); + struct pci_mem *mem = pci_mem_get(); + + if (mem) { + pcimem_start = mem->start32; + pcimem_end = mem->end32; + pcimem64_start = mem->start64; + pcimem64_end = mem->end64; + } else { + pcimem_start = RamSize; + } + + pci_bios_init_platform(mem); dprintf(1, "=== PCI new allocation pass #1 ===\n"); struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1)); if (!busses) { warn_noalloc(); - return; + goto done; } memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1)); if (pci_bios_check_devices(busses)) - return; + goto done; dprintf(1, "=== PCI new allocation pass #2 ===\n"); - pci_bios_map_devices(busses); + pci_bios_map_devices(busses, mem); pci_bios_init_devices(); free(busses); pci_enable_default_vga(); + +done: + if (mem) + free(mem); } -- MST

6 years, 4 months

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[PATCH v2 00/19] SeaBIOS as Compatibility Support Module for UEFI/OVMF

by David Woodhouse

Changes from v1: - Make CONFIG_CSM a top-level build target in parallel with COREBOOT/QEMU. - More Kconfig cleanup. - Add generic find_pmtimer() function to find the pmtimer from ACPI tables. - Make Xen and coreboot builds both use find_pmtimer(). - Merge E820 table one entry at a time instead of wholesale copy. - Add pic_save_mask() and pic_restore_mask() functions. - Less intrusive size reduction for handle_post(). - Various other cleanups. -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

6 years, 5 months

6
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seabios for qemu 1.5

by Gerd Hoffmann

Hi, > b44a7be17bdd270ea029a8e2ec0c2e80c6cd0444 virtio-scsi: Pack struct virtio_scsi_{req_cmd,resp_cmd} > 5a7730db57ab0715223421e65b54fb50d6fefe5c virtio-scsi: Set _DRIVER_OK flag before scsi target scanning > Anthony + Gerd, can we expect an rev to pc-bios/bios.bin soon to pick up > these seabios changes for vhost-scsi..? I don't feel like placing a seabios git snapshot into qemu. I think we should just cherry-pick everything we need for qemu 1.5 into the 1.7.2-stable branch, roll out a 1.7.2.2 release and put that into qemu 1.5. So, what will be needed? (1) The two commits listed above. (2) The patch for the pvpanic device (assuming it gets merged for 1.5). Anything else? Hard freeze for qemu 1.5 is next Wednesday. cheers, Gerd PS: For qemu 1.6 (which will hopefully include the acpi table reorganization) we will need a new release from the master branch and thus a bit more careful release planning.

6 years, 6 months

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[PATCH v17] Add pvpanic device driver

by Hu Tao

pvpanic device is used to notify host(qemu) when guest panic happens. Signed-off-by: Paolo Bonzini <pbonzini(a)redhat.com> Signed-off-by: Hu Tao <hutao(a)cn.fujitsu.com> --- No change from v16. qemu patches at: http://lists.nongnu.org/archive/html/qemu-devel/2013-04/msg01028.html src/acpi.c | 3 +++ src/ssdt-misc.dsl | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/src/acpi.c b/src/acpi.c index bc4d8ea..fe504f0 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -534,6 +534,9 @@ build_ssdt(void) ssdt_ptr[acpi_pci64_valid[0]] = 0; } + int pvpanic_port = romfile_loadint("etc/pvpanic-port", 0x0); + *(u16 *)(ssdt_ptr + *ssdt_isa_pest) = pvpanic_port; + ssdt_ptr += sizeof(ssdp_misc_aml); // build Scope(_SB_) header diff --git a/src/ssdt-misc.dsl b/src/ssdt-misc.dsl index 679422b..acc850e 100644 --- a/src/ssdt-misc.dsl +++ b/src/ssdt-misc.dsl @@ -55,4 +55,50 @@ DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1) Zero /* reserved */ }) } + + External(\_SB.PCI0, DeviceObj) + External(\_SB.PCI0.ISA, DeviceObj) + + Scope(\_SB.PCI0.ISA) { + Device(PEVT) { + Name(_HID, "QEMU0001") + /* PEST will be patched to be Zero if no such device */ + ACPI_EXTRACT_NAME_WORD_CONST ssdt_isa_pest + Name(PEST, 0xFFFF) + OperationRegion(PEOR, SystemIO, PEST, 0x01) + Field(PEOR, ByteAcc, NoLock, Preserve) { + PEPT, 8, + } + + Method(_STA, 0, NotSerialized) { + Store(PEST, Local0) + If (LEqual(Local0, Zero)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + + Method(RDPT, 0, NotSerialized) { + Store(PEPT, Local0) + Return (Local0) + } + + Method(WRPT, 1, NotSerialized) { + Store(Arg0, PEPT) + } + + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00, 0x00, 0x01, 0x01, IO) + }) + + CreateWordField(_CRS, IO._MIN, IOMN) + CreateWordField(_CRS, IO._MAX, IOMX) + + Method(_INI, 0, NotSerialized) { + Store(PEST, IOMN) + Store(PEST, IOMX) + } + } + } } -- 1.8.1.4

6 years, 6 months

5
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[PATCH RFC 0/3] seabios: move acpi table formatting out of bios

by Michael S. Tsirkin

Untested yet, but I thought I'd share the BIOS bits so we can agree on direction. In particular check out ROM sizes: - Before patchset with DSDT enabled Total size: 127880 Fixed: 59060 Free: 3192 (used 97.6% of 128KiB rom) - Before patchset with DSDT disabled Total size: 122844 Fixed: 58884 Free: 8228 (used 93.7% of 128KiB rom) - After patchset: Total size: 128776 Fixed: 59100 Free: 2296 (used 98.2% of 128KiB rom) - Legacy disabled at build time: Total size: 119836 Fixed: 58996 Free: 11236 (used 91.4% of 128KiB rom) As can be seen from this, most size savings come from dropping DSDT, but we do save a bit by removing other tables. Of course the real reason to move tables to QEMU is so that ACPI can better match hardware. This patchset adds an option to move all code for formatting acpi tables out of BIOS. With this, QEMU has full control over the table layout. All tables are loaded from the new "/etc/acpi/" directory. Any entries in this directory cause BIOS to disable ACPI table generation completely. A generic linker script, controlled by QEMU, is loaded from "/etc/linker-script". It is used to patch in table pointers and checksums. BIOS still has limited ability to parse the tables, for the following purposes: - locate resume vector - allocate RSDP in FSEG - allocate FACS at an aligned address -- MST Michael S. Tsirkin (3): linker: utility to patch in-memory ROM files acpi: load and link tables from /etc/acpi/ acpi: add an option to disable builtin tables Makefile | 2 +- src/Kconfig | 12 +++++++- src/acpi.c | 67 +++++++++++++++++++++++++++++++++++++++++++- src/linker.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/linker.h | 50 +++++++++++++++++++++++++++++++++ src/util.h | 1 + 6 files changed, 219 insertions(+), 3 deletions(-) create mode 100644 src/linker.c create mode 100644 src/linker.h -- MST

6 years, 7 months

4
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[PATCH 0/2] accept MADT over fw_cfg

by Laszlo Ersek

The first patch cleans up some field assignments in build_madt(). The second one handles the case when MADT is provided by qemu over fw_cfg. I'll soon post the qemu-side series as well. I cross-tested {patched, unpatched} qemu with {patched, unpatched} seabios. Inside a RHEL-6 guest I dumped the RSDT, DSDT, and APIC (MADT) in all four cases, and compared the results. Patched qemu with unpatched seabios don't play nicely together (two APIC (MADT) tables present). Otherwise everything seemed fine to me. The CPU topology was set with -smp 3,maxcpus=16,sockets=2,cores=4,threads=2 The table dumps / disassemblies are too big to include here, please find them at <http://people.redhat.com/~lersek/acpi_move/madt_tests.tar.gz>. Laszlo Ersek (2): build_madt(): "fix" intsrcovr->{gsi,flags} and local_nmi->flags byte order accept MADT over fw_cfg src/acpi.c | 31 +++++++++++++++++++++++-------- 1 files changed, 23 insertions(+), 8 deletions(-)

6 years, 7 months

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[PATCH] acpi: minor clean-up of 64 bit window logic

by Michael S. Tsirkin

Make 64 bit window detection logic a bit cleaner: don't hardcode 0 address as invalid, instead check start < end. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- src/acpi.c | 2 +- src/pciinit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index b03b2ba..1037093 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -355,7 +355,7 @@ build_ssdt(void) // store pci io windows *(u32*)&ssdt_ptr[acpi_pci32_start[0]] = cpu_to_le32(pcimem_start); *(u32*)&ssdt_ptr[acpi_pci32_end[0]] = cpu_to_le32(pcimem_end - 1); - if (pcimem64_start) { + if (pcimem64_start < pcimem64_end) { ssdt_ptr[acpi_pci64_valid[0]] = 1; *(u64*)&ssdt_ptr[acpi_pci64_start[0]] = cpu_to_le64(pcimem64_start); *(u64*)&ssdt_ptr[acpi_pci64_end[0]] = cpu_to_le64(pcimem64_end - 1); diff --git a/src/pciinit.c b/src/pciinit.c index a4a5bf5..fdf1362 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -818,7 +818,7 @@ static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem) pci_region_map_entries(busses, &r64_pref); } else if (!mem) { // no bars mapped high -> drop 64bit window (see dsdt) - pcimem64_start = 0; + pcimem64_end = pcimem64_start = 0; } // Map regions on each device. int bus; -- MST

6 years, 7 months

1
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unaligned option rom

by Michael S. Tsirkin

Each time I boot seabios built with debug enabled, I see this on serial console: Scan for VGA option rom WARNING! Found unaligned PCI rom (vd=1013:00b8) Is this a bogus warning? -- MST

6 years, 7 months

2
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Re: [SeaBIOS] [PATCH 1/2] paravirt: init qemu cfg earlier

by Kevin O'Connor

On Mon, Apr 29, 2013 at 06:21:43PM +0300, Michael S. Tsirkin wrote: > This will make it possible to use fw config > info for pci initialization. > > Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> > --- > src/paravirt.c | 2 ++ > src/post.c | 1 - > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/paravirt.c b/src/paravirt.c > index e5027d0..85aa423 100644 > --- a/src/paravirt.c > +++ b/src/paravirt.c > @@ -97,6 +97,8 @@ qemu_platform_setup(void) > if (!CONFIG_QEMU) > return; > > + qemu_cfg_init(); That wont work - the romfile stuff is needed earlier (eg, in boot_init()). -Kevin

6 years, 7 months

2
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SeaBIOS April 2013