SeaBIOS January 2014

seabios@seabios.org

13 participants
37 discussions

[PATCH v2] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update

by David Woodhouse

We expect to use the space between the top of option ROMs and the bottom of our own BIOS code as a stack. OVMF was previously marking the whole region from 0xC0000 to 0xFFFFF read-only before invoking our Legacy16Boot method. Read-only stack considered harmful. Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which allow the CSM to specify a memory region that needs to be writable. There exists CONFIG_MALLOC_UPPERMEMORY which we could turn off to use the 9-segment, but that isn't particularly useful for the CSM case either because that memory isn't ours to play with until the final Legacy16Boot call. There's a LowPmmMemory given to use by UEFI to play with, but that's right in the *middle* of low memory and using that for persistent allocations would be painful. So just require CONFIG_MALLOC_UPPERMEMORY when building a CSM. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- v2: Require CONFIG_MALLOC_UPPERMEMORY. Default UmaAddress to &zonelow_base. src/Kconfig | 2 +- src/fw/csm.c | 6 +++++- src/std/LegacyBios.h | 20 ++++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a42ab2d..093075c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -114,7 +114,7 @@ endchoice the BIOS in 16bit protected mode. config MALLOC_UPPERMEMORY - bool "Allocate memory that needs to be in first Meg above 0xc0000" + bool "Allocate memory that needs to be in first Meg above 0xc0000" if !CSM default y help Use the "Upper Memory Block" area (0xc0000-0xf0000) for diff --git a/src/fw/csm.c b/src/fw/csm.c index dfb0d12..4e4b688 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -34,6 +34,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG __aligned(16) = { .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */, .OemIdStringPointer = (u32)"SeaBIOS", .AcpiRsdPtrPointer = (u32)&csm_rsdp, + .UmaAddress = (u32)&zonelow_base, + .UmaSize = 0x10000, }; EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table; @@ -46,9 +48,11 @@ extern void __csm_return(struct bregs *regs) __noreturn; static void csm_return(struct bregs *regs) { - dprintf(3, "handle_csm returning AX=%04x\n", regs->ax); + u32 top = rom_get_max(); PICMask = pic_irqmask_read(); + csm_compat_table.UmaAddress = top; + csm_compat_table.UmaSize = 0xf0000 - top; __csm_return(regs); } diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h index cf0c3c5..5170c37 100644 --- a/src/std/LegacyBios.h +++ b/src/std/LegacyBios.h @@ -228,6 +228,26 @@ typedef struct { /// Maximum PCI bus number assigned. /// UINT8 LastPciBus; + + /// + /// Start address of UMB RAM + /// + UINT32 UmaAddress; + + /// + /// Size of UMB RAM + /// + UINT32 UmaSize; + + /// + /// Start address of persistent allocation in high (>1MiB) memory + /// + UINT32 HiPermanentMemoryAddress; + + /// + /// Size of persistent allocation in high (>1MiB) memory + /// + UINT32 HiPermanentMemorySize; } EFI_COMPATIBILITY16_TABLE; /// -- 1.8.3.1 -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

7 years, 1 month

[PATCH 0/3] Run pvscsi driver entirely in 32bit mode.

by Kevin O'Connor

As with the recent change to AHCI, if the pvscsi driver needs to jump into 32bit mode to access a register, then it's better to run the pvscsi driver entirely in 32bit mode. Evgeny, can you take a look at this and give it a test? Also, what command line do you use for testing? I tried testing locally by adding: -device pvscsi,id=pvscsi0 -device scsi-disk,bus=pvscsi0.0,drive=drive0 -drive id=drive0,if=none,file=dos-drivec-new to my qemu command line (both qemu v1.6 and qemu v1.7), but it doesn't work for me even before my changes. It hangs in pvscsi_wait_intr_cmpl(). -Kevin Kevin O'Connor (3): pvscsi: Don't store reference to struct pci_device. pvscsi: Always run entirely in 32bit mode. pvscsi: Remove use of LOWFLAT and GLOBALFLAT macros. Makefile | 4 +-- src/block.c | 8 +++-- src/hw/blockcmd.c | 3 +- src/hw/pvscsi.c | 106 +++++++++++++++++++++++++----------------------------- 4 files changed, 58 insertions(+), 63 deletions(-) -- 1.8.3.1

7 years, 2 months

[RFC PATCH] Add support for Intel Quark UART.

by David Woodhouse

This provides basic debug output on the Quark system, assuming that *something* (i.e. coreboot or UEFI) has set it up in advance for us. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- I looked briefly at making this part of the CONFIG_DEBUG_SERIAL code, and making that generic enough to handle I/O access *or* MMIO access depending on what's present... but in fact that's probably overkill. This isn't really limited to Quark; it would work with any 16550 device wired up as MMIO32. But we can expand it as required, I think. No point in starting off with the same functionality as the 5000-odd lines of the Linux kernel's 8250_pci.c. What do I need to do if called in 32-bit segmented mode? I'm guessing that's not going to work right now... src/Kconfig | 5 +++++ src/fw/csm.c | 2 ++ src/output.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index a42ab2d..bdc2602 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -472,6 +472,11 @@ menu "Debugging" Set to zero to disable debugging. + config DEBUG_QUARK_UART + depends on DEBUG_LEVEL != 0 + bool "Debug to Quark UART #1" + default n + config DEBUG_SERIAL depends on DEBUG_LEVEL != 0 bool "Serial port debugging" diff --git a/src/fw/csm.c b/src/fw/csm.c index dfb0d12..afd7ffe 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -280,6 +280,8 @@ handle_csm(struct bregs *regs) if (!CONFIG_CSM) return; + debug_serial_preinit(); + dprintf(3, "handle_csm regs %p AX=%04x\n", regs, regs->ax); pic_irqmask_write(PICMask); diff --git a/src/output.c b/src/output.c index b47625f..a90d350 100644 --- a/src/output.c +++ b/src/output.c @@ -17,6 +17,8 @@ #include "stacks.h" // call16_int #include "string.h" // memset #include "util.h" // ScreenAndDebug +#include "hw/pci_regs.h" // PCI_VENDOR_ID, PCI_BASE_ADDRESS_0 +#include "hw/pci.h" // pci_config_readl struct putcinfo { void (*func)(struct putcinfo *info, char c); @@ -31,9 +33,59 @@ struct putcinfo { u16 DebugOutputPort VARFSEG = 0x402; +static volatile u32 *quark_uart_addr = 0; + +extern void _cfunc32flat_quark_uart_preinit(void); +extern void _cfunc32flat_quark_uart_putc(void); +extern void _cfunc32flat_quark_uart_flush(void); + +void quark_uart_preinit(void) +{ + // debug port is bus 0, device 0x14, function 5. + u16 uart_bdf = pci_to_bdf(0, 0x14, 5); + + // If it isn't a Quark UART... + if (pci_config_readl(uart_bdf, PCI_VENDOR_ID) != 0x09368086) + return; + + u32 bar0 = pci_config_readl(uart_bdf, PCI_BASE_ADDRESS_0); + if (!(bar0 & 0xf)) + quark_uart_addr = (void *)bar0; +} + +void quark_uart_putc(char c) +{ + if (!quark_uart_addr) + return; + + int timeout = DEBUG_TIMEOUT; + while ((quark_uart_addr[SEROFF_LSR] & 0x20) != 0x20) + if (!timeout--) + // Ran out of time. + return; + quark_uart_addr[SEROFF_DATA] = c; +} + +void quark_uart_flush(void) +{ + if (!quark_uart_addr) + return; + int timeout = DEBUG_TIMEOUT; + while ((quark_uart_addr[SEROFF_LSR] & 0x60) != 0x60) + if (!timeout--) + // Ran out of time. + return; +} + void debug_serial_preinit(void) { + if (CONFIG_DEBUG_QUARK_UART) { + if (MODE16) + call32(_cfunc32flat_quark_uart_preinit, 0, 0); + else + quark_uart_preinit(); + } if (!CONFIG_DEBUG_SERIAL) return; // setup for serial logging: 8N1 @@ -54,6 +106,12 @@ debug_serial_preinit(void) static void debug_serial(char c) { + if (CONFIG_DEBUG_QUARK_UART) { + if (MODE16) + call32(_cfunc32flat_quark_uart_putc, c, 0); + else + quark_uart_putc(c); + } if (!CONFIG_DEBUG_SERIAL) return; int timeout = DEBUG_TIMEOUT; @@ -68,6 +126,12 @@ debug_serial(char c) static void debug_serial_flush(void) { + if (CONFIG_DEBUG_QUARK_UART) { + if (MODE16) + call32(_cfunc32flat_quark_uart_flush, 0, 0); + else + quark_uart_flush(); + } if (!CONFIG_DEBUG_SERIAL) return; int timeout = DEBUG_TIMEOUT; -- 1.8.3.1 -- dwmw2

7 years, 2 months

[PATCH] vga: rework bar detection, add virtio-vga

by Gerd Hoffmann

Replace the heuristic which checks the bar 0 attributes to figure whenever bar 0 or bar 1 has the linear framebuffer with a vendor id check. Add support for virtio-vga which uses bar 2 for the linear framebuffer. Cc: Dave Airlie <airlied(a)redhat.com> Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- vgasrc/bochsvga.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/vgasrc/bochsvga.c b/vgasrc/bochsvga.c index 6da9d5d..b802be1 100644 --- a/vgasrc/bochsvga.c +++ b/vgasrc/bochsvga.c @@ -402,12 +402,20 @@ bochsvga_setup(void) u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS; int bdf = GET_GLOBAL(VgaBDF); if (CONFIG_VGA_PCI && bdf >= 0) { - int barid = 0; - u32 bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_0); - if ((bar & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY) { + u16 vendor = pci_config_readw(bdf, PCI_VENDOR_ID); + int barid; + switch (vendor) { + case 0x15ad: /* qemu vmware vga */ barid = 1; - bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_1); + break; + case 0x1af4: /* virtio-vga */ + barid = 2; + break; + default: /* stdvga, qxl */ + barid = 0; + break; } + u32 bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_0 + barid * 4); lfb_addr = bar & PCI_BASE_ADDRESS_MEM_MASK; dprintf(1, "VBE DISPI: bdf %02x:%02x.%x, bar %d\n", pci_bdf_to_bus(bdf) , pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf), barid); -- 1.8.3.1

7 years, 4 months

[PATCH] pci: improve io address space allocation

by Gerd Hoffmann

This patch improves the io address space allocation. It adds a check that the region above 0xc000 which is traditionally used for pci io is actually big enougth. If it isn't it tries the larger window at 0x1000. If that is to small too it errors out. When creating guests with multiple pci-pci bridges (and devices with io regions behind them) the 0xc000 -> 0xffff region quickly becomes too small. While being at it document the io address space layout used by qemu/seabios. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/fw/pciinit.c | 45 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index b0d01ca..64f1d41 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -705,10 +705,42 @@ static int pci_bios_check_devices(struct pci_bus *busses) ****************************************************************/ // Setup region bases (given the regions' size and alignment) -static int pci_bios_init_root_regions(struct pci_bus *bus) -{ - bus->r[PCI_REGION_TYPE_IO].base = 0xc000; +static int pci_bios_init_root_regions_io(struct pci_bus *bus) +{ + /* + * QEMU I/O address space usage: + * 0000 - 0fff legacy isa, pci config, pci root bus, ... + * 1000 - 9fff free + * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only) + * b000 - bfff power management (PORT_ACPI_PM_BASE) + * [ qemu 1.4+ implements pci config registers + * properly so guests can place the registers + * where they want, on older versions its fixed ] + * c000 - ffff free, traditionally used for pci io + */ + struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO]; + u64 sum = pci_region_sum(r_io); + if (sum < 0x4000) { + /* traditional region is big enougth, use it */ + r_io->base = 0xc000; + } else if (sum < 0x9000) { + /* use the larger region at 0x1000 */ + r_io->base = 0x1000; + } else { + /* + * Not enougth io address space -> error out. + * + * TODO: on q35 we can move PORT_ACPI_PM_BASE out of + * the way, then use the whole 1000 -> ffff region. + */ + return -1; + } + dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1); + return 0; +} +static int pci_bios_init_root_regions_mem(struct pci_bus *bus) +{ struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM]; struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM]; @@ -786,8 +818,11 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) static void pci_bios_map_devices(struct pci_bus *busses) { + if (pci_bios_init_root_regions_io(busses)) + panic("PCI: out of I/O address space\n"); + dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end); - if (pci_bios_init_root_regions(busses)) { + if (pci_bios_init_root_regions_mem(busses)) { struct pci_region r64_mem, r64_pref; r64_mem.list.first = NULL; r64_pref.list.first = NULL; @@ -796,7 +831,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM], &r64_pref); - if (pci_bios_init_root_regions(busses)) + if (pci_bios_init_root_regions_mem(busses)) panic("PCI: out of 32bit address space\n"); u64 sum_mem = pci_region_sum(&r64_mem); -- 1.8.3.1

7 years, 5 months

[RFC][PATCH] coreboot: Add support for a "links" file to have aliases in CBFS.

by Kevin O'Connor

The "links" file is a newline separated list where each line is a "link name" followed by a "destination name" separated by a space character. For each line, SeaBIOS will consider each "link name" to be a CBFS file that has the contents found in the CBFS file with "destination name". Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- This patch may be useful for those using intel option roms where the same rom is used on a number of VGA devices with different vendor/device ids. With this patch, one can make a "links" file with the list of devices (eg, "pci8086,0a06.rom") that all point to the same physical rom (eg, "pci8086,0406.rom"). It's possible to implement this aliasing approach in a number of different ways. The approach taken in this patch is a single file with all the link names. This was done based on feedback that there could be 20 or more aliases for a single rom and creating individual CBFS files for each link would be unwieldy. That said, I'm not sure this is the best approach. I'm circulating it for comments. --- src/fw/coreboot.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index df8fca8..270d01a 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -408,6 +408,40 @@ coreboot_cbfs_init(void) fhdr = (void*)ALIGN((u32)cfile->data + cfile->rawsize , be32_to_cpu(hdr->align)); } + + // Process CBFS links file. The links file is a newline separated + // file where each line has a "link name" and a destination name + // separated by a space character. + char *links = romfile_loadfile("links", NULL); + if (!links) + return; + char *p = links; + for (;;) { + char *linkname = p; + char *end = strchr(linkname, '\n'); + if (!end) + break; + *end = '\0'; + p = end + 1; + char *linkend = strchr(linkname, ' '); + if (!linkend || linkname == linkend) + continue; + *linkend = '\0'; + struct romfile_s *ufile = romfile_find(linkend+1); + if (!ufile) + continue; + struct cbfs_romfile_s *cufile + = container_of(ufile, struct cbfs_romfile_s, file); + struct cbfs_romfile_s *cfile = malloc_tmp(sizeof(*cfile)); + if (!cfile) { + warn_noalloc(); + break; + } + memcpy(cfile, cufile, sizeof(*cfile)); + strtcpy(cfile->file.name, linkname, sizeof(cfile->file.name)); + romfile_add(&cfile->file); + } + free(links); } struct cbfs_payload_segment { -- 1.8.5.3

7 years, 6 months

Re: [SeaBIOS] [RFC] vgahooks: Add Google stumpy, lumpy, and link boards to intel vgahook list.

by Kevin O'Connor

On Fri, Jan 17, 2014 at 04:50:27PM -0800, Stefan Reinauer wrote: > Yes, I think it's worth having them in upstream SeaBIOS! > > I've been thinking about creating a way of passing this information between > coreboot and SeaBIOS in the future, so we don't have to keep the handlers > around twice. One way of doing that would be to have the handler live in > SMM and have SeaBIOS do an SMI command to get the right answers. Would you > be open to something like that? That seems over kill to me. The Intel VGA stuff seems to be pretty stable and it's only a few fields that need to be passed back. What about placing the required info in a coreboot table - then SeaBIOS can just pass back the desired fields and not have to have board by board specific logic. BTW, I didn't port over "Alex" as it seems to be totally different from the other boards. -Kevin

7 years, 6 months

Re: [SeaBIOS] [PATCH 1/3] usb: Move default pipe max packet size code from xhci to main code.

by Kevin O'Connor

On Mon, Jan 27, 2014 at 12:29:11PM -0500, Kevin O'Connor wrote: > Also, the max packet size for super speed devices is 512 bytes (not > 256 bytes). > > Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> > --- > > Some additional patches on my xhci-testing branch. Also available at: > > https://github.com/KevinOConnor/seabios/tree/xhci-testing FYI, I have pushed the xhci-testing branch to the seabios master branch. -Kevin

7 years, 6 months

[PATCH 3/3] xhci: Add copyright notice to usb-xhci.c

by Kevin O'Connor

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/hw/usb-xhci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index b307c5e..e3acc39 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -1,3 +1,10 @@ +// Code for handling XHCI "Super speed" USB controllers. +// +// Copyright (C) 2013 Gerd Hoffmann <kraxel(a)redhat.com> +// Copyright (C) 2014 Kevin O'Connor <kevin(a)koconnor.net> +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + #include "biosvar.h" // GET_LOWFLAT #include "config.h" // CONFIG_* #include "malloc.h" // memalign_low -- 1.8.5.3

7 years, 6 months

[PATCH 2/3] xhci: Use the same endpoint initialization code in xhci_alloc_pipe()

by Kevin O'Connor

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/hw/usb-xhci.c | 74 ++++++++++++++++++++++--------------------------------- 1 file changed, 29 insertions(+), 45 deletions(-) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index 3366f09..b307c5e 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -804,7 +804,7 @@ static struct usbhub_op_s xhci_hub_ops = { static struct xhci_inctx * -xhci_alloc_inctx(struct usbdevice_s *usbdev) +xhci_alloc_inctx(struct usbdevice_s *usbdev, int maxepid) { struct usb_xhci_s *xhci = container_of( usbdev->hub->cntl, struct usb_xhci_s, usb); @@ -816,9 +816,8 @@ xhci_alloc_inctx(struct usbdevice_s *usbdev) } memset(in, 0, size); - in->add = 0x01; struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64]; - slot->ctx[0] |= (1 << 27); // context entries + slot->ctx[0] |= maxepid << 27; // context entries slot->ctx[0] |= speed_to_xhci[usbdev->speed] << 20; // Set high-speed hub flags. @@ -859,9 +858,10 @@ static int xhci_config_hub(struct usbhub_s *hub) if ((hdslot->ctx[3] >> 27) == 3) // Already configured return 0; - struct xhci_inctx *in = xhci_alloc_inctx(hub->usbdev); + struct xhci_inctx *in = xhci_alloc_inctx(hub->usbdev, 1); if (!in) return -1; + in->add = 0x01; struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64]; slot->ctx[0] |= 1 << 26; slot->ctx[1] |= hub->portcount << 24; @@ -911,6 +911,23 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev if (eptype == USB_ENDPOINT_XFER_INT) pipe->buf = malloc_low(pipe->pipe.maxpacket); + // Allocate input context and initialize endpoint info. + struct xhci_inctx *in = xhci_alloc_inctx(usbdev, epid); + if (!in) + goto fail; + in->add = 0x01 | (1 << epid); + struct xhci_epctx *ep = (void*)&in[(pipe->epid+1) << xhci->context64]; + if (eptype == USB_ENDPOINT_XFER_INT) + ep->ctx[0] = (usb_getFrameExp(usbdev, epdesc) + 3) << 16; + ep->ctx[1] |= eptype << 3; + if (epdesc->bEndpointAddress & USB_DIR_IN + || eptype == USB_ENDPOINT_XFER_CONTROL) + ep->ctx[1] |= 1 << 5; + ep->ctx[1] |= pipe->pipe.maxpacket << 16; + ep->deq_low = (u32)&pipe->reqs.ring[0]; + ep->deq_low |= 1; // dcs + ep->length = pipe->pipe.maxpacket; + dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__, usbdev, &pipe->reqs, pipe->slotid, pipe->epid); if (pipe->epid == 1) { @@ -920,7 +937,7 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev if (ret) goto fail; } - // Enable slot and send set_address command. + // Enable slot. u32 size = (sizeof(struct xhci_slotctx) * 32) << xhci->context64; struct xhci_slotctx *dev = memalign_high(1024 << xhci->context64, size); if (!dev) { @@ -934,65 +951,32 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev goto fail; } dprintf(3, "%s: enable slot: got slotid %d\n", __func__, slotid); - memset(dev, 0, size); pipe->slotid = usbdev->slotid = slotid; xhci->devs[slotid].ptr_low = (u32)dev; xhci->devs[slotid].ptr_high = 0; - struct xhci_inctx *in = xhci_alloc_inctx(usbdev); - if (!in) - goto fail; - in->add |= (1 << 1); - - struct xhci_epctx *ep = (void*)&in[2 << xhci->context64]; - ep->ctx[0] |= (3 << 16); // interval: 1ms - ep->ctx[1] |= (4 << 3); // control pipe - ep->ctx[1] |= (pipe->pipe.maxpacket << 16); - - ep->deq_low = (u32)&pipe->reqs.ring[0]; - ep->deq_low |= 1; // dcs - ep->deq_high = 0; - ep->length = pipe->pipe.maxpacket; - + // Send set_address command. int cc = xhci_cmd_address_device(xhci, slotid, in); - free(in); if (cc != CC_SUCCESS) { dprintf(1, "%s: address device: failed (cc %d)\n", __func__, cc); goto fail; } } else { - struct xhci_inctx *in = xhci_alloc_inctx(usbdev); - if (!in) - goto fail; - in->add |= (1 << pipe->epid); - struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64]; - slot->ctx[0] = (slot->ctx[0] & ~0xf8000000) | (pipe->epid << 27); - - struct xhci_epctx *ep = (void*)&in[(pipe->epid+1) << xhci->context64]; - if (eptype == USB_ENDPOINT_XFER_INT) - ep->ctx[0] = (usb_getFrameExp(usbdev, epdesc) + 3) << 16; - ep->ctx[1] |= (eptype << 3); - if (epdesc->bEndpointAddress & USB_DIR_IN) - ep->ctx[1] |= (1 << 5); - ep->ctx[1] |= (pipe->pipe.maxpacket << 16); - ep->deq_low = (u32)&pipe->reqs.ring[0]; - ep->deq_low |= 1; // dcs - ep->deq_high = 0; - ep->length = pipe->pipe.maxpacket; - pipe->slotid = usbdev->slotid; + // Send configure command. int cc = xhci_cmd_configure_endpoint(xhci, pipe->slotid, in); - free(in); if (cc != CC_SUCCESS) { dprintf(1, "%s: configure endpoint: failed (cc %d)\n", __func__, cc); goto fail; } } - + free(in); return &pipe->pipe; + fail: free(pipe); + free(in); return NULL; } @@ -1010,11 +994,11 @@ xhci_update_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__, usbdev, &pipe->reqs, pipe->slotid, pipe->epid); if (eptype == USB_ENDPOINT_XFER_CONTROL && - pipe->pipe.maxpacket != epdesc->wMaxPacketSize) { + pipe->pipe.maxpacket != epdesc->wMaxPacketSize) { dprintf(1, "%s: reconf ctl endpoint pkt size: %d -> %d\n", __func__, pipe->pipe.maxpacket, epdesc->wMaxPacketSize); pipe->pipe.maxpacket = epdesc->wMaxPacketSize; - struct xhci_inctx *in = xhci_alloc_inctx(usbdev); + struct xhci_inctx *in = xhci_alloc_inctx(usbdev, 1); if (!in) return upipe; in->add = (1 << 1); -- 1.8.5.3

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SeaBIOS January 2014