SeaBIOS January 2014

seabios@seabios.org

13 participants
37 discussions

[PATCH 00/10] XHCI patches for real-hardware
by Kevin O'Connor 13 Jan '14

13 Jan '14

The following is my test series for XHCI. I've gotten it to the point that I can boot from a "super speed" USB flash drive. However, high speed flash drives and low speed keyboard/mouse still don't work for me. Hopefully, when Gerd returns he'll have some insight. The most notable part of this series is the work to make the code auto-detect and handle 64 byte contexts (which the xhci controller on my e350m1 requires). The series is also available at: https://github.com/KevinOConnor/seabios/tree/xhci-testing -Kevin Gerd Hoffmann (1): xhci: allocate scratch pad buffers Kevin O'Connor (9): xhci: Use 64bit writes to ERDP register. xhci: Fix incorrect direction setting on status transmissions. xhci: Set the interval parameter on interrupt pipes. xhci: Verify PAGESIZE register before initializing driver. xhci: Allocate and free the xhci inctx structure on each use. xhci: Move set_address code from xhci_control to xhci_alloc_pipe. xhci: Eliminate 'struct xhci_device'. xhci: Support xhci controllers with 64 byte contexts. xhci: Allow the XHCI USB controller to be enabled for coreboot. src/Kconfig | 2 +- src/hw/usb-xhci.c | 342 +++++++++++++++++++++++++++++------------------------- src/hw/usb-xhci.h | 8 -- src/hw/usb.c | 4 +- src/hw/usb.h | 1 + 5 files changed, 186 insertions(+), 171 deletions(-) -- 1.8.3.1

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[PATCH] seabios: call pci_init_device on resume
by Michael S. Tsirkin 13 Jan '14

13 Jan '14

PIIX spec says that most its registers are reset on suspend. However, QEMU didn't reset most of them properly. Now that it started doing that, resume is broken. Fix it up by probing system devices on bus 0 and re-initializing them. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> Reported-by: Gal Hammer <ghammer(a)redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a(a)redhat.com> Tested-by: Marcel Apfelbaum <marcel.a(a)redhat.com> --- src/hw/pci.h | 1 + src/util.h | 1 + src/fw/pciinit.c | 5 +++++ src/hw/pci.c | 31 ++++++++++++++++++++----------- src/resume.c | 8 ++++++++ 5 files changed, 35 insertions(+), 11 deletions(-) diff --git a/src/hw/pci.h b/src/hw/pci.h index 9c7351d..a64f7c5 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -66,6 +66,7 @@ extern u64 pcimem64_start, pcimem64_end; extern struct hlist_head PCIDevices; extern int MaxPCIBus; int pci_probe_host(void); +void pci_probe_device(int bdf, struct pci_device *dev); void pci_probe_devices(void); static inline u32 pci_classprog(struct pci_device *pci) { return (pci->class << 8) | pci->prog_if; diff --git a/src/util.h b/src/util.h index e6a6cb5..3a24dba 100644 --- a/src/util.h +++ b/src/util.h @@ -28,6 +28,7 @@ void boot_add_cbfs(void *data, const char *desc, int prio); void interactive_bootmenu(void); void bcv_prepboot(void); struct pci_device; +void pci_bios_resume_device(struct pci_device *pci); int bootprio_find_pci_device(struct pci_device *pci); int bootprio_find_scsi_device(struct pci_device *pci, int target, int lun); int bootprio_find_ata_device(struct pci_device *pci, int chanid, int slave); diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 34279a4..a4cedfb 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -293,6 +293,11 @@ static const struct pci_device_id pci_device_tbl[] = { PCI_DEVICE_END, }; +void pci_bios_resume_device(struct pci_device *pci) +{ + pci_init_device(pci_device_tbl, pci, NULL); +} + static void pci_bios_init_device(struct pci_device *pci) { u16 bdf = pci->bdf; diff --git a/src/hw/pci.c b/src/hw/pci.c index 6c9aa81..c2873c3 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -105,6 +105,24 @@ pci_probe_host(void) return 0; } +void +pci_probe_device(int bdf, struct pci_device *dev) +{ + dev->bdf = bdf; + u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID); + dev->vendor = vendev & 0xffff; + dev->device = vendev >> 16; + u32 classrev = pci_config_readl(bdf, PCI_CLASS_REVISION); + dev->class = classrev >> 16; + dev->prog_if = classrev >> 8; + dev->revision = classrev & 0xff; + dev->header_type = pci_config_readb(bdf, PCI_HEADER_TYPE); + u8 v = dev->header_type & 0x7f; + if (v == PCI_HEADER_TYPE_BRIDGE || v == PCI_HEADER_TYPE_CARDBUS) { + u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS); + dev->secondary_bus = secbus; + } +} // Find all PCI devices and populate PCIDevices linked list. void pci_probe_devices(void) @@ -145,21 +163,12 @@ pci_probe_devices(void) } // Populate pci_device info. - dev->bdf = bdf; + pci_probe_device(bdf, dev); dev->parent = parent; dev->rootbus = rootbus; - u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID); - dev->vendor = vendev & 0xffff; - dev->device = vendev >> 16; - u32 classrev = pci_config_readl(bdf, PCI_CLASS_REVISION); - dev->class = classrev >> 16; - dev->prog_if = classrev >> 8; - dev->revision = classrev & 0xff; - dev->header_type = pci_config_readb(bdf, PCI_HEADER_TYPE); u8 v = dev->header_type & 0x7f; if (v == PCI_HEADER_TYPE_BRIDGE || v == PCI_HEADER_TYPE_CARDBUS) { - u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS); - dev->secondary_bus = secbus; + u8 secbus = dev->secondary_bus; if (secbus > bus && !busdevs[secbus]) busdevs[secbus] = dev; if (secbus > MaxPCIBus) diff --git a/src/resume.c b/src/resume.c index fc2fee9..9aac853 100644 --- a/src/resume.c +++ b/src/resume.c @@ -101,6 +101,14 @@ s3_resume(void) pic_setup(); smm_setup(); + int bdf; + foreachbdf(bdf, 0) { + // Create new pci_device struct and add to list. + struct pci_device pci; + pci_probe_device(bdf, &pci); + pci_bios_resume_device(&pci); + } + s3_resume_vga(); make_bios_readonly(); -- MST

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[[PATCH] ] Prevent build failure by not splitting line in the middle of arguments to checkrom.py script
by Sander Eikelenboom 10 Jan '14

10 Jan '14

File "./scripts/checkrom.py", line 24, in main objinfo, finalsize, rawfile, outfile = sys.argv[1:] ValueError: need more than 3 values to unpack Signed-off-by: Sander Eikelenboom <linux(a)eikelenboom.it> --- Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile b/Makefile index cb15217..8efc902 100644 --- a/Makefile +++ b/Makefile @@ -182,8 +182,7 @@ $(OUT)bios.bin.prep: $(OUT)rom.o scripts/checkrom.py $(Q)rm -f $(OUT)bios.bin $(OUT)Csm16.bin $(OUT)bios.bin.elf $(Q)$(OBJDUMP) -thr $< > $<.objdump $(Q)$(OBJCOPY) -O binary $< $(OUT)bios.bin.raw - $(Q)$(PYTHON) ./scripts/checkrom.py $<.objdump $(CONFIG_ROM_SIZE) \ - $(OUT)bios.bin.raw $(OUT)bios.bin.prep + $(Q)$(PYTHON) ./scripts/checkrom.py $<.objdump $(CONFIG_ROM_SIZE) $(OUT)bios.bin.raw $(OUT)bios.bin.prep $(OUT)bios.bin: $(OUT)bios.bin.prep @echo " Creating $@" -- 1.7.10.4

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[PATCH 1/3] Introduce serial_out(), serial_in() macros in serialio.c
by David Woodhouse 10 Jan '14

10 Jan '14

This will make it easier to abstract out the MMIO serial access. Even if that ends up in separate code which is a *copy* of this, at least they'll match. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- src/hw/serialio.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src/hw/serialio.c b/src/hw/serialio.c index 6486fc0..8ec36c2 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -1,6 +1,6 @@ // Low-level serial (and serial-like) device access. // -// Copyright (C) 2008-1013 Kevin O'Connor <kevin(a)koconnor.net> +// Copyright (C) 2008-2013 Kevin O'Connor <kevin(a)koconnor.net> // // This file may be distributed under the terms of the GNU LGPLv3 license. @@ -17,6 +17,9 @@ #define DEBUG_TIMEOUT 100000 +#define serial_out(d, reg) outb(d, CONFIG_DEBUG_SERIAL_PORT+(reg)) +#define serial_in(reg) inb(CONFIG_DEBUG_SERIAL_PORT+(reg)) + // Setup the debug serial port for output. void serial_debug_preinit(void) @@ -25,12 +28,12 @@ serial_debug_preinit(void) return; // setup for serial logging: 8N1 u8 oldparam, newparam = 0x03; - oldparam = inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LCR); - outb(newparam, CONFIG_DEBUG_SERIAL_PORT+SEROFF_LCR); + oldparam = serial_in(SEROFF_LCR); + serial_out(newparam, SEROFF_LCR); // Disable irqs u8 oldier, newier = 0; - oldier = inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_IER); - outb(newier, CONFIG_DEBUG_SERIAL_PORT+SEROFF_IER); + oldier = serial_in(SEROFF_IER); + serial_out(newier, SEROFF_IER); if (oldparam != newparam || oldier != newier) dprintf(1, "Changing serial settings was %x/%x now %x/%x\n" @@ -44,11 +47,11 @@ serial_debug(char c) if (!CONFIG_DEBUG_SERIAL) return; int timeout = DEBUG_TIMEOUT; - while ((inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LSR) & 0x20) != 0x20) + while ((serial_in(SEROFF_LSR) & 0x20) != 0x20) if (!timeout--) // Ran out of time. return; - outb(c, CONFIG_DEBUG_SERIAL_PORT+SEROFF_DATA); + serial_out(c, SEROFF_DATA); } void @@ -66,7 +69,7 @@ serial_debug_flush(void) if (!CONFIG_DEBUG_SERIAL) return; int timeout = DEBUG_TIMEOUT; - while ((inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LSR) & 0x60) != 0x60) + while ((serial_in(SEROFF_LSR) & 0x60) != 0x60) if (!timeout--) // Ran out of time. return; -- 1.8.3.1 -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

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[PATCH] Change pvscsi to use BAR 1.
by Don Koch 09 Jan '14

09 Jan '14

From: Don Koch <dkoch(a)cloudswitch.com> Change pvscsi to use BAR 1 (mmio) instead of BAR 0 (ioport). Signed-off-by: Don Koch <dkoch(a)verizon.com> --- I found that when using bar 0, the VM wouldn't boot where using bar 1 worked. Cced Evgeny for review. src/hw/pvscsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hw/pvscsi.c b/src/hw/pvscsi.c index 6911230..1204a4c 100644 --- a/src/hw/pvscsi.c +++ b/src/hw/pvscsi.c @@ -326,7 +326,7 @@ init_pvscsi(struct pci_device *pci) struct pvscsi_ring_dsc_s *ring_dsc = NULL; int i; u16 bdf = pci->bdf; - u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0) + u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_1) & PCI_BASE_ADDRESS_MEM_MASK; pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_MASTER); -- 1.8.1.4

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Re: [SeaBIOS] [PATCH] usb: Replace EHCI to UHCI/OHCI synchronization with new scheme.
by Kevin O'Connor 06 Jan '14

06 Jan '14

On Fri, Dec 27, 2013 at 12:25:02PM -0500, Kevin O'Connor wrote: > The previous code attempts to correlate which UHCI and OHCI > controllers correlate with which EHCI controllers so that it can > ensure high speed devices are handled by the EHCI code while low/full > speed devices are handled by the UHCI/OHCI code. Replace this logic > by initializing all EHCI controllers first, and then initializing all > UHCI and OHCI controllers. This simplifies the code and improves > support for some hardware devices that don't follow the OHCI/UHCI to > EHCI correlation standard. > > Also, remove the unused usb->busid field. FYI, I have pushed this patch (along with the pvscsi, thread cleanup, and block transfer patches). -Kevin

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Re: [SeaBIOS] [PATCH] xhci: allocate scratch pad buffers
by Idwer Vollering 01 Jan '14

01 Jan '14

Running the same branch, with rebase code; commit ID is 83c7484d5c and a super high speed device is attached to one of the usb 3.0 ports: SeaBIOS (version rel-1.7.4-26-g83c7484-20131231_152015-debian) init usb XHCI init on dev 00:10.0: regs @ 0xf0148000, 4 ports, 32 slots, 32 byte contexts XHCI extcap 0x1 @ f0148500 XHCI protocol USB 3.00, 2 ports (offset 1), def 0 XHCI protocol USB 2.00, 2 ports (offset 3), def 0 configure_xhci: resetting xhci_hub_detect port #1: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #2: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #3: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #4: 0x000202e1, powered, pls 7, speed 0 [ - ] xhci_hub_reset port #4: 0x000202e1, powered, pls 7, speed 0 [ - ] XHCI port #4: 0x00200e03, powered, enabled, pls 0, speed 3 [High] set_address 0x000ee6b0 xhci_alloc_pipe: usbdev 0xbf1025d0, ring 0xbf11eb00, slotid 0, epid 1 xhci_cmd_enable_slot: xhci_trb_queue: ring 0xbf11ed00 [nidx 1, len 0] xhci_process_events: status change port #4 xhci_process_events: status change port #2 xhci_process_events: status change port #4 xhci_process_events: ring 0xbf11ed00 [trb 0xbf11ed00, evt 0xbf11ee00, type 33, eidx 1, cc 1] xhci_alloc_pipe: enable slot: got slotid 1 xhci_cmd_address_device: slotid 1 xhci_trb_queue: ring 0xbf11ed00 [nidx 2, len 0] WARNING - Timeout at xhci_event_wait:394! xhci_alloc_pipe: address device: failed (cc -1) XHCI no devices found WARNING - Timeout at wait_bit:484! XHCI init on dev 00:10.1: regs @ 0xf014a000, 4 ports, 32 slots, 32 byte contexts XHCI extcap 0x1 @ f014a500 XHCI protocol USB 3.00, 2 ports (offset 1), def 0 XHCI protocol USB 2.00, 2 ports (offset 3), def 0 configure_xhci: resetting xhci_hub_detect port #1: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #2: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #3: 0x000002a0, powered, pls 5, speed 0 [ - ] xhci_hub_detect port #4: 0x000002a0, powered, pls 5, speed 0 [ - ] XHCI no devices found EHCI init on dev 00:12.2 (regs=0xf014f820) set_address 0xbf1026c0 ehci_alloc_async_pipe 0xbf1026c0 0 ehci_control 0xbf102550 (dir=0 cmd=8 data=0) ehci_alloc_async_pipe 0xbf1026c0 0 config_usb: 0xbf102550 ehci_control 0xbf102550 (dir=128 cmd=8 data=8) device rev=0200 cls=00 sub=00 proto=00 size=40 ehci_alloc_async_pipe 0xbf1026c0 0 ehci_control 0xbf102550 (dir=128 cmd=8 data=9) ehci_control 0xbf102550 (dir=128 cmd=8 data=46) ehci_free_pipes 0xbf1026c0 EHCI init on dev 00:13.2 (regs=0xf014f920) ehci_free_pipes 0xbf1026c0 OHCI init on dev 00:12.0 (regs=0xf014c000) set_address 0xbf1026c0 ohci_alloc_async_pipe 0xbf1026c0 ohci_control 0xbf1025c0 ohci_alloc_async_pipe 0xbf1026c0 config_usb: 0xbf1025c0 ohci_control 0xbf1025c0 device rev=0110 cls=00 sub=00 proto=00 size=08 ohci_alloc_async_pipe 0xbf1026c0 ohci_control 0xbf1025c0 ohci_control 0xbf1025c0 ohci_control 0xbf1025c0 usb_hid_setup 0xbf1025c0 ohci_control 0xbf1025c0 ohci_control 0xbf1025c0 ohci_alloc_intr_pipe 0xbf1026c0 3 USB keyboard initialized ohci_free_pipes 0xbf1026c0 OHCI init on dev 00:13.0 (regs=0xf014d000) ohci_free_pipes 0xbf102610 OHCI init on dev 00:14.5 (regs=0xf014e000) ohci_free_pipes 0xbf1025c0

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SeaBIOS January 2014