SeaBIOS January 2014

seabios@seabios.org

13 participants
37 discussions

[PATCH 1/3] usb: Move default pipe max packet size code from xhci to main code.
by Kevin O'Connor 27 Jan '14

27 Jan '14

Also, the max packet size for super speed devices is 512 bytes (not 256 bytes). Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- Some additional patches on my xhci-testing branch. Also available at: https://github.com/KevinOConnor/seabios/tree/xhci-testing --- src/hw/usb-xhci.c | 11 ++--------- src/hw/usb.c | 9 ++++++++- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index daa7b5a..3366f09 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -282,13 +282,6 @@ static const int speed_to_xhci[] = { [ USB_SUPERSPEED ] = 4, }; -static const int speed_to_ctlsize[] = { - [ USB_FULLSPEED ] = 8, - [ USB_LOWSPEED ] = 8, - [ USB_HIGHSPEED ] = 64, - [ USB_SUPERSPEED ] = 256, -}; - static const int eptype_to_xhci_in[] = { [ USB_ENDPOINT_XFER_CONTROL] = 4, [ USB_ENDPOINT_XFER_ISOC ] = 5, @@ -955,12 +948,12 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev struct xhci_epctx *ep = (void*)&in[2 << xhci->context64]; ep->ctx[0] |= (3 << 16); // interval: 1ms ep->ctx[1] |= (4 << 3); // control pipe - ep->ctx[1] |= (speed_to_ctlsize[usbdev->speed] << 16); + ep->ctx[1] |= (pipe->pipe.maxpacket << 16); ep->deq_low = (u32)&pipe->reqs.ring[0]; ep->deq_low |= 1; // dcs ep->deq_high = 0; - ep->length = 8; + ep->length = pipe->pipe.maxpacket; int cc = xhci_cmd_address_device(xhci, slotid, in); free(in); diff --git a/src/hw/usb.c b/src/hw/usb.c index ff20b6c..7b8a9f5 100644 --- a/src/hw/usb.c +++ b/src/hw/usb.c @@ -261,6 +261,13 @@ set_configuration(struct usb_pipe *pipe, u16 val) * Initialization and enumeration ****************************************************************/ +static const int speed_to_ctlsize[] = { + [ USB_FULLSPEED ] = 8, + [ USB_LOWSPEED ] = 8, + [ USB_HIGHSPEED ] = 64, + [ USB_SUPERSPEED ] = 512, +}; + // Assign an address to a device in the default state on the given // controller. static int @@ -276,7 +283,7 @@ usb_set_address(struct usbdevice_s *usbdev) // Create a pipe for the default address. struct usb_endpoint_descriptor epdesc = { - .wMaxPacketSize = 8, + .wMaxPacketSize = speed_to_ctlsize[usbdev->speed], .bmAttributes = USB_ENDPOINT_XFER_CONTROL, }; usbdev->defpipe = usb_alloc_pipe(usbdev, &epdesc); -- 1.8.5.3

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[PATCH] usb: USB 3 devices encode bMaxPacketSize0 field.
by Kevin O'Connor 27 Jan '14

27 Jan '14

A USB 3 device uses an exponential encoding of the max packet size for the default end point. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- With this patch, my superspeed flash drive is now detected on my Haswell based xhci controller. (Interestingly, the same flash drive worked on my other computer without this patch, even though the max packet length is definitely not correct without this patch.) This is also at: https://github.com/KevinOConnor/seabios/tree/xhci-testing --- src/hw/usb.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/hw/usb.c b/src/hw/usb.c index 8ffddf8..ff20b6c 100644 --- a/src/hw/usb.c +++ b/src/hw/usb.c @@ -319,13 +319,16 @@ configure_usb_device(struct usbdevice_s *usbdev) int ret = get_device_info8(usbdev->defpipe, &dinfo); if (ret) return 0; - dprintf(3, "device rev=%04x cls=%02x sub=%02x proto=%02x size=%02x\n" + u16 maxpacket = dinfo.bMaxPacketSize0; + if (dinfo.bcdUSB >= 0x0300) + maxpacket = 1 << dinfo.bMaxPacketSize0; + dprintf(3, "device rev=%04x cls=%02x sub=%02x proto=%02x size=%d\n" , dinfo.bcdUSB, dinfo.bDeviceClass, dinfo.bDeviceSubClass - , dinfo.bDeviceProtocol, dinfo.bMaxPacketSize0); - if (dinfo.bMaxPacketSize0 < 8 || dinfo.bMaxPacketSize0 > 64) + , dinfo.bDeviceProtocol, maxpacket); + if (maxpacket < 8) return 0; struct usb_endpoint_descriptor epdesc = { - .wMaxPacketSize = dinfo.bMaxPacketSize0, + .wMaxPacketSize = maxpacket, .bmAttributes = USB_ENDPOINT_XFER_CONTROL, }; usbdev->defpipe = usb_update_pipe(usbdev, usbdev->defpipe, &epdesc); -- 1.8.3.1

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[PATCH] Increase maximum size of permanent high memory area.
by Kevin O'Connor 24 Jan '14

24 Jan '14

Some XHCI controllers can request a significant chunk of reserved memory for scratch pad buffers. (At least one controller Intel Haswell based controller has been seen to request 64KiB.) Unused memory is returned after POST completes, so it should be okay to increase the maximum permanent high memory zone from 64K to 256K. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- I have pushed this to the xhci testing branch at: https://github.com/KevinOConnor/seabios/tree/xhci-testing --- src/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config.h b/src/config.h index 64e3c92..2fee0c7 100644 --- a/src/config.h +++ b/src/config.h @@ -17,7 +17,7 @@ // Maximum number of map entries in the e820 map #define BUILD_MAX_E820 32 // Space to reserve in high-memory for tables -#define BUILD_MAX_HIGHTABLE (64*1024) +#define BUILD_MAX_HIGHTABLE (256*1024) // Largest supported externaly facing drive id #define BUILD_MAX_EXTDRIVE 16 // Number of bytes the smbios may be and still live in the f-segment -- 1.8.3.1

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SeaBIOS xhci driver
by Kevin O'Connor 24 Jan '14

24 Jan '14

Hi Gerd, Have you had a chance to review the XHCI branch I've been testing? https://github.com/KevinOConnor/seabios/commits/xhci-testing Beyond a general review, I have a few questions on the XHCI code: 1 - It looks like usb-xhci.c is missing a copyright. Are you okay if I add one that looks like what you have on ahci.c? 2 - What is the mdelay(100) in configure_xhci() for? I don't understand the comment there. Also, any delay should probably be an msleep(), so that seabios can continue to bring up other devices. (An mdelay() doesn't let other threads run.) 3 - In the original code xhci_hub_disconnect() free'd the xhci slot for a device, but this doesn't look right to me as there can be more than one slot for a given port (in the case of a hub). The testing branch above never free's slots now - do you have any thoughts on how slot allocation/free'ing should be done? 4 - In the testing branch above, I added a patch to make hubs work (see "xhci: Hack to get hubs working."). This further overloads xhci_alloc_pipe() though. Do you think that is okay or do you think there is a better way to catch hub registration so that the xhci controller knows about it? -Kevin

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Latest SeaBIOS on Acer c720
by Kevin O'Connor 23 Jan '14

23 Jan '14

This is a quick status update on my attempts to run the latest SeaBIOS on the Acer c720 chromebook (aka Google peppy). In brief, the latest SeaBIOS runs well on the c720, and it also enables booting from SD cards (which oddly doesn't seem to work in the version of seabios shipped with the c720). At this point, I've only upgrading SeaBIOS. I haven't updated the version of coreboot in the c720. For those interested in reproducing, it will require the very latest seabios from the git repo. Because only a small portion of the flash is used for seabios and that portion is in a non-standard location, the new seabios CONFIG_CBFS_LOCATION config option needs to be set to 0xffe00000 and some additional steps are needed to build the final rom. I've attached a script with the steps I run to build and install seabios for the c720 (based on instructions from Stefan Reinauer). In some initial tests, I can install and run Fedora on the c720, but there are some quirks. Suspend/resume is quirky (very slow to resume), the touchpad isn't working (needs a driver), and the keyboard mappings seem to be a little quirky. I don't think this is seabios related though. Also, systems using syslinux for a boot loader don't like the fact that the c720 reserves chunks of memory under 16Meg (which requires setting an explicit "mem=1600m" in the kernel boot parameters), however that doesn't seem to be a problem once the OS in installed (and no longer uses syslinux). The seabios xhci testing branch does detect the xhci controller. However, the current c720 boot code maps all the xhci devices to an ehci controller. I'm going to see if I can convince the boot code to map the devices back to the xhci controller so that I can test the seabios code on the Haswell xhci controller. -Kevin

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Re: [SeaBIOS] [PATCH 1/3] debug: Add runtime option to not report the debug serial port to the OS.
by Kevin O'Connor 22 Jan '14

22 Jan '14

On Mon, Jan 20, 2014 at 12:33:00PM -0500, Kevin O'Connor wrote: > DOS resets the serial ports reported by the BIOS. This can mess up > debugging and timing when the serial baud rate changes on the debug > port. The new "etc/advertise-serial-debug-port" option allows one to > suppress the debug serial port from the normal list of serial ports > the BIOS reports to DOS. FYI, I have pushed the above series (as well as the encodeint.py, kconfig updates, and CBFS alternate location patches) to the seabios master repo. -Kevin

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[PATCH] smbios: catch zero-length strings
by Gerd Hoffmann 22 Jan '14

22 Jan '14

qemu may pass us zero-length strings for smbios fields, when starting qemu this way ... qemu -smbios type=1,version=,serial=test ... for example. Today we don't specifically handle them and simply append them to the string list. Therefore we get two string-terminating zeros in a row. Result is that we by accident create a end-of-entry marker in the middle of the entry. Fix this by handling zero-length strings like non-present strings. Cc: armbru(a)redhat.com Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/fw/smbios.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/fw/smbios.c b/src/fw/smbios.c index affb9be..d549329 100644 --- a/src/fw/smbios.c +++ b/src/fw/smbios.c @@ -133,20 +133,24 @@ get_external(int type, char **p, unsigned *nr_structs, do { \ size = get_field(type, offsetof(struct smbios_type_##type, \ field), end); \ - if (size > 0) { \ + if (size == 1) { \ + /* zero-length string, skip to avoid bogous end marker */ \ + p->field = 0; \ + } else if (size > 1) { \ end += size; \ + p->field = ++str_index; \ } else { \ memcpy(end, def, sizeof(def)); \ end += sizeof(def); \ + p->field = ++str_index; \ } \ - p->field = ++str_index; \ } while (0) #define load_str_field_or_skip(type, field) \ do { \ size = get_field(type, offsetof(struct smbios_type_##type, \ field), end); \ - if (size > 0) { \ + if (size > 1) { \ end += size; \ p->field = ++str_index; \ } else { \ -- 1.8.3.1

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[Patch] Force usage of Python 2 on systems with Python 3 as default
by Johannes Krampf 20 Jan '14

20 Jan '14

Hello SeaBIOS developers, I'm using SeaBIOS together with Coreboot and it works very well. Thank you for your great work! The compilation of coreboot is done on a system where /usr/bin/python refers to python3. This makes scripts in the Python2 dialect fail with a syntax error. Since afaik Ubuntu will use Python 3 as default in the next release a bigger number of people will be affected by this when compiling coreboot. According to PEP-394 (http://www.python.org/dev/peps/pep-0394/) systems are supposed to have a "python2" command which refers to Python 2. This is the case on the systems I've tested. (Note: I have not tested many enterprise distributions.) I *think* it should be safe to make the usage of python2 explicit and I've attached a patch to do so. The patch should be trivial, but please tell me if you require any adjustments. I will be happy to do them. Should you have reservations over this patch due to some older systems possibly not having "python2", I might also try to make the scripts compatible with both Python 2 and Python 3. Regards, Johannes P.S. Please be so kind as to CC me in any responses as I'm not subscribed to the list.

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[PATCH 3/3] debug: Unify the SeaBIOS debug version banner.
by Kevin O'Connor 20 Jan '14

20 Jan '14

Introduce debug_banner() and use it in all the places SeaBIOS version is displayed for debugging purposes. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/fw/coreboot.c | 2 +- src/fw/xen.c | 4 ++-- src/output.c | 6 ++++++ src/output.h | 1 + src/post.c | 2 +- 5 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 0f7bf8c..4ffc9b7 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -182,7 +182,7 @@ coreboot_preinit(void) struct cb_cbmem_ref *cbref = find_cb_subtable(cbh, CB_TAG_CBMEM_CONSOLE); if (cbref) { cbcon = (void*)(u32)cbref->cbmem_addr; - dprintf(1, "----- [ SeaBIOS %s ] -----\n", VERSION); + debug_banner(); dprintf(1, "Found coreboot cbmem console @ %llx\n", cbref->cbmem_addr); } diff --git a/src/fw/xen.c b/src/fw/xen.c index d5f5ed3..dd8e8af 100644 --- a/src/fw/xen.c +++ b/src/fw/xen.c @@ -71,8 +71,8 @@ void xen_preinit(void) if (strcmp(signature, "XenVMMXenVMM") == 0) { /* Set debug_io_port first, so the following messages work. */ DebugOutputPort = 0xe9; - dprintf(1, "SeaBIOS (version %s)\n\n", VERSION); - dprintf(1, "Found Xen hypervisor signature at %x\n", base); + debug_banner(); + dprintf(1, "\nFound Xen hypervisor signature at %x\n", base); if ((eax - base) < 2) panic("Insufficient Xen cpuid leaves. eax=%x at base %x\n", eax, base); diff --git a/src/output.c b/src/output.c index 06d42a2..994a1d6 100644 --- a/src/output.c +++ b/src/output.c @@ -26,6 +26,12 @@ struct putcinfo { * Debug output ****************************************************************/ +void +debug_banner(void) +{ + dprintf(1, "SeaBIOS (version %s)\n", VERSION); +} + // Write a character to debug port(s). static void debug_putc(struct putcinfo *action, char c) diff --git a/src/output.h b/src/output.h index 6601035..42a76b8 100644 --- a/src/output.h +++ b/src/output.h @@ -4,6 +4,7 @@ #include "types.h" // u32 // output.c +void debug_banner(void); void panic(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))) __noreturn; void printf(const char *fmt, ...) diff --git a/src/post.c b/src/post.c index ec3271e..b5cbdb8 100644 --- a/src/post.c +++ b/src/post.c @@ -319,7 +319,7 @@ handle_post(void) return; serial_debug_preinit(); - dprintf(1, "Start bios (version %s)\n", VERSION); + debug_banner(); // Check if we are running under Xen. xen_preinit(); -- 1.8.3.1

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[PATCH 2/3] debug: Only call serial_debug_preinit() at startup.
by Kevin O'Connor 20 Jan '14

20 Jan '14

The serial_debug_preinit() function disables serial interrupts so that the OS doesn't get confused by "transmit buffer empty" interrupts caused when seabios writes to the serial port. It's unnecessary paranoia to keep rechecking that interrupts are disabled. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/boot.c | 2 -- src/optionroms.c | 2 -- src/output.c | 7 ------- src/output.h | 1 - src/post.c | 3 ++- src/resume.c | 1 - vgasrc/vgainit.c | 3 ++- 7 files changed, 4 insertions(+), 15 deletions(-) diff --git a/src/boot.c b/src/boot.c index ad799f9..183f4f3 100644 --- a/src/boot.c +++ b/src/boot.c @@ -743,7 +743,6 @@ int BootSequence VARLOW = -1; void VISIBLE32FLAT handle_18(void) { - debug_preinit(); debug_enter(NULL, DEBUG_HDL_18); int seq = BootSequence + 1; BootSequence = seq; @@ -754,7 +753,6 @@ handle_18(void) void VISIBLE32FLAT handle_19(void) { - debug_preinit(); debug_enter(NULL, DEBUG_HDL_19); BootSequence = 0; do_boot(0); diff --git a/src/optionroms.c b/src/optionroms.c index 1ff73c4..93d9d2f 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -44,8 +44,6 @@ __callrom(struct rom_header *rom, u16 offset, u16 bdf) start_preempt(); farcall16big(&br); finish_preempt(); - - debug_preinit(); } // Execute a given option rom at the standard entry vector. diff --git a/src/output.c b/src/output.c index 1d882fa..06d42a2 100644 --- a/src/output.c +++ b/src/output.c @@ -26,13 +26,6 @@ struct putcinfo { * Debug output ****************************************************************/ -// Setup debugging port(s). -void -debug_preinit(void) -{ - serial_debug_preinit(); -} - // Write a character to debug port(s). static void debug_putc(struct putcinfo *action, char c) diff --git a/src/output.h b/src/output.h index a13d55b..6601035 100644 --- a/src/output.h +++ b/src/output.h @@ -4,7 +4,6 @@ #include "types.h" // u32 // output.c -void debug_preinit(void); void panic(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))) __noreturn; void printf(const char *fmt, ...) diff --git a/src/post.c b/src/post.c index ace6f4c..ec3271e 100644 --- a/src/post.c +++ b/src/post.c @@ -19,6 +19,7 @@ #include "hw/pic.h" // pic_setup #include "hw/ps2port.h" // ps2port_setup #include "hw/rtc.h" // rtc_write +#include "hw/serialio.h" // serial_debug_preinit #include "hw/usb.h" // usb_setup #include "hw/virtio-blk.h" // virtio_blk_setup #include "hw/virtio-scsi.h" // virtio_scsi_setup @@ -317,7 +318,7 @@ handle_post(void) if (!CONFIG_QEMU && !CONFIG_COREBOOT) return; - debug_preinit(); + serial_debug_preinit(); dprintf(1, "Start bios (version %s)\n", VERSION); // Check if we are running under Xen. diff --git a/src/resume.c b/src/resume.c index 9ad2e4f..e2ceef1 100644 --- a/src/resume.c +++ b/src/resume.c @@ -25,7 +25,6 @@ void VISIBLE16 handle_resume(void) { ASSERT16(); - debug_preinit(); int status = rtc_read(CMOS_RESET_CODE); rtc_write(CMOS_RESET_CODE, 0); dprintf(1, "In resume (status=%d)\n", status); diff --git a/vgasrc/vgainit.c b/vgasrc/vgainit.c index 7b01e03..13221fd 100644 --- a/vgasrc/vgainit.c +++ b/vgasrc/vgainit.c @@ -9,6 +9,7 @@ #include "bregs.h" // struct bregs #include "hw/pci.h" // pci_config_readw #include "hw/pci_regs.h" // PCI_VENDOR_ID +#include "hw/serialio.h" // serial_debug_preinit #include "output.h" // dprintf #include "std/optionrom.h" // struct pci_data #include "std/pmm.h" // struct pmmheader @@ -126,7 +127,7 @@ int HaveRunInit VAR16; void VISIBLE16 vga_post(struct bregs *regs) { - debug_preinit(); + serial_debug_preinit(); dprintf(1, "Start SeaVGABIOS (version %s)\n", VERSION); debug_enter(regs, DEBUG_VGA_POST); -- 1.8.3.1

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SeaBIOS January 2014