October 2010 - SeaBIOS - mail.coreboot.org

Re: [SeaBIOS] [Qemu-devel] SeaBIOS error with Juniper FreeBSD kernel

by Kevin O'Connor

On Sun, Feb 21, 2010 at 04:18:38PM -0700, Brandon Bennett wrote: > > On Sat, Feb 20, 2010 at 9:05 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > >> Should a kernel fail during boot, I'd suspect it doesn't like one of > >> the apm/pcibios callbacks, or it doesn't like one of the > >> smbios/mptable/acpi tables. You could try compiling the SeaBIOS code > >> (see http://seabios.org/Download ) and increasing the debugging by > >> modifying src/config.h. Specifically, you could increase > >> CONFIG_DEBUG_LEVEL, and set DEBUG_HDL_pcibios32 and DEBUG_HDL_apm to > >> 1. Also, you could try disabling some of the features to see if that > >> prevents the fault (eg, disabling CONFIG_ACPI / CONFIG_SMBIOS / > >> CONFIG_MPTABLE). > > > > I have narrowed it down to SMBIOS. If I disable CONFIG_SMBIOS the > image boots up fine. Gleb, have you seen this thread? Some of the recent changes to smbios that look like possible culprits are: Make SMBIOS table pass MS SVVP test Use MaxCountCPUs during building of per cpu tables. Add malloc_high/fseg() and rework bios table creation to use them. There were other changes, but the comments indicate they were only ports of changes already in bochs. I suppose it's also possible the lack of smbios is turning off some other feature in the guest (eg, acpi) that's the real culprit. -Kevin

8 years, 4 months

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[PATCH] support piix PAM registers in KVM

by Gleb Natapov

Without this BIOS fails to remap 0xf0000 memory from ROM to RAM so writes to F-segment modify ROM content instead of memory copy. Since QEMU does not reloads ROMs during reset on next boot modified copy of BIOS is used. Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 933ad86..0bf435d 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -99,10 +99,6 @@ static void i440fx_update_memory_mappings(PCII440FXState *d) int i, r; uint32_t smram, addr; - if (kvm_enabled()) { - /* FIXME: Support remappings and protection changes. */ - return; - } update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3); for(i = 0; i < 12; i++) { r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; -- Gleb.

8 years, 5 months

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ohci bulk?

by Jonathan A. Kollasch

Hi, http://www.seabios.org/pipermail/seabios/2010-March/000396.html Could anyone explain what the difficulty with OHCI bulk in 16-bit mode is before I spend a few hours discovering for myself? Jonathan Kollasch

9 years

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[PATCH v3 0/2] pciinit: fix overflow when bar allocation

by Isaku Yamahata

Changes v2 -> v3: - use [first, last] instead of [start, end) Changes v1 -> v2: - add comment. Patch description: This patch set fixes PCI bar allocation when bar overflow occured. I checked if pmm_alloc facility can be used, but it doesn't suit for pci bar allocation. So I resulted in new API, pci_region which encapsulates region allocation and overflow checks. The first patch introduces pci_region, and the second patch fixes the overflow case with pci_region. Isaku Yamahata (2): pci: introduce pci_region to manage pci io/memory/prefmemory regions. pciinit: use pci_region functions. Makefile | 3 +- src/pci_region.c | 77 ++++++++++++++++++++++++++++++++++ src/pciinit.c | 122 ++++++++++++++++++++++++++--------------------------- src/util.h | 29 +++++++++++++ 4 files changed, 168 insertions(+), 63 deletions(-) create mode 100644 src/pci_region.c

9 years

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[PATCH] fix virtio-blk failure after reboot

by Gleb Natapov

vring_virtqueue should be zeroed otherwise old values will be reused after reboot. Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/src/virtio-blk.c b/src/virtio-blk.c index 34d7863..7a25826 100644 --- a/src/virtio-blk.c +++ b/src/virtio-blk.c @@ -109,6 +109,7 @@ init_virtio_blk(u16 bdf) goto fail; } memset(vdrive_g, 0, sizeof(*vdrive_g)); + memset(vq, 0, sizeof(*vq)); vdrive_g->drive.type = DTYPE_VIRTIO; vdrive_g->drive.cntl_id = bdf; vdrive_g->vq = vq; -- Gleb.

9 years

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[PATCH] mark irq9 active high in DSDT

by Gleb Natapov

In PIIX4 SCI (irq9) is active high. Seabios marks it so in interrupt override table, but some OSes (FreeBSD) require the same information to be present in DSDT too. Make it so. Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index bb0a176..dafcf45 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -73,7 +73,7 @@ DefinitionBlock ( #define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB) prt_slot0(0x0000), /* Device 1 is power mgmt device, and can only use irq 9 */ - Package() { 0x0001ffff, 0, 0, 9 }, + Package() { 0x0001ffff, 0, LNKS, 0 }, Package() { 0x0001ffff, 1, LNKB, 0 }, Package() { 0x0001ffff, 2, LNKC, 0 }, Package() { 0x0001ffff, 3, LNKD, 0 }, @@ -634,6 +634,46 @@ DefinitionBlock ( Store (TMP, PRQ3) } } + Device(LNKS){ + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 5) + Name(_PRS, ResourceTemplate(){ + Interrupt (, Level, ActiveHigh, Shared) + { 9 } + }) + Method (_STA, 0, NotSerialized) + { + Store (0x0B, Local0) + If (And (0x80, PRQ0, Local1)) + { + Store (0x09, Local0) + } + Return (Local0) + } + Method (_DIS, 0, NotSerialized) + { + Or (PRQ0, 0x80, PRQ0) + } + Method (_CRS, 0, NotSerialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (, Level, ActiveHigh, Shared) + {9} + }) + CreateDWordField (PRR0, 0x05, TMP) + Store (PRQ0, Local0) + If (LLess (Local0, 0x80)) + { + Store (Local0, TMP) + } + Else + { + Store (Zero, TMP) + } + Return (PRR0) + } + } } /* -- Gleb.

9 years, 1 month

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Re: [SeaBIOS] [PATCH v2 2/2] pciinit: use pci_region functions.

by Michael S. Tsirkin

As a sepaate note, BIOS currently seems to allocate regions in-order, correct? A classical trick is to allocate regions behind each bridge in the reverse order of their size. This avoids holes due to alignment. -- MST

9 years, 1 month

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Re: [SeaBIOS] [PATCH v2 1/2] pci: introduce pci_region to manage pci io/memory/prefmemory regions.

by Michael S. Tsirkin

On Thu, Oct 28, 2010 at 02:04:05PM +0900, Isaku Yamahata wrote: > This patch adds helper functions to manage pci area. > > Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp> > > --- > Changes v1 -> v2 > - add comments > --- > Makefile | 3 +- > src/pci_region.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > src/util.h | 28 +++++++++++++++++++ > 3 files changed, 107 insertions(+), 1 deletions(-) > create mode 100644 src/pci_region.c > > diff --git a/Makefile b/Makefile > index 9d412f1..1663a5d 100644 > --- a/Makefile > +++ b/Makefile > @@ -19,7 +19,8 @@ SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \ > SRC16=$(SRCBOTH) system.c disk.c font.c > SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ > acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ > - lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c > + lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \ > + pci_region.c > SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c > > cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \ > diff --git a/src/pci_region.c b/src/pci_region.c > new file mode 100644 > index 0000000..c8656cb > --- /dev/null > +++ b/src/pci_region.c > @@ -0,0 +1,77 @@ > +// helper functions to manage pci io/memory/prefetch memory region > +// > +// Copyright (C) 2009 Isaku Yamahata <yamahata at valinux co jp> > +// > +// This file may be distributed under the terms of the GNU LGPLv3 license. > +// > +// > + > +#include "util.h" > + > +#define PCI_REGION_DISABLED (-1) > + > +void pci_region_init(struct pci_region *r, u32 start, u32 end) > +{ > + r->start = start; > + r->end = end; > + > + r->cur_end = start; > +} > + > +// PCI_REGION_DISABLED represents that the region is in special state. > +// its value is chosen such that cur_end can't be PCI_REGION_DISABLED normally. > +u32 pci_region_disable(struct pci_region *r) > +{ > + return r->cur_end = PCI_REGION_DISABLED; > +} > + > +static int pci_region_disabled(const struct pci_region *r) > +{ > + return r->cur_end == PCI_REGION_DISABLED; > +} > + > +static u32 pci_region_alloc_align(struct pci_region *r, u32 size, u32 align) > +{ > + if (pci_region_disabled(r)) { > + return 0; > + } > + > + u32 s = ALIGN(r->cur_end, align); > + if (s > r->end || s < r->cur_end) { > + return 0; > + } > + u32 e = s + size; > + if (e > r->end || e < s) { > + return 0; > + } > + r->cur_end = e; > + return s; > +} > + > +u32 pci_region_alloc(struct pci_region *r, u32 size) > +{ > + return pci_region_alloc_align(r, size, size); > +} > + > +u32 pci_region_align(struct pci_region *r, u32 align) > +{ > + return pci_region_alloc_align(r, 0, align); > +} > + > +void pci_region_revert(struct pci_region *r, u32 addr) > +{ > + r->cur_end = addr; > +} > + > +u32 pci_region_addr(const struct pci_region *r) > +{ > + if (pci_region_disabled(r)){ > + return r->end; > + } > + return r->cur_end; > +} > + > +u32 pci_region_size(const struct pci_region *r) > +{ > + return r->end - r->start; > +} > diff --git a/src/util.h b/src/util.h > index 5cc9f17..17eedd0 100644 > --- a/src/util.h > +++ b/src/util.h > @@ -344,6 +344,34 @@ void qemu_prep_reset(void); > void smm_save_and_copy(void); > void smm_relocate_and_restore(void); > > +// pci_region.c > +// region allocator. pci region allocates the requested region > +// sequentially with overflow check. > +struct pci_region { > + // The region is [start, region). [start end)? > + u32 start; > + u32 end; > + > + // The next allocation is start from this. > + // i.e. [start, cur_end) is allocated. > + // Right after initialization cur_end == start. > + u32 cur_end; What is the value for a region at 0xfffff000 and size 0x1000? Maybe first, last is better to detect this? > +}; > +// initialize the pci_region of [start, end) > +void pci_region_init(struct pci_region *r, u32 start, u32 end); > +// allocate the region of size > +u32 pci_region_alloc(struct pci_region *r, u32 size); > +// make the next allocation aligned to align > +u32 pci_region_align(struct pci_region *r, u32 align); > +// revert the allocation to addr. > +void pci_region_revert(struct pci_region *r, u32 addr); > +// make the allocation fail. > +u32 pci_region_disable(struct pci_region *r); > +// returns the current allocation point. > +u32 pci_region_addr(const struct pci_region *r); > +// returns the region size. > +u32 pci_region_size(const struct pci_region *r); > + > // pciinit.c > extern const u8 pci_irqs[4]; > void pci_bios_allocate_regions(u16 bdf, void *arg); > -- > 1.7.1.1

9 years, 1 month

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[PATCH v2 0/2] pciinit: fix overflow when bar allocation

by Isaku Yamahata

Okay, now added comments to members and functions as requested. No essential code change. Changes v1 -> v2: - add comment. Patch description: This patch set fixes PCI bar allocation when bar overflow occured. I checked if pmm_alloc facility can be used, but it doesn't suit for pci bar allocation. So I resulted in new API, pci_region which encapsulates region allocation and overflow checks. The first patch introduces pci_region, and the second patch fixes the overflow case with pci_region. Isaku Yamahata (2): pci: introduce pci_region to manage pci io/memory/prefmemory regions. pciinit: use pci_region functions. Makefile | 3 +- src/pci_region.c | 77 ++++++++++++++++++++++++++++++++++ src/pciinit.c | 122 ++++++++++++++++++++++++++--------------------------- src/util.h | 28 ++++++++++++ 4 files changed, 167 insertions(+), 63 deletions(-) create mode 100644 src/pci_region.c

9 years, 1 month

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Re: [SeaBIOS] [Qemu-devel] [PATCH 1/2] pci: Automatically patch PCI device id in PCI ROM

by Anthony Liguori

On 10/15/2010 03:51 PM, Stefan Weil wrote: > PCI device with different device ids sometimes share > the same rom code. Only the device id and the checksum > differ in a boot rom for such devices. > BTW, SeaBIOS doesn't reject ROMs when they're loaded via rombar, only when they're loaded via romfile. Maybe it's better to use fw_cfg to explicitly tell SeaBIOS to ignore the PCI device id in the rom header for a certain device? Regards, Anthony Liguori > The i825xx ethernet controller family is a typical example > which is implemented in hw/eepro100.c. It uses at least > 3 different device ids, so normally 3 boot roms would be needed. > > By automatically patching the device id (and the checksum) > in qemu, all emulated family members can share the same > boot rom. > > Cc: Markus Armbruster<armbru(a)redhat.com> > Cc: Michael S. Tsirkin<mst(a)redhat.com> > Signed-off-by: Stefan Weil<weil(a)mail.berlios.de> > --- > hw/pci.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 53 insertions(+), 0 deletions(-) > > diff --git a/hw/pci.c b/hw/pci.c > index 1280d4d..c1f8218 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -1797,6 +1797,57 @@ static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, p > cpu_register_physical_memory(addr, size, pdev->rom_offset); > } > > +/* Patch the PCI device id in a PCI rom image if necessary. > + This is needed for an option rom which is used for more than one device. */ > +static void pci_patch_device_id(PCIDevice *pdev, uint8_t *ptr, int size) > +{ > + uint16_t vendor_id; > + uint16_t device_id; > + uint16_t rom_vendor_id; > + uint16_t rom_device_id; > + uint16_t rom_magic; > + uint16_t pcir_offset; > + > + /* Words in rom data are little endian (like in PCI configuration), > + so they can be read / written with pci_get_word / pci_set_word. */ > + > + /* Only a valid rom will be patched. */ > + rom_magic = pci_get_word(ptr); > + if (rom_magic != 0xaa55) { > + PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); > + return; > + } > + pcir_offset = pci_get_word(ptr + 0x18); > + if (pcir_offset + 8>= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { > + PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); > + return; > + } > + > + vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); > + device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); > + rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); > + rom_device_id = pci_get_word(ptr + pcir_offset + 6); > + > + /* Don't patch a rom with wrong vendor id (might be changed if needed). */ > + if (vendor_id != rom_vendor_id) { > + return; > + } > + > + PCI_DPRINTF("ROM id %04x%04x / PCI id %04x%04x\n", > + vendor_id, device_id, rom_vendor_id, rom_device_id); > + > + if (device_id != rom_device_id) { > + /* Patch device id and checksum (at offset 6 for etherboot roms). */ > + uint8_t checksum; > + checksum = ptr[6]; > + checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id>> 8); > + checksum -= (uint8_t)device_id + (uint8_t)(device_id>> 8); > + PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); > + ptr[6] = checksum; > + pci_set_word(ptr + pcir_offset + 6, device_id); > + } > +} > + > /* Add an option rom for the device */ > static int pci_add_option_rom(PCIDevice *pdev) > { > @@ -1849,6 +1900,8 @@ static int pci_add_option_rom(PCIDevice *pdev) > load_image(path, ptr); > qemu_free(path); > > + pci_patch_device_id(pdev, ptr, size); > + > pci_register_bar(pdev, PCI_ROM_SLOT, size, > 0, pci_map_option_rom); > >

9 years, 1 month

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SeaBIOS October 2010