[PATCH 0/3] Patches for baytrail based chromebooks
by Kevin O'Connor
This series enables seabios to run on some Baytrail CPU based
chromebooks. At least some of these machines do not support routing
of legacy interrupts and at least some have SDHCI controllers that do
not appear as regular PCI devices. This series is mainly a hack to
get some minimal support on the hardware.
This series is also available at:
https://github.com/KevinOConnor/seabios/tree/baytrail-testing
-Kevin
Kevin O'Connor (3):
Add minimal support for machines without hardware interrupts
ps2: Eliminate "etc/ps2-poll-only"; use CONFIG_HARDWARE_IRQ instead
sdcard: Allow sdcard addresses to be specified in CBFS files
docs/Runtime_config.md | 2 +-
src/Kconfig | 13 ++++++++++++-
src/clock.c | 31 +++++++++++++++++++++++++------
src/hw/pic.c | 14 ++++++++++++++
src/hw/pic.h | 4 ++++
src/hw/ps2port.c | 16 ++++++----------
src/hw/sdcard.c | 48 ++++++++++++++++++++++++++++++++++++------------
src/hw/timer.c | 2 ++
src/stacks.c | 5 ++++-
src/util.h | 1 +
10 files changed, 105 insertions(+), 31 deletions(-)
--
1.9.3
3 years, 2 months
[PATCH 1/2] Consolidate code16*() functions
by Kevin O'Connor
Introduce code16_override() for cases where call16() should not
restore the previous 16bit state. All callers now use call16_back()
to invoke 16bit code, so rename call16_back() to call16().
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/stacks.c | 61 +++++++++++++++++++++++++++---------------------------------
1 file changed, 27 insertions(+), 34 deletions(-)
diff --git a/src/stacks.c b/src/stacks.c
index 850a335..a156138 100644
--- a/src/stacks.c
+++ b/src/stacks.c
@@ -92,7 +92,23 @@ call32_post(void)
return method;
}
-// 16bit handler code called from call16_back() / call16_smm()
+// Force next call16() to restore to a pristine cpu environment state
+static void
+call16_override(int big)
+{
+ ASSERT32FLAT();
+ if (getesp() > BUILD_STACK_ADDR)
+ panic("call16_override with invalid stack\n");
+ memset(&Call16Data, 0, sizeof(Call16Data));
+ if (big) {
+ Call16Data.method = C16_BIG;
+ Call16Data.a20 = 1;
+ } else {
+ Call16Data.a20 = !CONFIG_DISABLE_A20;
+ }
+}
+
+// 16bit handler code called from call16() / call16_smm()
u32 VISIBLE16
call16_helper(u32 eax, u32 edx, u32 (*func)(u32 eax, u32 edx))
{
@@ -243,11 +259,11 @@ call32(void *func, u32 eax, u32 errret)
// Call a 16bit SeaBIOS function, restoring the mode from last call32().
static u32
-call16_back(u32 eax, u32 edx, void *func)
+call16(u32 eax, u32 edx, void *func)
{
ASSERT32FLAT();
if (getesp() > MAIN_STACK_MAX)
- panic("call16_back with invalid stack\n");
+ panic("call16 with invalid stack\n");
if (CONFIG_CALL32_SMM && Call16Data.method == C16_SMM)
return call16_smm(eax, edx, func);
@@ -283,31 +299,6 @@ call16_back(u32 eax, u32 edx, void *func)
return eax;
}
-// Call a 16bit SeaBIOS function in regular ("non-big") mode.
-static u32
-call16(u32 eax, u32 edx, void *func)
-{
- ASSERT32FLAT();
- if (getesp() > BUILD_STACK_ADDR)
- panic("call16 with invalid stack\n");
- memset(&Call16Data, 0, sizeof(Call16Data));
- Call16Data.a20 = !CONFIG_DISABLE_A20;
- return call16_back(eax, edx, func);
-}
-
-// Call a 16bit SeaBIOS function in "big real" mode.
-static u32
-call16big(u32 eax, u32 edx, void *func)
-{
- ASSERT32FLAT();
- if (getesp() > BUILD_STACK_ADDR)
- panic("call16big with invalid stack\n");
- memset(&Call16Data, 0, sizeof(Call16Data));
- Call16Data.method = C16_BIG;
- Call16Data.a20 = 1;
- return call16_back(eax, edx, func);
-}
-
/****************************************************************
* Extra 16bit stack
@@ -362,7 +353,7 @@ u32
stack_hop_back(u32 eax, u32 edx, void *func)
{
if (!MODESEGMENT)
- return call16_back(eax, edx, func);
+ return call16(eax, edx, func);
if (!MODE16 || !on_extra_stack())
return ((u32 (*)(u32, u32))func)(eax, edx);
ASSERT16();
@@ -414,18 +405,20 @@ _farcall16(struct bregs *callregs, u16 callregseg)
: "ebx", "ecx", "esi", "edi", "cc", "memory");
}
+// Invoke external 16bit code.
void
farcall16(struct bregs *callregs)
{
- extern void _cfunc16__farcall16(void);
- call16((u32)callregs, 0, _cfunc16__farcall16);
+ call16_override(0);
+ _farcall16(callregs, 0);
}
+// Invoke external 16bit code in "big real" mode.
void
farcall16big(struct bregs *callregs)
{
- extern void _cfunc16__farcall16(void);
- call16big((u32)callregs, 0, _cfunc16__farcall16);
+ call16_override(1);
+ _farcall16(callregs, 0);
}
// Invoke a 16bit software interrupt.
@@ -448,7 +441,7 @@ reset(void)
{
extern void reset_vector(void) __noreturn;
if (!MODE16)
- call16_back(0, 0, reset_vector);
+ call16(0, 0, reset_vector);
reset_vector();
}
--
2.4.3
3 years, 3 months
[RFC PATCH] x86: Support booting SeaBIOS
by Bin Meng
SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
It can run in an emulator or natively on X86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.
As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload. No U-Boot native support there.
Booting SeaBIOS is done via U-Boot's bootelf command.
This is the initial attempt to support booting SeaBIOS from U-Boot.
If the basic concept is good, I can spend time working on follow-on
patches to enable BIOS tables as well as graphics support. One issue
is that U-Boot x86 does not has a ROM file system like coreboot.
This brings difficulities to pass PCI option ROM to SeaBIOS, if we
don't modify SeaBIOS's source codes. Maybe we should promote CBFS
in U-Boot x86?
This is tested on an Intel Crown Bay board with VGA card, booting
SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel
finally.
Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com>
---
arch/x86/Kconfig | 10 ++++++++++
arch/x86/include/asm/tables.h | 29 +++++++++++++++++++++++++++++
arch/x86/lib/tables.c | 39 +++++++++++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5e42d7d..b432ff8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -401,6 +401,16 @@ config PCIE_ECAM_SIZE
so a default 0x10000000 size covers all of the 256 buses which is the
maximum number of PCI buses as defined by the PCI specification.
+config SEABIOS
+ bool "Support booting SeaBIOS"
+ help
+ SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
+ It can run in an emulator or natively on X86 hardware with the use
+ of coreboot/U-Boot. By turning on this option, U-Boot prepares
+ all the configuration tables that are necessary to boot SeaBIOS.
+
+ Check http://www.seabios.org/SeaBIOS for details.
+
source "arch/x86/lib/efi/Kconfig"
endmenu
diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
index 0aa6d9b..a083cac 100644
--- a/arch/x86/include/asm/tables.h
+++ b/arch/x86/include/asm/tables.h
@@ -7,6 +7,32 @@
#ifndef _X86_TABLES_H_
#define _X86_TABLES_H_
+#ifdef CONFIG_SEABIOS
+
+#define CB_TAG_MEMORY 1
+
+struct cb_header {
+ u8 signature[4];
+ u32 header_bytes;
+ u32 header_checksum;
+ u32 table_bytes;
+ u32 table_checksum;
+ u32 table_entries;
+};
+
+struct cb_memory_range {
+ u64 start;
+ u64 size;
+ u32 type;
+};
+
+struct cb_memory {
+ u32 tag;
+ u32 size;
+ struct cb_memory_range map[0];
+};
+#endif
+
/*
* All x86 tables happen to like the address range from 0xf0000 to 0x100000.
* We use 0xf0000 as the starting address to store those tables, including
@@ -14,6 +40,9 @@
*/
#define ROM_TABLE_ADDR 0xf0000
+/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
+#define CB_TABLE_ADDR 0x800
+
/**
* table_compute_checksum() - Compute a table checksum
*
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index f15b2e2..5849b2f 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -9,6 +9,7 @@
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/acpi_table.h>
+#include <asm/e820.h>
u8 table_compute_checksum(void *v, int len)
{
@@ -36,6 +37,41 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad)
dest[i] = pad;
}
+#ifdef CONFIG_SEABIOS
+static u32 write_cb_tables(u32 addr)
+{
+ struct cb_header *cbh = (struct cb_header *)addr;
+ struct cb_memory *mem;
+ struct cb_memory_range *map;
+ struct e820entry entry[32];
+ int num, i;
+
+ memset(cbh, 0, sizeof(struct cb_header));
+ strncpy((char *)cbh->signature, "LBIO", 4);
+ cbh->header_bytes = sizeof(struct cb_header);
+
+ /* populate memory map table */
+ mem = (struct cb_memory *)(cbh + 1);
+ mem->tag = CB_TAG_MEMORY;
+ map = mem->map;
+ num = install_e820_map(32, entry);
+ for (i = 0; i < num; i++) {
+ map->start = entry[i].addr;
+ map->size = entry[i].size;
+ map->type = entry[i].type;
+ map++;
+ }
+ mem->size = num * sizeof(struct cb_memory_range) + 8;
+
+ cbh->table_bytes = mem->size;
+ cbh->table_checksum = compute_ip_checksum(mem, cbh->table_bytes);
+ cbh->table_entries = 1;
+ cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes);
+
+ return (u32)map;
+}
+#endif
+
void write_tables(void)
{
u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR;
@@ -56,4 +92,7 @@ void write_tables(void)
rom_table_end = write_acpi_tables(rom_table_end);
rom_table_end = ALIGN(rom_table_end, 1024);
#endif
+#ifdef CONFIG_SEABIOS
+ write_cb_tables(CB_TABLE_ADDR);
+#endif
}
--
1.8.2.1
3 years, 3 months
SeaBIOS PAE experiment
by Kevin O'Connor
I was curious to see if SeaBIOS could run its 32bit code with PAE
paging enabled. So, I put together some test code, and so far it
seems to work.
The patch below changes "transition32" to always enable PAE (if PAE
has been detected as available). This means that all SeaBIOS 32bit
"flat mode" code will end up running with paging enabled. Even the
SMI handlers run with it on. The code is also available at:
https://github.com/KevinOConnor/seabios/tree/testing
The test code currently just creates an "identity mapping" of all
memory in the first 4GB. However, it should be possible to setup page
table entries to enable access to all ram/device memory - even above
4GB.
I don't plan to commit the patch in its current state. In order for
it to be useful, the identity mapping would need to be replaced with
something more dynamic. That would likely require updating all the
seabios driver code to use "ioremap()" before accessing any device
memory.
Some further notes:
* The reason why PAE is interesting (instead of standard i386 paging)
is that it allows for 64bit mappings and because one can set it up
with just a single level page directory of 2MB pages. The single
level page directory makes maintaining it much easier.
* Since SeaBIOS doesn't touch much memory in practice, I think it
would be possible to implement an ioremap() with a simple hashing
scheme. That way, ioremap() wouldn't need any more storage beyond
the 16KB page directory itself.
* The SeaBIOS' malloc code could also be updated to remap pages which
would make it possible for it to relocate itself above 4GB and to
store data above 4GB. That's likely not all that useful, but I
think it would be a little amusing for a 16bit bios to fully support
64bit memory.
* I haven't done any performance tests. It's unclear what the
performance impact of enabling paging on every 32bit entry point
would be.
-Kevin
commit 6ffd9a0b0852c83850cc531a97d3f576bfc93e21
Author: Kevin O'Connor <kevin(a)koconnor.net>
Date: Mon Sep 28 13:55:29 2015 -0400
Experimental support for PAE paging
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
diff --git a/Makefile b/Makefile
index 3a0d2e8..4ee5eb4 100644
--- a/Makefile
+++ b/Makefile
@@ -37,7 +37,7 @@ SRCBOTH=misc.c stacks.c output.c string.c block.c cdrom.c disk.c mouse.c kbd.c \
hw/lsi-scsi.c hw/esp-scsi.c hw/megasas.c
SRC16=$(SRCBOTH)
SRC32FLAT=$(SRCBOTH) post.c memmap.c malloc.c romfile.c x86.c optionroms.c \
- pmm.c font.c boot.c bootsplash.c jpeg.c bmp.c tcgbios.c sha1.c \
+ pmm.c font.c boot.c bootsplash.c jpeg.c bmp.c tcgbios.c sha1.c paging.c \
hw/ahci.c hw/pvscsi.c hw/usb-xhci.c hw/usb-hub.c hw/sdcard.c \
fw/coreboot.c fw/lzmadecode.c fw/multiboot.c fw/csm.c fw/biostables.c \
fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c fw/xen.c \
diff --git a/src/Kconfig b/src/Kconfig
index b873cd3..c28f671 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -122,6 +122,13 @@ endchoice
selected, the memory is instead allocated from the
"9-segment" (0x90000-0xa0000).
+ config PAGING
+ bool "PAE paging support"
+ default y
+ help
+ Enable paging in 32bit mode on processors that support PAE
+ paging.
+
config ROM_SIZE
int "ROM size (in KB)"
default 0
diff --git a/src/paging.c b/src/paging.c
new file mode 100644
index 0000000..022fad0
--- /dev/null
+++ b/src/paging.c
@@ -0,0 +1,63 @@
+// CPU page table support
+//
+// Copyright (C) 2015 Kevin O'Connor <kevin(a)koconnor.net>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "malloc.h" // memalign_high
+#include "memmap.h" // PAGE_SIZE
+#include "output.h" // dprintf
+#include "x86.h" // cpuid
+
+u32 PageDirPtr VARFSEG;
+
+#define PAE_MAP_SIZE (2*1024*1024)
+
+#define PG_P (1<<0)
+#define PG_RW (1<<1)
+#define PG_PS (1<<7)
+
+static void
+fill_page_directory(u64 *dir)
+{
+ // Build dummy identity mapping for first 4GB
+ u32 i;
+ for (i=0; i<2048; i++)
+ dir[i] = i*PAE_MAP_SIZE | PG_P | PG_RW | PG_PS;
+}
+
+// Detect PAE support and enable it if present
+void
+paging_preinit(void)
+{
+ if (!CONFIG_PAGING)
+ return;
+ // Check if CPU supports PAE
+ u32 eax, ebx, ecx, edx, cpuid_features = 0;
+ cpuid(0, &eax, &ebx, &ecx, &edx);
+ if (!eax)
+ return;
+ cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
+ if (!(eax & (1<<6)))
+ return;
+
+ dprintf(1, "PAE support found\n");
+ u64 *pdp = malloc_high(sizeof(u64)*4);
+ u64 *dir = memalign_high(PAGE_SIZE, sizeof(u64)*2048);
+ if (!pdp || !dir) {
+ warn_noalloc();
+ free(pdp);
+ free(dir);
+ return;
+ }
+ int i;
+ for (i=0; i<4; i++)
+ pdp[i] = ((u32)dir + i*4096) | PG_P;
+ fill_page_directory(dir);
+
+ // Enable PAE
+ PageDirPtr = (u32)pdp;
+ cr3_write(PageDirPtr);
+ cr4_mask(0, CR4_PAE);
+ cr0_mask(0, CR0_PG);
+}
diff --git a/src/post.c b/src/post.c
index e19b06c..d0f52fe 100644
--- a/src/post.c
+++ b/src/post.c
@@ -315,6 +315,7 @@ dopost(void)
qemu_preinit();
coreboot_preinit();
malloc_preinit();
+ paging_preinit();
// Relocate initialization code and call maininit().
reloc_preinit(maininit, NULL);
diff --git a/src/romlayout.S b/src/romlayout.S
index 823188b..3545612 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -51,12 +51,26 @@ transition32_nmi_off:
orl $CR0_PE, %ecx
movl %ecx, %cr0
+#if CONFIG_PAGING
+ movl %cs:PageDirPtr, %ecx
+ cmpl $0, %ecx
+ jz 1f
+ // Enable PAE paging
+ movl %ecx, %cr3
+ movl %cr4, %ecx
+ orl $CR4_PAE, %ecx
+ movl %ecx, %cr4
+ movl %cr0, %ecx
+ orl $CR0_PG, %ecx
+ movl %ecx, %cr0
+#endif
+
// start 32bit protected mode code
- ljmpl $SEG32_MODE32_CS, $(BUILD_BIOS_ADDR + 1f)
+1: ljmpl $SEG32_MODE32_CS, $(BUILD_BIOS_ADDR + 2f)
.code32
// init data segments
-1: movl $SEG32_MODE32_DS, %ecx
+2: movl $SEG32_MODE32_DS, %ecx
movw %cx, %ds
movw %cx, %es
movw %cx, %ss
@@ -97,14 +111,25 @@ transition16big:
.code16
// Disable protected mode
1: movl %cr0, %ecx
- andl $~CR0_PE, %ecx
+ andl $~(CR0_PE|CR0_PG), %ecx
movl %ecx, %cr0
+#if CONFIG_PAGING
+ cmpl $0, %cs:PageDirPtr
+ jz 2f
+ // Disable PAE paging
+ movl %cr4, %ecx
+ andl $~CR4_PAE, %ecx
+ movl %ecx, %cr4
+ xorl %ecx, %ecx
+ movl %ecx, %cr3
+#endif
+
// far jump to flush CPU queue after transition to real mode
- ljmpw $SEG_BIOS, $2f
+2: ljmpw $SEG_BIOS, $3f
// restore IDT to normal real-mode defaults
-2: lidtw %cs:rmode_IDT_info
+3: lidtw %cs:rmode_IDT_info
// Clear segment registers
xorw %cx, %cx
diff --git a/src/stacks.c b/src/stacks.c
index fa9c7db..555a2f5 100644
--- a/src/stacks.c
+++ b/src/stacks.c
@@ -28,7 +28,7 @@ struct {
u8 cmosindex;
u8 a20;
u16 ss, fs, gs;
- u32 cr0;
+ u32 cr0, cr3, cr4;
struct descloc_s gdt;
} Call16Data VARLOW;
@@ -48,6 +48,10 @@ call32_prep(u8 method)
// Called in 16bit protected mode?!
return -1;
SET_LOW(Call16Data.cr0, cr0);
+ if (CONFIG_PAGING && GET_GLOBAL(PageDirPtr)) {
+ SET_LOW(Call16Data.cr3, cr3_read());
+ SET_LOW(Call16Data.cr4, cr4_read());
+ }
// Backup fs/gs and gdt
SET_LOW(Call16Data.fs, GET_SEG(FS));
@@ -98,6 +102,14 @@ call32_post(void)
u32 cr0_caching = GET_LOW(Call16Data.cr0) & (CR0_CD|CR0_NW);
if (cr0_caching)
cr0_mask(CR0_CD|CR0_NW, cr0_caching);
+ if (CONFIG_PAGING && GET_GLOBAL(PageDirPtr)) {
+ u32 cr4_pae = GET_LOW(Call16Data.cr4) & CR4_PAE;
+ if (cr4_pae)
+ cr4_mask(CR4_PAE, cr4_pae);
+ u32 cr3 = GET_LOW(Call16Data.cr3);
+ if (cr3)
+ cr3_write(cr3);
+ }
}
// Restore cmos index register
diff --git a/src/util.h b/src/util.h
index 327abeb..25a03ce 100644
--- a/src/util.h
+++ b/src/util.h
@@ -203,6 +203,10 @@ void vgarom_setup(void);
void s3_resume_vga(void);
extern int ScreenAndDebug;
+// paging.c
+extern u32 PageDirPtr;
+void paging_preinit(void);
+
// pcibios.c
void handle_1ab1(struct bregs *regs);
void bios32_init(void);
diff --git a/src/x86.h b/src/x86.h
index 19d404f..b9b256d 100644
--- a/src/x86.h
+++ b/src/x86.h
@@ -14,6 +14,8 @@
#define CR0_NW (1<<29) // Not Write-through
#define CR0_PE (1<<0) // Protection enable
+#define CR4_PAE (1<<5)
+
// PORT_A20 bitdefs
#define PORT_A20 0x0092
#define A20_ENABLE_BIT 0x02
@@ -92,6 +94,27 @@ static inline u16 cr0_vm86_read(void) {
return cr0;
}
+static inline u32 cr3_read(void) {
+ u32 cr3;
+ asm("movl %%cr3, %0" : "=r"(cr3));
+ return cr3;
+}
+static inline void cr3_write(u32 cr3) {
+ asm("movl %0, %%cr3" : : "r"(cr3));
+}
+
+static inline u32 cr4_read(void) {
+ u32 cr4;
+ asm("movl %%cr4, %0" : "=r"(cr4));
+ return cr4;
+}
+static inline void cr4_write(u32 cr4) {
+ asm("movl %0, %%cr4" : : "r"(cr4));
+}
+static inline void cr4_mask(u32 off, u32 on) {
+ cr4_write((cr4_read() & ~off) | on);
+}
+
static inline u64 rdmsr(u32 index)
{
u64 ret;
3 years, 3 months
[RFC 0/3] NVDIMM booting support
by Marc Marí
Implement support for booting from a PMEM region compatible with NVDIMM and
NFIT specifications.
The current implementation is still slow. When running a Linux guest on top of
QEMU in x86:
Using actual -kernel option:
QEMU startup time: .080
BIOS startup time: .060
Kernel setup time: .590
Total time: .730
Using -kernel option and fw_cfg DMA patch:
QEMU startup time: .080
BIOS startup time: .039
Kernel setup time: .002
Total time: .121
Using this patch series and adding the vmlinuz as a NVDIMM device:
QEMU startup time: .080
BIOS startup time: .065
Kernel setup time: .015
Total time: .160
This patch series is not ready for merging. There are things missing and
questions to be answered:
- Is it necessary to retrieve any other data from the NVDIMM?
- Is there any other nicer (and faster) option for the page table?
- Make NVDIMM a compile-time option, as the other devices.
- Add some kind of wrapper to the boot files instead of a direct vmlinux.
- Add NVDIMM boot priority support.
- Add support for intitrd and cmdline. Maybe in another NVDIMM, or in the
same, or through fw_cfg.
- Reorder code to change to long mode less times.
Any other proposals for improvements are appreciated
Marc Marí (3):
Basic NVDIMM PMEM support
Transitions to and from 64 bits
Add NVDIMM booting support
Makefile | 3 +-
src/boot.c | 18 ++++++++
src/config.h | 2 +
src/fw/biostables.c | 80 ++++++++++++++++++++++++++++++++
src/hw/nvdimm.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++++++++
src/hw/nvdimm.h | 12 +++++
src/misc.c | 4 ++
src/post.c | 2 +
src/romlayout.S | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++
src/stacks.c | 77 +++++++++++++++++++++++++++++++
src/stacks.h | 2 +
src/std/acpi.h | 40 ++++++++++++++++
src/util.h | 3 ++
src/x86.h | 1 +
14 files changed, 497 insertions(+), 1 deletion(-)
create mode 100644 src/hw/nvdimm.c
create mode 100644 src/hw/nvdimm.h
--
2.4.3
3 years, 3 months
QEMU fw_cfg DMA interface
by Marc Marí
Implementation of the FW CFG DMA interface.
When running a Linux guest on top of QEMU, using the -kernel options, this
is the timing improvement for x86:
QEMU commit 16a1b6e and SeaBIOS commit e4d2b8c
QEMU startup time: .080
BIOS startup time: .060
Kernel setup time: .586
Total time: .726
QEMU with this patch series and SeaBIOS with this patch series
QEMU startup time: .080
BIOS startup time: .039
Kernel setup time: .002
Total time: .121
QEMU startup time is the time between the start and the first kvm_entry.
BIOS startup time is the time between the first kvm_entry and the start of
function do_boot, in SeaBIOS.
Kernel setup time is the time between the start of the function do_boot in
SeaBIOS and the jump to the Linux kernel.
As you can see, both the BIOS (because of ACPI tables and other configurations)
and the Linux kernel boot (because of the copy to memory) are greatly
improved with this new interface.
Also, this new interface is an addon to the old interface. Both interfaces
are compatible and interchangeable.
Changes from v1:
- Take into account order of fields in the FWCfgDmaAccess structure
- Check and change endianness of FWCfgDmaAccess fields
- Change order of fields in the FWCfgDmaAccess structure
- Add FW_CFG_DMA_CTL_SKIP feature for control field
- Split FW_CFG_SIZE in QEMU
- Make FW_CFG_ID a bitmap of features
- Add 64 bit address support for the transfer. Trigger when writing the low
address, and address is 0 by default and at the end of each transfer.
- Align ports and addresses.
- Preserve old fw_cfg_comb_valid behaviour in QEMU
- Update documentation to reflect all these changes
Changes from v2:
- Make IOports fw_cfg DMA region a different IO region.
- Reuse everything for MMIO and IOport DMA regions
- Make transfer status only based on control field
- Use DMA helpers instead of direct map/unmap
- Change ARM fw_cfg DMA address space
- Change Linux boot process to match linuxboot.S
- Add select capabilities in the FWCfgDmaAccess struct
- Update documentation to reflect all these changes
3 years, 4 months
[PATCH 0/5] Simplify 16bit/32bit trampoline code
by Kevin O'Connor
This series simplifies some of the existing trampoline code.
-Kevin
Kevin O'Connor (5):
Unify smm/sloppy variants of call32_prep/post and call16_helper
Rename Call32Data to Call16Data
Unify inline assembler in variants of call16 functions
Unify call32_sloppy() and call32()
Use transition32_nmi_off from call32() and call16_back()
src/romlayout.S | 10 +-
src/stacks.c | 282 +++++++++++++++++++++-----------------------------------
2 files changed, 106 insertions(+), 186 deletions(-)
--
2.4.3
3 years, 4 months
Version of master behind stable branch versions
by Paul Menzel
Dear SeaBIOS folks,
building SeaBIOS from master, the version string shows 1.8.0-…, which
is more current than the rel-1.8.0-148-g75cb2b9 release. This is
confusing.
Should the stable branches be merged back into the master branch to get
a less confusing behavior? Or is there a different way to handle this?
Thanks,
Paul
3 years, 4 months
[PATCH] build: use -fstack-check=no when available
by Mike Frysinger
From: Magnus Granberg <zorry(a)gentoo.org>
Some compilers default this option to on which leads to build failures:
src/stacks.c: In function 'call16_back':
src/stacks.c:139:5: error: 'asm' operand has impossible constraints
asm volatile(
^
URL: https://bugs.gentoo.org/559980
Reported-by: Alon Bar-Lev <alonbl(a)gentoo.org>
Signed-off-by: Magnus Granberg <zorry(a)gentoo.org>
Signed-off-by: Mike Frysinger <vapier(a)gentoo.org>
---
Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/Makefile b/Makefile
index e287530..3a0d2e8 100644
--- a/Makefile
+++ b/Makefile
@@ -63,6 +63,7 @@ COMMONCFLAGS := -I$(OUT) -Isrc -Os -MD -g \
COMMONCFLAGS += $(call cc-option,$(CC),-nopie,)
COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector,)
COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector-all,)
+COMMONCFLAGS += $(call cc-option,$(CC),-fstack-check=no,)
COMMA := ,
CFLAGS32FLAT := $(COMMONCFLAGS) -DMODE16=0 -DMODESEGMENT=0
--
2.5.1
3 years, 4 months
[PATCH] Simplify transition16/32 assembler code
by Kevin O'Connor
Backup and restore %eax only around code that needs to use %eax.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/romlayout.S | 89 ++++++++++++++++++++++++++-------------------------------
1 file changed, 40 insertions(+), 49 deletions(-)
diff --git a/src/romlayout.S b/src/romlayout.S
index 7938e22..d78737b 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -22,18 +22,13 @@
// %edx = return location (in 32bit mode)
// Clobbers: ecx, flags, segment registers, cr0, idt/gdt
DECLFUNC transition32
-transition32_nmi_off:
- // transition32 when NMI and A20 are already initialized
- movl %eax, %ecx
- jmp 1f
transition32:
- movl %eax, %ecx
-
// Disable irqs (and clear direction flag)
cli
cld
// Disable nmi
+ movl %eax, %ecx
movl $CMOS_RESET_CODE|NMI_DISABLE_BIT, %eax
outb %al, $PORT_CMOS_INDEX
inb $PORT_CMOS_DATA, %al
@@ -42,29 +37,30 @@ transition32:
inb $PORT_A20, %al
orb $A20_ENABLE_BIT, %al
outb %al, $PORT_A20
+ movl %ecx, %eax
+transition32_nmi_off:
// Set segment descriptors
-1: lidtw %cs:pmode_IDT_info
+ lidtw %cs:pmode_IDT_info
lgdtw %cs:rombios32_gdt_48
// Enable protected mode
- movl %cr0, %eax
- orl $CR0_PE, %eax
- movl %eax, %cr0
+ movl %cr0, %ecx
+ orl $CR0_PE, %ecx
+ movl %ecx, %cr0
// start 32bit protected mode code
- ljmpl $SEG32_MODE32_CS, $(BUILD_BIOS_ADDR + 2f)
+ ljmpl $SEG32_MODE32_CS, $(BUILD_BIOS_ADDR + 1f)
.code32
// init data segments
-2: movl $SEG32_MODE32_DS, %eax
- movw %ax, %ds
- movw %ax, %es
- movw %ax, %ss
- movw %ax, %fs
- movw %ax, %gs
+1: movl $SEG32_MODE32_DS, %ecx
+ movw %cx, %ds
+ movw %cx, %es
+ movw %cx, %ss
+ movw %cx, %fs
+ movw %cx, %gs
- movl %ecx, %eax
jmpl *%edx
.code16
@@ -75,61 +71,56 @@ transition32:
.global transition16big
.code32
transition16:
- movl %eax, %ecx
-
- // restore data segment limits to 0xffff
- movl $SEG32_MODE16_DS, %eax
- movw %ax, %ds
- movw %ax, %es
- movw %ax, %ss
- movw %ax, %fs
- movw %ax, %gs
-
#if CONFIG_DISABLE_A20
// disable a20
+ movl %eax, %ecx
inb $PORT_A20, %al
andb $~A20_ENABLE_BIT, %al
outb %al, $PORT_A20
+ movl %ecx, %eax
#endif
+ // Reset data segment limits
+ movl $SEG32_MODE16_DS, %ecx
+ movw %cx, %ds
+ movw %cx, %es
+ movw %cx, %ss
+ movw %cx, %fs
+ movw %cx, %gs
+
// Jump to 16bit mode
ljmpw $SEG32_MODE16_CS, $1f
transition16big:
- movl %eax, %ecx
-
- movl $SEG32_MODE16BIG_DS, %eax
- movw %ax, %ds
- movw %ax, %es
- movw %ax, %ss
- movw %ax, %fs
- movw %ax, %gs
+ movl $SEG32_MODE16BIG_DS, %ecx
+ movw %cx, %ds
+ movw %cx, %es
+ movw %cx, %ss
+ movw %cx, %fs
+ movw %cx, %gs
ljmpw $SEG32_MODE16BIG_CS, $1f
.code16
-1:
// Disable protected mode
- movl %cr0, %eax
- andl $~CR0_PE, %eax
- movl %eax, %cr0
+1: movl %cr0, %ecx
+ andl $~CR0_PE, %ecx
+ movl %ecx, %cr0
// far jump to flush CPU queue after transition to real mode
ljmpw $SEG_BIOS, $2f
-2:
// restore IDT to normal real-mode defaults
- lidtw %cs:rmode_IDT_info
+2: lidtw %cs:rmode_IDT_info
// Clear segment registers
- xorw %ax, %ax
- movw %ax, %fs
- movw %ax, %gs
- movw %ax, %es
- movw %ax, %ds
- movw %ax, %ss // Assume stack is in segment 0
+ xorw %cx, %cx
+ movw %cx, %fs
+ movw %cx, %gs
+ movw %cx, %es
+ movw %cx, %ds
+ movw %cx, %ss // Assume stack is in segment 0
- movl %ecx, %eax
jmpl *%edx
--
2.4.3
3 years, 4 months
