Re: [SeaBIOS] [Qemu-devel] SeaBIOS error with Juniper FreeBSD kernel
by Kevin O'Connor
On Sun, Feb 21, 2010 at 04:18:38PM -0700, Brandon Bennett wrote:
> > On Sat, Feb 20, 2010 at 9:05 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote:
> >> Should a kernel fail during boot, I'd suspect it doesn't like one of
> >> the apm/pcibios callbacks, or it doesn't like one of the
> >> smbios/mptable/acpi tables. You could try compiling the SeaBIOS code
> >> (see http://seabios.org/Download ) and increasing the debugging by
> >> modifying src/config.h. Specifically, you could increase
> >> CONFIG_DEBUG_LEVEL, and set DEBUG_HDL_pcibios32 and DEBUG_HDL_apm to
> >> 1. Also, you could try disabling some of the features to see if that
> >> prevents the fault (eg, disabling CONFIG_ACPI / CONFIG_SMBIOS /
> >> CONFIG_MPTABLE).
> >
>
> I have narrowed it down to SMBIOS. If I disable CONFIG_SMBIOS the
> image boots up fine.
Gleb, have you seen this thread?
Some of the recent changes to smbios that look like possible culprits
are:
Make SMBIOS table pass MS SVVP test
Use MaxCountCPUs during building of per cpu tables.
Add malloc_high/fseg() and rework bios table creation to use them.
There were other changes, but the comments indicate they were only
ports of changes already in bochs. I suppose it's also possible the
lack of smbios is turning off some other feature in the guest (eg,
acpi) that's the real culprit.
-Kevin
8 years
Re: [SeaBIOS] [Qemu-devel] Re: Unusual physical address when using 64-bit BAR
by Isaku Yamahata
Added Cc: seabios(a)seabios.org
On Wed, Jul 21, 2010 at 06:31:01AM +0300, Michael S. Tsirkin wrote:
> On Tue, Jul 20, 2010 at 06:52:23PM +0900, Isaku Yamahata wrote:
> > On Wed, Jul 14, 2010 at 09:10:28AM -0600, Cam Macdonell wrote:
> > > On Tue, Jul 13, 2010 at 8:52 PM, Isaku Yamahata <yamahata(a)valinux.co.jp> wrote:
> > > > On Tue, Jul 13, 2010 at 04:48:19PM -0600, Cam Macdonell wrote:
> > > >> On Tue, Jul 13, 2010 at 2:41 PM, Isaku Yamahata <yamahata(a)valinux.co.jp> wrote:
> > > >> > On Tue, Jul 13, 2010 at 02:05:51PM -0600, Cam Macdonell wrote:
> > > >> >> >> > Seabios completely ignore the 64-bitness of the BAR. ?Looks like it also
> > > >> >> >> > thinks the second half of the BAR is an I/O region instead of memory (hence
> > > >> >> >> > the c200, that's part of the pci portio region.
> > > >> >> >
> > > >> >> > I've sent the patches to address it. But they haven't been merged yet.
> > > >> >> > seabios doesn't map BARs beyond 4GB.
> > > >> >> > If bar is mapped beyond 4GB, guest BIOS does it.
> > > >> >>
> > > >> >> Have those patches been merged yet?
> > > >> >
> > > >> > They have been merged into seabios upstream now.
> > > >> > qemu seabios fork hasn't pulled for a while, though.
> > > >> >
> > > >> >
> > > >> >> > To see how seabios works, it would help to increase CONFIG_DEBUG_LEVEL
> > > >> >> > in config.h of seabios
> > > >> >>
> > > >> >> Where does the output from seabios end up? ?Inside dmesg?
> > > >> >
> > > >> > It outputs them to the serial console which qemu emulates.
> > > >> > seabios is out of kernel control, so dmesg doesn't show it.
> > > >> >
> > > >> >
> > > >> >> >> pci_read_config: (val) 0x0 <- 0x1c (addr)
> > > >> >> >> pci_write_config: (val) 0x0 -> 0x1c (addr)
> > > >> >> >> pci_read_config: (val) 0xffffffff <- 0x1c (addr)
> > > >> >> >> pci_write_config: (val) 0x0 -> 0x1c (addr)
> > > >> >> >> pci_read_config: (val) 0x0 <- 0x1c (addr)
> > > >> >> >> pci_write_config: (val) 0x0 -> 0x1c (addr)
> > > >> >> >
> > > >> >> > seabios BAR3. Not sure how it is mapped from this
> > > >> >> > message.
> > > >> >>
> > > >> >> Isn't the BAR3 from the fact that a 64-bit BAR would use both BAR2 and
> > > >> >> BAR3 to store all 64-bits?
> > > >> >
> > > >> > Yes. Seabios misbehaves. 64bit bar is(was) a missing feature.
> > > >> > --
> > > >> > yamahata
> > > >> >
> > > >> >
> > > >>
> > > >> With the latest seabios git passed via -bios, I no longer see the
> > > >> 48-bit address, but instead a 32-bit address and then
> > > >> ffffffff00000000. ?This guest has 1gb of RAM so the address isn't be
> > > >> mapped beyond 4g.
> > > >
> > > > Can I see the debug log like before?
> > > > (hopefully seabios with CONFIG_DEBUG_LEVEL enabled.)
> > >
> > > Here's the dump from SeaBIOS in the region related to the PCI devices.
> > > The SeaBIOS output is identical whether the BAR is 32-bit or 64-bit.
> > >
> > > PCI: bus=0 devfn=0x10: vendor_id=0x1013 device_id=0x00b8
> > > region 0: 0xf0000000
> > > region 1: 0xf2000000
> > > region 6: 0xf2010000
> > > PCI: bus=0 devfn=0x18: vendor_id=0x1af4 device_id=0x1000
> > > region 0: 0x0000c020
> > > region 1: 0xf2020000
> > > region 6: 0xf2030000
> > > PCI: bus=0 devfn=0x20: vendor_id=0x1af4 device_id=0x1110
> > > region 0: 0xf2040000
> > > region 1: 0xf2041000
> > > region 2: 0x00000000
> >
> > Is this region (region 2 of devfn=0x20: vendor_id=0x1af4 device_id=0x1110)
> > the BAR in quistion?
> > The value 0 seems odd. Probably BAR address calculation overflowed.
> > Currently seabios doesn't check overflow. I attached the patch.
> >
> >
> > > > Do you know who sets the BAR to ffffffff00000000?
> > >
> > > Here are the config reads/writes related to the 0x18/1c, the 'IVSHMEM'
> > > lines are from the map function passed to pci_register_bar(). It
> > > looks like SeaBIOS sets the address to 0 and then the potentially
> > > useful e0000000 address gets mangled into ffffffff000000.
> >
> > There is something wrong with the debug message of write case, I suppose.
> > All written value are 0, but the resulted effect doesn't seems so.
> >
> > >
> > > IVSHMEM: guest pci addr = 0, guest h/w addr = 1090912256, size = 536870912
> > >
> > > ...snip...
> > >
> > > pci_read_config: (val) 0x4 <- 0x18 (addr)
> > > pci_write_config: (val) 0x0 -> 0x18 (addr)
> > > IVSHMEM: guest pci addr = e0000000, guest h/w addr = 1090912256, size = 20000000
> >
> > If 0 is written to 0x18, the bar address should be 0, but it says e0000000.
> >
> > > pci_read_config: (val) 0xe0000004 <- 0x18 (addr)
> >
> > The read value isn't 0. and so on...
> >
> > > pci_write_config: (val) 0x0 -> 0x18 (addr)
> > > pci_read_config: (val) 0x0 <- 0x1c (addr)
> > > pci_write_config: (val) 0x0 -> 0x1c (addr)
> > > IVSHMEM: guest pci addr = ffffffff00000000, guest h/w addr =
> > > 1090912256, size = 20000000
> > > pci_read_config: (val) 0xffffffff <- 0x1c (addr)
> > > pci_write_config: (val) 0x0 -> 0x1c (addr)
> > >
> > > and with the 64-bit guest I get this error as well (recall the guest
> > > fails to boot on 64-bit)
> > >
> > > BUG: kvm_dirty_pages_log_change: invalid parameters
> > > 00000000f0000000-00000000f0ffffff
> >
> >
> > diff --git a/src/pciinit.c b/src/pciinit.c
> > index b110531..6eca2ce 100644
> > --- a/src/pciinit.c
> > +++ b/src/pciinit.c
> > @@ -90,7 +90,8 @@ static int pci_bios_allocate_region(u16 bdf, int region_num)
> > /* If pci_bios_prefmem_addr == 0, keep old behaviour */
> > pci_bios_prefmem_addr != 0) {
> > paddr = &pci_bios_prefmem_addr;
> > - if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
> > + if (ALIGN(*paddr, size) + size < *paddr ||
> > + ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
> > dprintf(1,
> > "prefmem region of (bdf 0x%x bar %d) can't be mapped. "
> > "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n",
> > @@ -99,7 +100,8 @@ static int pci_bios_allocate_region(u16 bdf, int region_num)
> > }
> > } else {
> > paddr = &pci_bios_mem_addr;
> > - if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
> > + if (ALIGN(*paddr, size) + size < *paddr ||
> > + ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
> > dprintf(1,
> > "mem region of (bdf 0x%x bar %d) can't be mapped. "
> > "increase BUILD_PCIMEM_SIZE and recompile. size %x\n",
>
> Looking at the source, all of the values like pci_bios_prefmem_addr seem to be
> 32 bit. Since in the spec prefetcheable memory is up to 64 bit,
> can't the math overflow, here and elsewhere?
> Maybe we should switch to 64 bit values all over ...
Make sense. I'll create a patch to convert them into u64.
>
> > @@ -116,12 +118,8 @@ static int pci_bios_allocate_region(u16 bdf, int region_num)
> >
> > int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
> > (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
> > - if (is_64bit) {
> > - if (size > 0) {
> > - pci_config_writel(bdf, ofs + 4, 0);
> > - } else {
> > - pci_config_writel(bdf, ofs + 4, ~0);
> > - }
> > + if (is_64bit && size > 0) {
> > + pci_config_writel(bdf, ofs + 4, 0);
> > }
> > return is_64bit;
> > }
>
>
> Was there any reason we wrote all-ones there on size 0?
> BAR sizing?
No reason. It's just left over from debugging.
So I'd like to remove it.
--
yamahata
8 years, 10 months
Re: [SeaBIOS] Alt SeaBIOS SSDT cpu hotplug
by Kevin O'Connor
On Sat, Jul 31, 2010 at 01:22:59AM +0800, Liu, Jinsong wrote:
> Liu, Jinsong wrote:
> > Kevin O'Connor wrote:
> >> On Sat, Jul 10, 2010 at 12:41:18AM +0800, Liu, Jinsong wrote:
> >>> Kevin O'Connor wrote:
> >>>> I've tested this under linux - there were a few bugs in the
> >>>> previous patch. I also had to replace the dynamically created
> >>>> CPUS array with a dynamically created NTFY method - which is a bit
> >>>> more complicated.
> >>>
> >>> Yeah, thanks Kevin.
> >>> After you done patch and draft test, our QA may do nightly test.
[...]
> Kevin,
>
> We have done test for your patch, result are:
> 1. For linux 2.6.32 hvm guest, it works OK, for both vcpu add and vcpu remove, and re-add, re-remove, ...
> 2. For Window 2008 DataCenter hvm guest, it BSOD every time, QA feedback below:
Sorry about that. It looks like I messed up the SSDT ScopeOp length.
New patch attached below. I've tested it by adding/removing cpus on
Linux, and I've now also boot tested winxp and winvista. (I don't
have Windows 2008 DataCenter.)
-Kevin
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index cc31112..640716c 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -648,6 +648,78 @@ DefinitionBlock (
Zero /* reserved */
})
+ /* CPU hotplug */
+ Scope(\_SB) {
+ /* Objects filled in by run-time generated SSDT */
+ External(NTFY, MethodObj)
+ External(CPON, PkgObj)
+
+ /* Methods called by run-time generated SSDT Processor objects */
+ Method (CPMA, 1, NotSerialized) {
+ // _MAT method - create an madt apic buffer
+ // Local0 = CPON flag for this cpu
+ Store(DerefOf(Index(CPON, Arg0)), Local0)
+ // Local1 = Buffer (in madt apic form) to return
+ Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
+ // Update the processor id, lapic id, and enable/disable status
+ Store(Arg0, Index(Local1, 2))
+ Store(Arg0, Index(Local1, 3))
+ Store(Local0, Index(Local1, 4))
+ Return (Local1)
+ }
+ Method (CPST, 1, NotSerialized) {
+ // _STA method - return ON status of cpu
+ // Local0 = CPON flag for this cpu
+ Store(DerefOf(Index(CPON, Arg0)), Local0)
+ If (Local0) { Return(0xF) } Else { Return(0x0) }
+ }
+ Method (CPEJ, 2, NotSerialized) {
+ // _EJ0 method - eject callback
+ Sleep(200)
+ }
+
+ /* CPU hotplug notify method */
+ OperationRegion(PRST, SystemIO, 0xaf00, 32)
+ Field (PRST, ByteAcc, NoLock, Preserve)
+ {
+ PRS, 256
+ }
+ Method(PRSC, 0) {
+ // Local5 = active cpu bitmap
+ Store (PRS, Local5)
+ // Local2 = last read byte from bitmap
+ Store (Zero, Local2)
+ // Local0 = cpuid iterator
+ Store (Zero, Local0)
+ While (LLess(Local0, SizeOf(CPON))) {
+ // Local1 = CPON flag for this cpu
+ Store(DerefOf(Index(CPON, Local0)), Local1)
+ If (And(Local0, 0x07)) {
+ // Shift down previously read bitmap byte
+ ShiftRight(Local2, 1, Local2)
+ } Else {
+ // Read next byte from cpu bitmap
+ Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
+ }
+ // Local3 = active state for this cpu
+ Store(And(Local2, 1), Local3)
+
+ If (LNotEqual(Local1, Local3)) {
+ // State change - update CPON with new state
+ Store(Local3, Index(CPON, Local0))
+ // Do CPU notify
+ If (LEqual(Local3, 1)) {
+ NTFY(Local0, 1)
+ } Else {
+ NTFY(Local0, 3)
+ }
+ }
+ Increment(Local0)
+ }
+ Return(One)
+ }
+ }
+
Scope (\_GPE)
{
Name(_HID, "ACPI0006")
@@ -701,7 +773,8 @@ DefinitionBlock (
}
Method(_L02) {
- Return(0x01)
+ // CPU hotplug event
+ Return(\_SB.PRSC())
}
Method(_L03) {
Return(0x01)
diff --git a/src/acpi.c b/src/acpi.c
index e91f8e0..3b49c4e 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -1,6 +1,6 @@
// Support for generating ACPI tables (on emulators)
//
-// Copyright (C) 2008,2009 Kevin O'Connor <kevin(a)koconnor.net>
+// Copyright (C) 2008-2010 Kevin O'Connor <kevin(a)koconnor.net>
// Copyright (C) 2006 Fabrice Bellard
//
// This file may be distributed under the terms of the GNU LGPLv3 license.
@@ -329,64 +329,121 @@ build_madt(void)
return madt;
}
+// Encode a hex value
+static inline char getHex(u32 val) {
+ val &= 0x0f;
+ return (val <= 9) ? ('0' + val) : ('A' + val - 10);
+}
+
+// Encode a length in an SSDT.
+static u8 *
+encodeLen(u8 *ssdt_ptr, int length, int bytes)
+{
+ switch (bytes) {
+ default:
+ case 4: ssdt_ptr[3] = ((length >> 20) & 0xff);
+ case 3: ssdt_ptr[2] = ((length >> 12) & 0xff);
+ case 2: ssdt_ptr[1] = ((length >> 4) & 0xff);
+ ssdt_ptr[0] = (((bytes-1) & 0x3) << 6) | (length & 0x0f);
+ break;
+ case 1: ssdt_ptr[0] = length & 0x3f;
+ }
+ return ssdt_ptr + bytes;
+}
+
+// AML Processor() object. See src/ssdt-proc.dsl for info.
+static unsigned char ssdt_proc[] = {
+ 0x5b,0x83,0x43,0x05,0x43,0x50,0x41,0x41,
+ 0xaa,0x10,0xb0,0x00,0x00,0x06,0x08,0x49,
+ 0x44,0x5f,0x5f,0x0a,0xaa,0x08,0x5f,0x48,
+ 0x49,0x44,0x0d,0x41,0x43,0x50,0x49,0x30,
+ 0x30,0x30,0x37,0x00,0x14,0x0f,0x5f,0x4d,
+ 0x41,0x54,0x00,0xa4,0x43,0x50,0x4d,0x41,
+ 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x53,
+ 0x54,0x41,0x00,0xa4,0x43,0x50,0x53,0x54,
+ 0x49,0x44,0x5f,0x5f,0x14,0x10,0x5f,0x45,
+ 0x4a,0x30,0x01,0xa4,0x43,0x50,0x45,0x4a,
+ 0x49,0x44,0x5f,0x5f,0x68
+};
+#define SD_OFFSET_CPUHEX 6
+#define SD_OFFSET_CPUID1 8
+#define SD_OFFSET_CPUID2 20
+
#define SSDT_SIGNATURE 0x54445353 // SSDT
static void*
build_ssdt(void)
{
int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
- // calculate the length of processor block and scope block
- // excluding PkgLength
- int cpu_length = 13 * acpi_cpus + 4;
-
- int length = sizeof(struct acpi_table_header) + 3 + cpu_length;
- u8 *ssdt = malloc_high(length);
+ // length = ScopeOp + procs + NTYF method + CPON package
+ int length = ((1+3+4)
+ + (acpi_cpus * sizeof(ssdt_proc))
+ + (1+2+5+(12*acpi_cpus))
+ + (6+2+1+(1*acpi_cpus)));
+ u8 *ssdt = malloc_high(sizeof(struct acpi_table_header) + length);
if (! ssdt) {
warn_noalloc();
return NULL;
}
+ u8 *ssdt_ptr = ssdt + sizeof(struct acpi_table_header);
- u8 *ssdt_ptr = ssdt;
- ssdt_ptr[9] = 0; // checksum;
- ssdt_ptr += sizeof(struct acpi_table_header);
-
- // build processor scope header
+ // build Scope(_SB_) header
*(ssdt_ptr++) = 0x10; // ScopeOp
- if (cpu_length <= 0x3e) {
- /* Handle 1-4 CPUs with one byte encoding */
- *(ssdt_ptr++) = cpu_length + 1;
- } else {
- /* Handle 5-314 CPUs with two byte encoding */
- *(ssdt_ptr++) = 0x40 | ((cpu_length + 2) & 0xf);
- *(ssdt_ptr++) = (cpu_length + 2) >> 4;
- }
- *(ssdt_ptr++) = '_'; // Name
- *(ssdt_ptr++) = 'P';
- *(ssdt_ptr++) = 'R';
+ ssdt_ptr = encodeLen(ssdt_ptr, length-1, 3);
+ *(ssdt_ptr++) = '_';
+ *(ssdt_ptr++) = 'S';
+ *(ssdt_ptr++) = 'B';
*(ssdt_ptr++) = '_';
- // build object for each processor
+ // build Processor object for each processor
int i;
for (i=0; i<acpi_cpus; i++) {
- *(ssdt_ptr++) = 0x5B; // ProcessorOp
- *(ssdt_ptr++) = 0x83;
- *(ssdt_ptr++) = 0x0B; // Length
- *(ssdt_ptr++) = 'C'; // Name (CPUxx)
- *(ssdt_ptr++) = 'P';
- if ((i & 0xf0) != 0)
- *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
- else
- *(ssdt_ptr++) = 'U';
- *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
+ memcpy(ssdt_ptr, ssdt_proc, sizeof(ssdt_proc));
+ ssdt_ptr[SD_OFFSET_CPUHEX] = getHex(i >> 4);
+ ssdt_ptr[SD_OFFSET_CPUHEX+1] = getHex(i);
+ ssdt_ptr[SD_OFFSET_CPUID1] = i;
+ ssdt_ptr[SD_OFFSET_CPUID2] = i;
+ ssdt_ptr += sizeof(ssdt_proc);
+ }
+
+ // build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}"
+ *(ssdt_ptr++) = 0x14; // MethodOp
+ ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*acpi_cpus), 2);
+ *(ssdt_ptr++) = 'N';
+ *(ssdt_ptr++) = 'T';
+ *(ssdt_ptr++) = 'F';
+ *(ssdt_ptr++) = 'Y';
+ *(ssdt_ptr++) = 0x02;
+ for (i=0; i<acpi_cpus; i++) {
+ *(ssdt_ptr++) = 0xA0; // IfOp
+ ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
+ *(ssdt_ptr++) = 0x93; // LEqualOp
+ *(ssdt_ptr++) = 0x68; // Arg0Op
+ *(ssdt_ptr++) = 0x0A; // BytePrefix
*(ssdt_ptr++) = i;
- *(ssdt_ptr++) = 0x10; // Processor block address
- *(ssdt_ptr++) = 0xb0;
- *(ssdt_ptr++) = 0;
- *(ssdt_ptr++) = 0;
- *(ssdt_ptr++) = 6; // Processor block length
+ *(ssdt_ptr++) = 0x86; // NotifyOp
+ *(ssdt_ptr++) = 'C';
+ *(ssdt_ptr++) = 'P';
+ *(ssdt_ptr++) = getHex(i >> 4);
+ *(ssdt_ptr++) = getHex(i);
+ *(ssdt_ptr++) = 0x69; // Arg1Op
}
+ // build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
+ *(ssdt_ptr++) = 0x08; // NameOp
+ *(ssdt_ptr++) = 'C';
+ *(ssdt_ptr++) = 'P';
+ *(ssdt_ptr++) = 'O';
+ *(ssdt_ptr++) = 'N';
+ *(ssdt_ptr++) = 0x12; // PackageOp
+ ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2);
+ *(ssdt_ptr++) = acpi_cpus;
+ for (i=0; i<acpi_cpus; i++)
+ *(ssdt_ptr++) = (i < CountCPUs) ? 0x01 : 0x00;
+
build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
+ //hexdump(ssdt, ssdt_ptr - ssdt);
+
return ssdt;
}
diff --git a/src/ssdt-proc.dsl b/src/ssdt-proc.dsl
new file mode 100644
index 0000000..2ffb326
--- /dev/null
+++ b/src/ssdt-proc.dsl
@@ -0,0 +1,50 @@
+/* This file is the basis for the ssdt_proc[] variable in src/acpi.c.
+ * It defines the contents of the per-cpu Processor() object. At
+ * runtime, a dynamically generated SSDT will contain one copy of this
+ * AML snippet for every possible cpu in the system. The objects will
+ * be placed in the \_SB_ namespace.
+ *
+ * To generate a new ssdt_proc[], run the commands:
+ * cpp -P src/ssdt-proc.dsl > out/ssdt-proc.dsl.i
+ * iasl -ta -p out/ssdt-proc out/ssdt-proc.dsl.i
+ * tail -c +37 < out/ssdt-proc.aml | hexdump -e '" " 8/1 "0x%02x," "\n"'
+ * and then cut-and-paste the output into the src/acpi.c ssdt_proc[]
+ * array.
+ *
+ * In addition to the aml code generated from this file, the
+ * src/acpi.c file creates a NTFY method with an entry for each cpu:
+ * Method(NTFY, 2) {
+ * If (LEqual(Arg0, 0x00)) { Notify(CP00, Arg1) }
+ * If (LEqual(Arg0, 0x01)) { Notify(CP01, Arg1) }
+ * ...
+ * }
+ * and a CPON array with the list of active and inactive cpus:
+ * Name(CPON, Package() { One, One, ..., Zero, Zero, ... })
+ */
+DefinitionBlock ("ssdt-proc.aml", "SSDT", 0x01, "BXPC", "BXSSDT", 0x1)
+/* v------------------ DO NOT EDIT ------------------v */
+{
+ Processor (CPAA, 0xAA, 0x0000b010, 0x06) {
+ Name (ID, 0xAA)
+/* ^------------------ DO NOT EDIT ------------------^
+ *
+ * The src/acpi.c code requires the above layout so that it can update
+ * CPAA and 0xAA with the appropriate CPU id (see
+ * SD_OFFSET_CPUHEX/CPUID1/CPUID2). Don't change the above without
+ * also updating the C code.
+ */
+ Name (_HID, "ACPI0007")
+ External(CPMA, MethodObj)
+ External(CPST, MethodObj)
+ External(CPEJ, MethodObj)
+ Method(_MAT, 0) {
+ Return(CPMA(ID))
+ }
+ Method (_STA, 0) {
+ Return(CPST(ID))
+ }
+ Method (_EJ0, 1, NotSerialized) {
+ Return(CPEJ(ID, Arg0))
+ }
+ }
+}
8 years, 11 months
[PATCH] EDD fixes
by Sebastian Herbszt
Fix data returned in the int13dpt structure.
Signed-off-by: Sebastian Herbszt <herbszt(a)gmx.de>
diff --git a/src/disk.c b/src/disk.c
index 242c742..d7fd6b3 100644
--- a/src/disk.c
+++ b/src/disk.c
@@ -603,14 +603,14 @@ disk_1348(struct bregs *regs, struct drive_s *drive_g)
ebda_seg, (void*)offsetof(struct extended_bios_data_area_s, dpte), 15);
SET_EBDA2(ebda_seg, dpte.checksum, -sum);
- if (size < 66) {
+ if (size < 74) {
disk_ret(regs, DISK_RET_SUCCESS);
return;
}
// EDD 3.x
SET_INT13DPT(regs, key, 0xbedd);
- SET_INT13DPT(regs, dpi_length, 36);
+ SET_INT13DPT(regs, dpi_length, 44);
SET_INT13DPT(regs, reserved1, 0);
SET_INT13DPT(regs, reserved2, 0);
@@ -619,7 +619,7 @@ disk_1348(struct bregs *regs, struct drive_s *drive_g)
SET_INT13DPT(regs, host_bus[0], 'P');
SET_INT13DPT(regs, host_bus[1], 'C');
SET_INT13DPT(regs, host_bus[2], 'I');
- SET_INT13DPT(regs, host_bus[3], 0);
+ SET_INT13DPT(regs, host_bus[3], ' ');
u32 path = (pci_bdf_to_bus(bdf) | (pci_bdf_to_dev(bdf) << 8)
| (pci_bdf_to_fn(bdf) << 16));
@@ -629,7 +629,7 @@ disk_1348(struct bregs *regs, struct drive_s *drive_g)
SET_INT13DPT(regs, host_bus[0], 'I');
SET_INT13DPT(regs, host_bus[1], 'S');
SET_INT13DPT(regs, host_bus[2], 'A');
- SET_INT13DPT(regs, host_bus[3], 0);
+ SET_INT13DPT(regs, host_bus[3], ' ');
SET_INT13DPT(regs, iface_path, iobase1);
}
@@ -637,16 +637,19 @@ disk_1348(struct bregs *regs, struct drive_s *drive_g)
SET_INT13DPT(regs, iface_type[0], 'A');
SET_INT13DPT(regs, iface_type[1], 'T');
SET_INT13DPT(regs, iface_type[2], 'A');
- SET_INT13DPT(regs, iface_type[3], 0);
- SET_INT13DPT(regs, iface_type[4], 0);
- SET_INT13DPT(regs, iface_type[5], 0);
- SET_INT13DPT(regs, iface_type[6], 0);
- SET_INT13DPT(regs, iface_type[7], 0);
+ SET_INT13DPT(regs, iface_type[3], ' ');
+ SET_INT13DPT(regs, iface_type[4], ' ');
+ SET_INT13DPT(regs, iface_type[5], ' ');
+ SET_INT13DPT(regs, iface_type[6], ' ');
+ SET_INT13DPT(regs, iface_type[7], ' ');
- SET_INT13DPT(regs, device_path, slave);
+ SET_INT13DPT(regs, device_path1, slave);
+ SET_INT13DPT(regs, device_path2, 0);
+
+ SET_INT13DPT(regs, reserved3, 0);
SET_INT13DPT(regs, checksum
- , -checksum_far(regs->ds, (void*)(regs->si+30), 35));
+ , -checksum_far(regs->ds, (void*)(regs->si+30), 43));
disk_ret(regs, DISK_RET_SUCCESS);
}
diff --git a/src/disk.h b/src/disk.h
index 9e5b083..0ef849d 100644
--- a/src/disk.h
+++ b/src/disk.h
@@ -63,7 +63,8 @@ struct int13dpt_s {
u8 host_bus[4];
u8 iface_type[8];
u64 iface_path;
- u64 device_path;
+ u64 device_path1;
+ u64 device_path2;
u8 reserved3;
u8 checksum;
} PACKED;
8 years, 11 months
[PATCH 0/5] More bootsplash enhancements
by Kevin O'Connor
This series further enhances the bootsplash code. The last patch
enables it by default (for coreboot users).
Kevin O'Connor (5):
Avoid using BSS variables in jpeg.c.
Breakup jpeg_decode into parsing and displaying phases.
Rename "decdata" to "jpeg" in bootsplash - to be consistent with
jpeg.c.
Autodetect video mode based on bootsplash jpeg dimensions.
Default bootsplash on (for coreboot users).
src/bootsplash.c | 117 +++++++++++++-------
src/config.h | 10 +--
src/jpeg.c | 307 +++++++++++++++++++++++++++++-------------------------
src/jpeg.h | 37 +------
4 files changed, 248 insertions(+), 223 deletions(-)
--
1.7.2
8 years, 11 months
Re: [SeaBIOS] Alt SeaBIOS SSDT cpu hotplug
by Kevin O'Connor
On Sat, Jul 10, 2010 at 12:41:18AM +0800, Liu, Jinsong wrote:
> Kevin O'Connor wrote:
> > On Thu, Jul 08, 2010 at 09:19:13PM +0800, Liu, Jinsong wrote:
> >> Avi Kivity wrote:
> >>> Very nice. I thought about doing this but abandoned it as
> >>> unmaintainable. Using external functions and the ID variable,
> >>> however, reduces the mess to tolerable proportions, and gains us a
> >>> lot of flexibility. We can now have any combinations of sockets and
> >>> installed cpus.
> >>
> >> Agree, only 1 concern
> >> will it bring debugable/ scalable issue by hardcode aml code?
> >
> > I've updated the patch (see below). This version documents how one
> > can build a new version of the Processor() ssdt snippet.
> >
> > I've tested this under linux - there were a few bugs in the previous
> > patch. I also had to replace the dynamically created CPUS array with
> > a dynamically created NTFY method - which is a bit more complicated.
>
> Yeah, thanks Kevin.
> After you done patch and draft test, our QA may do nightly test.
Hi Jinsong,
Have you had any feedback from tests?
Thanks,
-Kevin
8 years, 11 months
[PATCH] seabios: acpi: add mcfg table.
by Isaku Yamahata
add mcfg table.
mcfg isn't populated at the moment. dev-q35 will use it later.
Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp>
---
src/acpi.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
src/acpi.h | 17 ++++++++++++++++
src/post.h | 14 +++++++++++++
3 files changed, 93 insertions(+), 0 deletions(-)
create mode 100644 src/post.h
diff --git a/src/acpi.c b/src/acpi.c
index e91f8e0..d61ae16 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -13,6 +13,7 @@
#include "pci_regs.h" // PCI_INTERRUPT_LINE
#include "paravirt.h"
#include "dev-i440fx.h" // piix4_fadt_init
+#include "post.h"
/****************************************************/
/* ACPI tables init */
@@ -522,6 +523,66 @@ build_srat(void)
return srat;
}
+static const struct pci_device_id mcfg_find_tbl[] = {
+ PCI_DEVICE_END,
+};
+
+static const struct pci_device_id mcfg_init_tbl[] = {
+ PCI_DEVICE_END,
+};
+
+static void *
+build_mcfg(void)
+{
+ struct acpi_mcfg acpi_mcfg = {
+ .nr = 0,
+ .mcfg = NULL,
+ .e820 = NULL,
+ };
+ int bdf = pci_find_init_device(mcfg_find_tbl, &acpi_mcfg);
+ if (bdf < 0) {
+ return NULL;
+ }
+ if (acpi_mcfg.nr == 0) {
+ return NULL;
+ }
+
+ struct acpi_table_mcfg *mcfg;
+ int len = sizeof(*mcfg) + acpi_mcfg.nr * sizeof(mcfg->allocation[0]);
+ mcfg = malloc_high(len);
+ if (!mcfg) {
+ dprintf(1, "Not enough memory for mcfg table!\n");
+ return NULL;
+ }
+ memset(mcfg, 0, len);
+ acpi_mcfg.mcfg = mcfg;
+
+
+ struct e820entry *e820;
+ int e820_len = acpi_mcfg.nr * sizeof(*e820);
+ e820 = malloc_tmphigh(e820_len);
+ if (!e820) {
+ dprintf(1, "Not enough memory for e820 table!\n");
+ free(mcfg);
+ return NULL;
+ }
+ memset(e820, 0, e820_len);
+ acpi_mcfg.e820 = e820;
+
+ pci_init_device(mcfg_init_tbl, bdf, &acpi_mcfg);
+
+ /* Linux checks if e820 covers mcfg area as reserved.
+ * If no, Linux thinks bios is buggy and won't use MCFG */
+ int i;
+ for (i = 0; i < acpi_mcfg.nr; i++) {
+ add_e820(e820[i].start, e820[i].size, E820_RESERVED);
+ }
+ free(e820);
+
+ build_header((void *)mcfg, MCFG_SIGNATURE, len, 1);
+ return mcfg;
+}
+
static const struct pci_device_id acpi_find_tbl[] = {
/* PIIX4 Power Management device. */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
@@ -568,6 +629,7 @@ acpi_bios_init(void)
ACPI_INIT_TABLE(build_madt());
ACPI_INIT_TABLE(build_hpet());
ACPI_INIT_TABLE(build_srat());
+ ACPI_INIT_TABLE(build_mcfg());
u16 i, external_tables = qemu_cfg_acpi_additional_tables();
diff --git a/src/acpi.h b/src/acpi.h
index e01315a..798fb19 100644
--- a/src/acpi.h
+++ b/src/acpi.h
@@ -98,4 +98,21 @@ struct fadt_descriptor_rev1
#endif
} PACKED;
+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct acpi_mcfg_allocation {
+ u64 address; /* Base address, processor-relative */
+ u16 pci_segment; /* PCI segment group number */
+ u8 start_bus_number; /* Starting PCI Bus number */
+ u8 end_bus_number; /* Final PCI Bus number */
+ u32 reserved;
+} PACKED;
+
+#define MCFG_SIGNATURE 0x4746434d // MCFG
+struct acpi_table_mcfg {
+ ACPI_TABLE_HEADER_DEF;
+ u8 reserved[8];
+ struct acpi_mcfg_allocation allocation[0];
+} PACKED;
+
#endif // acpi.h
diff --git a/src/post.h b/src/post.h
new file mode 100644
index 0000000..04e506d
--- /dev/null
+++ b/src/post.h
@@ -0,0 +1,14 @@
+#ifndef __POST_H
+#define __POST_H
+
+#include "memmap.h" // struct e820entry
+#include "acpi.h" // struct acpi_table_mcfg
+
+struct acpi_mcfg
+{
+ u32 nr;
+ struct acpi_table_mcfg *mcfg;
+ struct e820entry *e820;
+};
+
+#endif /* __POST_H */
--
1.7.1.1
8 years, 11 months
Re: [SeaBIOS] [PATCH 2/2] seabios: pciinit: fix overflow when bar allocation.
by Kevin O'Connor
On Mon, Jul 26, 2010 at 02:02:46PM +0900, Isaku Yamahata wrote:
> When allocating bar, overflow can occur.
> So add overflow check and don't allocate bar if overflowed.
> Overflow check is ugly, but necessary.
> Another suggested way is to change related variables u64 from u32
> thus overflow can't occur because the related value are all u32 addressable.
> Anyway even with u64, it is necessary to the resulted value > max_u32.
I wonder if we could create malloc zones for this and then use
pmm_alloc. The pmm_alloc function already handles overflow and
alignments.
One difficulty, though, is that pmm_alloc doesn't guarentee linear
allocations, and it looks like pci_bios_init_device_bridge assumes
this.
-Kevin
8 years, 11 months
[PATCH] Fix bug causing truncation of files in cbfs_copyfile().
by Kevin O'Connor
Fix bug causing truncation of uncompressed files that had a size not a
multiple of 4.
Make sure to allocate extra space for jpeg temp location in bootsplash
code.
---
src/bootsplash.c | 2 +-
src/coreboot.c | 6 +++---
src/util.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/bootsplash.c b/src/bootsplash.c
index ed10415..9dcdd99 100644
--- a/src/bootsplash.c
+++ b/src/bootsplash.c
@@ -119,7 +119,7 @@ void enable_vga_console(void)
struct cbfs_file *file = cbfs_finddatafile("bootsplash.jpg");
if (!file)
goto gotext;
- int filesize = cbfs_datasize(file);
+ int filesize = ALIGN(cbfs_datasize(file), 4);
int imagesize = (CONFIG_BOOTSPLASH_X * CONFIG_BOOTSPLASH_Y *
(CONFIG_BOOTSPLASH_DEPTH / 8));
diff --git a/src/coreboot.c b/src/coreboot.c
index 5d9a101..207c4a4 100644
--- a/src/coreboot.c
+++ b/src/coreboot.c
@@ -507,10 +507,10 @@ cbfs_copyfile(struct cbfs_file *file, void *dst, u32 maxlen)
return -1;
u32 size = ntohl(file->len);
+ u32 asize = ALIGN(size, 4);
void *src = (void*)file + ntohl(file->offset);
if (cbfs_iscomp(file)) {
// Compressed - copy to temp ram and uncompress it.
- u32 asize = ALIGN(size, 4);
void *temp = malloc_tmphigh(asize);
if (!temp)
return -1;
@@ -523,11 +523,11 @@ cbfs_copyfile(struct cbfs_file *file, void *dst, u32 maxlen)
// Not compressed.
dprintf(3, "Copying data %d@%p to %d@%p\n", size, src, maxlen, dst);
- if (size > maxlen) {
+ if (asize > maxlen) {
warn_noalloc();
return -1;
}
- iomemcpy(dst, src, size);
+ iomemcpy(dst, src, asize);
return size;
}
diff --git a/src/util.c b/src/util.c
index 2c22dfc..d99bf06 100644
--- a/src/util.c
+++ b/src/util.c
@@ -202,7 +202,7 @@ memcpy(void *d1, const void *s1, size_t len)
return d1;
}
-// Copy from memory mapped IO. IO mem is very slow, so yield
+// Copy to/from memory mapped IO. IO mem is very slow, so yield
// periodically. 'len' must be 4 byte aligned.
void
iomemcpy(void *d, const void *s, u32 len)
--
1.7.1.1
8 years, 11 months
[PATCH 0/6] Bootsplash cleanups and enhancements
by Kevin O'Connor
This patch series fixes some bugs in the bootsplash code, and adds
some cleanups. It is in preparation for turning bootsplash on by
default.
Kevin O'Connor (6):
Bootsplash fixes and cleanups.
Check that malloc succeeds in bootsplash code.
Don't do "double buffering" in bootsplash code.
Add call16_int10 helper to bootsplash.c.
Be sure to disable bootsplash on all BIOS boot cases.
Cleanup bootsplash vesa signature detection.
src/biosvar.h | 3 +-
src/boot.c | 8 +-
src/bootsplash.c | 210 ++++++++++++++++++++++--------------------------------
src/post.c | 8 ++-
src/util.h | 5 +-
5 files changed, 101 insertions(+), 133 deletions(-)
8 years, 11 months