This patch is equivalent to a patch recently committed to Bochs bios
diff --git a/src/post.c b/src/post.c
index 6964f38..f087a27 100644
@@ -66,6 +66,10 @@ init_ivt()
+ // INT 60h-66h reserved for user interrupt
+ for (i=0x60; i<=0x66; i++)
+ SET_IVT(i, SEGOFF(0, 0));
// set vector 0x79 to zero
// this is used by 'gardian angel' protection system
SET_IVT(0x79, SEGOFF(0, 0));
On Mon, Dec 14, 2009 at 10:23:39AM +0100, Magnus Christensson wrote:
>> This function implement the same logic as pci_swizzle_interrupt_pin() in
>> Linux kernel. This logic defines how PCI bridge connects INTx of each
>> devices behind it to system board interrupt line and it is part of PCI
>> spec (page 30 of PCI3.0 spec). Note that the function return pin, not
>> interrupt line. To get interrupt line we look into pci_irqs array.
> The swizzling of INTx-pins happens in PCI-to-PCI bridges. But it looks
> like the pci_slot_get_pirq function is applied to all devices, including
> those on the top-level bus that are not behind any PCI-to-PCI bridge.
> Further, the function only looks at device (slot) and doesn't care where
> the device is in the PCI hierarchy.
The pci_slot_get_pirq() appears to be taken directly from
hw/piix_pci.c in the qemu source. So, it represents the "motherboard"
mapping of irq lines on bus 0.
Note, the mapping isn't the same as the swizzling of PCI-to-PCI
bridges - on a pci bridge, INTA# of device 0 would map to the upstream
INTA# pin, but the pci_slot_get_pirq() would actually map it to INTD#.
The code is in line with the ACPI mapping in src/acpi-dsdt.dsl and the
PIR mapping in src/pirtable.c.
I've completed another round of improvements and timings on my epia-cn
machine. From power-on to grub serial menu is now 750ms. For
comparison, the same equipment with the factory bios takes 9.9s. (To
be fair though, I needed to remove the 2.5s boot menu delay in SeaBIOS
to get to 750ms.)
More background info is available in the thread at:
A breakdown of the 750ms reveals:
* cpu appears to start running around 350ms
* smbus power stabilizes around 400ms
* 20ms to program ddr ram controller
* 15ms to uncompress coreboot_ram (note flash access wasn't a factor -
* 10ms to run coreboot_ram
* 35ms to read and uncompress seabios from flash
* 40ms to read and uncompress via vga rom from flash
* 200ms to run via vga option rom and turn on vga
* 10ms for remaining hardware init (the hardware init runs in parallel
with the 240ms for vga option rom - the 10ms is what remains after
* 10ms time spent in grub (and in grub reads from disk)
Changes since last time:
* I'm using a SATA SSD (OCZ Vertex 30G) to store grub (and the OS).
This device doesn't seem to require a "spin up" delay.
* I've enhanced SeaBIOS to support ATA bus mastering DMA. I'll send a
patch out separately with the details. This dramatically increases
the speed of disk reads.
* I've commented out the calls to wbinvd() in coreboot's mtrr
cache_disable logic - those calls are expensive and the code seems
to work without it.
* While waiting for the smbus to power stabilize, I added reads to the
flash to seed the cache with the bootblock and coreboot_ram. This
eliminates the costly flash read time for that code.
Also interesting is adding a gPXE rom (rtl8169) only added 50ms to the
total SeaBIOS boot time (I set gPXE's BANNER_TIMEOUT to 0).
From: Anthony Liguori <aliguori(a)us.ibm.com>
Option rom saga continued. This is the first series I consider ready
for merging. Changes:
* pci roms: will be loaded via option pci rom bar.
* non-pci roms: will be loaded via fw_cfg.
Note that using the old bochs-bios based pc-bios will stop working
with this patch series applied.
The last two patches of this series are *not* intended to be merged,
they are just for testing convinience. They carry a new seabios
binary and the changes needed and turn on bios debug messages in qemu.
Seabios patches will be posted shortly as separate patch series.