SeaBIOS December 2019

seabios@seabios.org

7 participants
16 discussions

[PATCH 4/4] serialio: Support for pci serial ports
by Your Real Name 11 Dec '19

11 Dec '19

From f65c435b8e3caf7249a3fb25150e7055898ccc12 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Fri, 18 Oct 2019 23:00:21 -0700 Subject: [PATCH 4/4] serialio: Support for pci serial ports Some Intel PCHs integrate pci uarts which are used for serial port debugging. For compatibility purpose, BIOS implementation may assign 0x3f8 to the pci uart's io bar at PEI stage, later during DXE stage the pci uart's bar is re-assigned to a different address. As a result, we can't use the hard coded IO port 0x3f8 in SeaBIOS for debugging. Instead, we need read the port base address from the pci uart's BAR, either an IO BAR, or a 32bit memory BAR. This patch adds support for pci serial port debugging. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/Kconfig | 34 +++++++++++++++++++++++++++++++++- src/hw/serialio.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 60 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6606ce4..6d9ce3b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -550,8 +550,40 @@ menu "Debugging" default 0x3f8 help Base port for serial - generally 0x3f8, 0x2f8, 0x3e8, or 0x2e8. - config DEBUG_SERIAL_MMIO + config DEBUG_SERIAL_PCI_IO depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL + bool "Serial port debugging via PCI IO" + default n + help + Send debugging information to PCI serial port. + The base address of the uart is in the PCI device's IO bar. + config DEBUG_SERIAL_PCI_MEM32 + depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO + bool "Serial port debugging via PCI MEM32" + default n + help + Send debugging information to PCI serial port. + The base address of the uart is in the PCI device's MEM32 bar. + config DEBUG_SERIAL_PCI_BDF + depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32 + hex "Serial port PCI bus/device/function" + range 0 ffff + help + 16bit hex of B:D:F of the PCI serial port. + Bit 15:8 - bus, bit 7:3 - device, bit 2:0 - function + E.g. for a PCI device: bus 0x0, dev 0x1a, func 0x1 you + should input 00d1. + config DEBUG_SERIAL_PCI_BAR + depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32 + hex "Serial port PCI BAR index (0 - 5)" + range 0 5 + default 0 + help + The index of the BAR where the base address would be read + from for the PCI serial port. Only IO BAR and 32bit memory + BAR are supported. + config DEBUG_SERIAL_MMIO + depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO && !DEBUG_SERIAL_PCI_MEM32 bool "Serial port debugging via memory mapped IO" default n help diff --git a/src/hw/serialio.c b/src/hw/serialio.c index 3163344..9a8565c 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -9,6 +9,7 @@ #include "output.h" // dprintf #include "serialio.h" // serial_debug_preinit #include "x86.h" // outb +#include "pci.h" //pci_config_readw /**************************************************************** @@ -23,6 +24,15 @@ serial_debug_write(u8 offset, u8 val) { if (CONFIG_DEBUG_SERIAL) { outb(val, CONFIG_DEBUG_SERIAL_PORT + offset); + } else if (CONFIG_DEBUG_SERIAL_PCI_IO) { + u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3); + outb(val, base + offset); + } else if (CONFIG_DEBUG_SERIAL_PCI_MEM32) { + ASSERT32FLAT(); + u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7); + writeb((void*)base + 4*offset, val); } else if (CONFIG_DEBUG_SERIAL_MMIO) { ASSERT32FLAT(); writeb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset, val); @@ -35,6 +45,17 @@ serial_debug_read(u8 offset) { if (CONFIG_DEBUG_SERIAL) return inb(CONFIG_DEBUG_SERIAL_PORT + offset); + if (CONFIG_DEBUG_SERIAL_PCI_IO) { + u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3); + return inb(base + offset); + } + if (CONFIG_DEBUG_SERIAL_PCI_MEM32) { + ASSERT32FLAT(); + u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7); + return readb((void*)base + 4*offset); + } if (CONFIG_DEBUG_SERIAL_MMIO) { ASSERT32FLAT(); return readb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset); @@ -65,7 +86,9 @@ serial_debug_preinit(void) static void serial_debug(char c) { - if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT)) + if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO && + ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) || + MODESEGMENT)) return; int timeout = DEBUG_TIMEOUT; while ((serial_debug_read(SEROFF_LSR) & 0x20) != 0x20) @@ -87,7 +110,9 @@ serial_debug_putc(char c) void serial_debug_flush(void) { - if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT)) + if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO && + ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) || + MODESEGMENT)) return; int timeout = DEBUG_TIMEOUT; while ((serial_debug_read(SEROFF_LSR) & 0x60) != 0x60) -- 2.17.1

3 11

[PATCH 3/4] csm: Enable boot from pci option rom
by Your Real Name 11 Dec '19

11 Dec '19

From 9ca6590769692b99e98acf48acc3ce700238e451 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 22:47:43 -0700 Subject: [PATCH 3/4] csm: Enable boot from pci option rom In csm mode, the bev pointer of the pci option rom was not added to the bootentry list, resulting in failure to boot from pci option rom. This patch fixed it. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/fw/csm.c | 18 ++++++++++++++++++ src/optionroms.c | 2 +- src/util.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/fw/csm.c b/src/fw/csm.c index c8111cd..8e2a1aa 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -19,6 +19,7 @@ #include "std/acpi.h" // RSDP_SIGNATURE #include "std/bda.h" // struct bios_data_area_s #include "std/optionrom.h" // struct rom_header +#include "std/pnpbios.h" // PNP_SIGNATURE #include "util.h" // copy_smbios #define UINT8 u8 @@ -218,12 +219,16 @@ handle_csm_0003(struct bregs *regs) regs->ax = 1; } +static int rom_instance; + /* Legacy16DispatchOprom */ static void handle_csm_0005(struct bregs *regs) { EFI_DISPATCH_OPROM_TABLE *table = MAKE_FLATPTR(regs->es, regs->bx); struct rom_header *rom; + struct pnp_data *pnp; + u64 sources[(BUILD_BIOS_ADDR - BUILD_ROM_START) / OPTION_ROM_ALIGN]; u16 bdf; if (!CONFIG_OPTIONROMS) { @@ -250,6 +255,19 @@ handle_csm_0005(struct bregs *regs) rom_confirm(rom->size * 512); + // PnP rom - check for BEV and BCV boot capabilities. + pnp = (void*)((u8*)rom + rom->pnpoffset); + if (pnp->signature == PNP_SIGNATURE) { + if (pnp->bev) + boot_add_bev(FLATPTR_TO_SEG(rom), pnp->bev, pnp->productname, + getRomPriority(sources, rom, rom_instance++)); + else if (pnp->bcv) + boot_add_bcv(FLATPTR_TO_SEG(rom), pnp->bcv, pnp->productname, + getRomPriority(sources, rom, rom_instance++)); + } else { + dprintf(1, "rom 0x%p is not PnP rom, no BEV and BCV capability\n", table); + } + regs->bx = 0; // FIXME regs->ax = 0; } diff --git a/src/optionroms.c b/src/optionroms.c index e906ab9..4f3848d 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -153,7 +153,7 @@ setRomSource(u64 *sources, struct rom_header *rom, u64 source) sources[((u32)rom - BUILD_ROM_START) / OPTION_ROM_ALIGN] = source; } -static int +int getRomPriority(u64 *sources, struct rom_header *rom, int instance) { u64 source = sources[((u32)rom - BUILD_ROM_START) / OPTION_ROM_ALIGN]; diff --git a/src/util.h b/src/util.h index b173fa8..0a52338 100644 --- a/src/util.h +++ b/src/util.h @@ -217,6 +217,7 @@ int is_pci_vga(struct pci_device *pci); void optionrom_setup(void); void vgarom_setup(void); void s3_resume_vga(void); +int getRomPriority(u64 *sources, struct rom_header *rom, int instance); extern int ScreenAndDebug; // pcibios.c -- 2.17.1

2 8

[ANNOUNCE] SeaBIOS 1.13.0
by Kevin O'Connor 09 Dec '19

09 Dec '19

The 1.13.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download ===== git shortlog -n rel-1.12.0..rel-1.13.0 ===== Gerd Hoffmann (25): vga: move modelist from bochsvga.c to new svgamodes.c vga: make memcpy_high() public vga: add atiext driver vga: add ati bios tables vbe: add edid support. ati: add edid support. bochsvga: add edid support. bochsdisplay: add edid support. bochsdisplay: parse resolution from edid. add get_keystroke_full() helper bootmenu: add support for more than 9 entries optionrom: disallow int19 redirect for pnp roms. ati-vga: make less verbose ati-vga: fix ati_read() ati-vga: make i2c register and bits configurable ati-vga: try vga ddc first ati-vga: add rage128 edid support bochsdisplay: add copyright and license to bochsdisplay.c ramfb: add copyright and license to ramfb.c cp437: add license to cp437.c ahci: zero-initialize port struct Revert "geometry: Apply LCHS values for boot devices" Revert "config: Add toggle for bootdevice information" Revert "geometry: Add boot_lchs_find_*() utility functions" Revert "geometry: Read LCHS from fw_cfg" Kevin O'Connor (11): output: Avoid thunking to 16bit mode in printf() if no vgabios docs: Update mailing list archive links docs: Fix cut-and-paste error in Mailinglist.md archive link usb-ehci: Clear pipe token on pipe reallocate pciinit: Use %pP shorthand for printing device ids in intel_igd_setup() virtio-pci: Use %pP format in dprintf() calls Makefile: Build with -Wno-address-of-packed-member svgamodes: Add copyright notice to vgasrc/svgamodes.c docs: Add developer-certificate-of-origin docs: Note release date for v1.12.1 docs: Note v1.13.0 release Sam Eiderman (10): smbios: Add missing zero byte to Type 0 geometry: Read LCHS from fw_cfg boot: Reorder functions in boot.c geometry: Add boot_lchs_find_*() utility functions config: Add toggle for bootdevice information geometry: Apply LCHS values for boot devices geometry: Read LCHS from fw_cfg boot: Build ata and scsi paths in function geometry: Add boot_lchs_find_*() utility functions geometry: Apply LCHS values for boot devices Stefan Berger (4): tcgbios: Use table to convert hash to buffer size tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks tpm: Require a response to have minimum size of a valid response header tcgbios: Check for enough bytes returned from TPM2_GetCapability Uwe Kleine-König (3): cbvga: reuse svga modes definitions from svgamodes.c Add additional resolutions for 16:9 displays: 1600x900 and 2560x1440 Remove dos line endings introduced in the last two commits David Woodhouse (2): csm: Sanitise alignment constraint in Legacy16GetTableAddress csm: Fix boot priority translation Denis Plotnikov (1): virtio: extend virtio queue size to 256 Joseph Pacheco-Corwin (1): bootsplash: Added support for 16/24/32bpp in one function Liran Alon (1): pvscsi: ring_desc do not have to be page aligned Stefano Garzarella (1): qemu: avoid debug prints if debugcon is not enabled Stephen Douthit (1): tpm: Check for TPM related ACPI tables before attempting hw probe

1 0

USB Keyboard and Mouse not Detected
by Ankita Mahato 09 Dec '19

09 Dec '19

Hi, I have some problem in SeaBIOS. USB keyboard and USB mouse are not detected. EHCI and OHCI are enabled. I cannot use my keyboard in my SeaBIOS. USB keyboard and USB mouse are enabled in SeaBIOS .config . The Linux kernel does detect them and I can use them in Linux. Some timeout is happening. Following is the part of the debug message where only keyboard is attached: Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: Set transfer mode to UDMA-6 AHCI/0: registering: "AHCI/0: WDC WD5000AZLX-00CL5A0 ATA-9 Hard-Disk (465 GiBytes)" Found 0 lpt ports Found 1 serial ports Searching bootorder for: /rom@img/uefi XHCI no devices found USB keyboard initialized WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000c00 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:178! Failure on hub port 3 reset WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 3 disconnect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7eccfd40 td=0x7eccfd40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 2 detect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7ecd0d40 td=0x7ecd0d40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 1 detect Initialized USB HUB (1 ports used) WARNING - Timeout at ehci_waittick:165! All threads complete. Scan for option roms Press ESC for boot menu. Thanks and Regards, Ankita L&T Technology Services Ltd www.LTTS.com L&T Technology Services Limited (LTTS) is committed to safeguard your data privacy. For more information to view our commitment towards data privacy under GDPR, please visit the privacy policy on our website www.Ltts.com. This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

1 0

[PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode
by Your Real Name 05 Dec '19

05 Dec '19

From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 11:23:04 -0700 Subject: [PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode On real hardware especially server platforms, there are many pci devices, bridges, either SoC integrated or addon. They can exhaust all the pci bus numbers. So when scanning the pci bus, we need to allow the bus number up to 255. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/hw/pcidevice.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index 8853cf7..acf15b4 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -26,6 +26,12 @@ pci_probe_devices(void) struct hlist_node **pprev = &PCIDevices.first; int extraroots = romfile_loadint("etc/extra-pci-roots", 0); int bus = -1, lastbus = 0, rootbuses = 0, count=0; + + // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff; + while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) { bus++; int bdf; -- 2.17.1

2 5

csm: Call pci_probe_devices() late until PrepareToBoot is invoked by UEFI
by Your Real Name 03 Dec '19

03 Dec '19

From 7dd0e8b98c71254148180b3cc432de1c4936526c Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 11:17:46 -0700 Subject: [PATCH 1/4] csm: Call pci_probe_devices() late until PrepareToBoot is invoked by UEFI On real hardware, some PCI devices are not detectable when UEFI BIOS invokes our InitializeYourself() function. But they are guaranteed to be available before UEFI invokes our PreparToBoot() function. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/fw/csm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/fw/csm.c b/src/fw/csm.c index 8359bcb..c8111cd 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -63,7 +63,6 @@ static void csm_maininit(struct bregs *regs) { interface_init(); - pci_probe_devices(); csm_compat_table.PnPInstallationCheckSegment = SEG_BIOS; csm_compat_table.PnPInstallationCheckOffset = get_pnp_offset(); @@ -143,6 +142,12 @@ handle_csm_0002(struct bregs *regs) return; } + // On real hardware, some PCI devices are not detectable when + // UEFI invokes our InitializeYourself() function. But they + // are guaranteed to be available before UEFI invokes our + // PreparToBoot() function. + pci_probe_devices(); + dprintf(3, "PrepareToBoot table %04x:%04x\n", regs->es, regs->bx); struct e820entry *p = (void *)csm_compat_table.E820Pointer; -- 2.17.1

2 2

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS December 2019