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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 09 Jan '17

09 Jan '17

On Fri, Jan 06, 2017 at 09:22:46AM +0200, Евгени Димитров wrote: > On Thu, Jan 5, 2017 at 6:29 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > On Thu, Jan 05, 2017 at 09:44:14AM +0200, Евгени Димитров wrote: > > > On Wed, Jan 4, 2017 at 4:52 PM, Kevin O'Connor <kevin(a)koconnor.net> > > wrote: > > > > > > > On Wed, Jan 04, 2017 at 03:57:33PM +0200, Евгени Димитров wrote: > > > > > Hi, > > > > > > > > > > I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When > > > > > trying to boot from an USB device I get the following error: > > > > > > > > > > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > > > > > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > > > > > ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 > > > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 > > > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 > > > > > WARNING - Timeout at ehci_wait_td:516! > > > > > ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 > > td=0x00006b40 > > > > > status=d0d80 > > > > > USB transmission failed > > > > > Unable to configure USB MSC drive. > > > > > phys_free f6030 (detail=0x0f7688a0) > > > > > Unable to configure USB MSC device. > > > > > > > > Did you disable threads in seabios (either via the kconfig option or > > > > via the /etc/threads runtime option)? It's not recommended to disable > > > > threads, and the USB code is less capable of handling timeouts when > > > > threads are disabled. Can you retry (and send the log) with threads > > > > enabled. > > > > > > > > If that fails, can you also try disabling CONFIG_USB_EHCI in Kconfig > > > > and send that log as well. > > > I get the same error with threads enabled. Disabling ehci did not help > > > either. Logs are attached as requested. > > > > It looks like the USB device is successfully identified and > > configured, but when sending the "inquiry" command to the drive behind > > the USB interface the connection halts. Not sure why that would be - > > it could be something with the controller, but it's odd that it > > happens with both the ohci and ehci controllers. > > > > If you boot to linux (using some other bootable device) what does > > 'lsusb' and 'lsusb -t' report? Have you tested with a different type > > of usb drive? > > > > -Kevin > > > > USB works on Linux. And yes I have tried a bunch of USB drives. All of them > failed with the same error. > > root@OpenWrt:/# lsusb > Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub > Bus 001 Device 002: ID 0011:7788 > Bus 001 Device 003: ID 058f:6377 Alcor Micro Corp. Multimedia Card Reader > Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub > root@OpenWrt:/# lsusb -t > /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=ohci-pci/4p, 12M > /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=ehci-pci/4p, 480M > |__ Port 1: Dev 3, If 0, Class=Mass Storage, Driver=, 480M > |__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=, 480M Are you trying to boot from the "Multimedia Card Reader" or from a regular USB flash drive? If you're not booting from the card reader, does the patch below help? -Kevin --- a/src/hw/usb-msc.c +++ b/src/hw/usb-msc.c @@ -203,6 +203,8 @@ usb_msc_setup(struct usbdevice_s *usbdev) goto fail; int maxlun = usb_msc_maxlun(usbdev->defpipe); + if (maxlun) + goto fail; int lun, pipesused = 0; for (lun = 0; lun < maxlun + 1; lun++) { int ret = usb_msc_lun_setup(inpipe, outpipe, usbdev, lun);

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 06 Jan '17

06 Jan '17

On Thu, Jan 05, 2017 at 09:44:14AM +0200, Евгени Димитров wrote: > On Wed, Jan 4, 2017 at 4:52 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > On Wed, Jan 04, 2017 at 03:57:33PM +0200, Евгени Димитров wrote: > > > Hi, > > > > > > I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When > > > trying to boot from an USB device I get the following error: > > > > > > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > > > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > > > ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 > > > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 > > > WARNING - Timeout at ehci_wait_td:516! > > > ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 td=0x00006b40 > > > status=d0d80 > > > USB transmission failed > > > Unable to configure USB MSC drive. > > > phys_free f6030 (detail=0x0f7688a0) > > > Unable to configure USB MSC device. > > > > Did you disable threads in seabios (either via the kconfig option or > > via the /etc/threads runtime option)? It's not recommended to disable > > threads, and the USB code is less capable of handling timeouts when > > threads are disabled. Can you retry (and send the log) with threads > > enabled. > > > > If that fails, can you also try disabling CONFIG_USB_EHCI in Kconfig > > and send that log as well. > I get the same error with threads enabled. Disabling ehci did not help > either. Logs are attached as requested. It looks like the USB device is successfully identified and configured, but when sending the "inquiry" command to the drive behind the USB interface the connection halts. Not sure why that would be - it could be something with the controller, but it's odd that it happens with both the ohci and ehci controllers. If you boot to linux (using some other bootable device) what does 'lsusb' and 'lsusb -t' report? Have you tested with a different type of usb drive? -Kevin

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Re: [SeaBIOS] USB timeout on ALIX.2C2 (CS5536)
by Kevin O'Connor 05 Jan '17

05 Jan '17

On Wed, Jan 04, 2017 at 03:57:33PM +0200, Евгени Димитров wrote: > Hi, > > I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When > trying to boot from an USB device I get the following error: > > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 > ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 > WARNING - Timeout at ehci_wait_td:516! > ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 td=0x00006b40 > status=d0d80 > USB transmission failed > Unable to configure USB MSC drive. > phys_free f6030 (detail=0x0f7688a0) > Unable to configure USB MSC device. Did you disable threads in seabios (either via the kconfig option or via the /etc/threads runtime option)? It's not recommended to disable threads, and the USB code is less capable of handling timeouts when threads are disabled. Can you retry (and send the log) with threads enabled. If that fails, can you also try disabling CONFIG_USB_EHCI in Kconfig and send that log as well. -Kevin

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USB timeout on ALIX.2C2 (CS5536)
by Евгени Димитров 04 Jan '17

04 Jan '17

Hi, I'm testing Coreboot with SeaBIOS as payload on my old Alix.2C2. When trying to boot from an USB device I get the following error: Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 ehci_send_pipe qh=0x000ecf00 dir=0 data=0x00006cf9 size=31 ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006dc4 size=36 ehci_send_pipe qh=0x000ecf80 dir=128 data=0x00006cec size=13 WARNING - Timeout at ehci_wait_td:516! ehci pipe=0x000ecf80 cur=00000000 tok=00000000 next=6b40 td=0x00006b40 status=d0d80 USB transmission failed Unable to configure USB MSC drive. phys_free f6030 (detail=0x0f7688a0) Unable to configure USB MSC device. Google found a thread from 2012 [1] where someone had the same problem with this particular chipset. Unfortunately he was unable to resolve the issue. Attached you will find the complete logs from both Coreboot and SeaBIOS. [1] https://www.coreboot.org/pipermail/coreboot/2012-October/071629.html

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how to enter into cmos-setup of seabios in qemu/kvm
by dw 04 Jan '17

04 Jan '17

Hi: I'm running a VM with qemu/kvm and libvirt,I want to know how to enter into cmos-setup of seabios. Anyone knows how to? Or there is not cmos-setup in seabios? please help me. thanks! dw

5 6

More than 9 boot devices
by Аладышев Константин 03 Jan '17

03 Jan '17

Is it possible in SeaBIOS to have working boot menu with amount of boot devices more than 9? I mean in this case we have boot device numbers with two digits, which is impossible to select. If I want to select string 12 and try to enter "12", SeaBIOS recognizes "1" and boot from device "1"...

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Re: [SeaBIOS] [PATCH v2] serialio: Support for mmap serial ports
by Kevin O'Connor 30 Dec '16

30 Dec '16

On Thu, Dec 29, 2016 at 10:03:06AM +0100, Ricardo Ribalda Delgado wrote: > Hi Kevin > > On Thu, Dec 29, 2016 at 1:45 AM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > Thanks. I'm a little concerned about overloading the meaning of > > CONFIG_DEBUG_SERIAL_PORT to mean either port or memory address. How > > about the modified patch below instead? > > Completely agree, the new version looks much better. I have also tried > it on my bettong-alike board > > You may add > > Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Thanks. I committed this change. -Kevin

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[PATCH v2] serialio: Support for mmap serial ports
by Ricardo Ribalda Delgado 29 Dec '16

29 Dec '16

Some chipsets have memory mapped serial ports. The protocol is the same as an standard uart, but with memory read/write instead of inb/outb. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- v2: Fix typos Suggested by: Kevin O'Connor <kevin(a)koconnor.net>: -Only operate in 32bit mode if !MODESEGMENT src/Kconfig | 3 +++ src/hw/serialio.c | 32 +++++++++++++++++++++++++------- src/serial.c | 2 +- 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e767be1351c3..e53713f2c527 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -532,6 +532,9 @@ menu "Debugging" default 0x3f8 help Base port for serial - generally 0x3f8, 0x2f8, 0x3e8, or 0x2e8. + On some chipsets the serial port is memory mapped, in those cases + provide the 32 bit address. E.g. 0xFEDC6000 for the AMD Kern + (a.k.a Hudson UART). config DEBUG_IO depends on QEMU_HARDWARE && DEBUG_LEVEL != 0 diff --git a/src/hw/serialio.c b/src/hw/serialio.c index 6486fc086b1c..6ed8e7b1880d 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -17,6 +17,24 @@ #define DEBUG_TIMEOUT 100000 +static void +serial_outb(u8 val, u32 port, u8 offset){ + if (port < 0x10000) + return outb(val, port + offset); + if (MODESEGMENT) + return; + writeb((void *)port + 4*offset, val); +} + +static u8 +serial_inb(u32 port, u8 offset){ + if (port < 0x10000) + return inb(port + offset); + if (MODESEGMENT) + return 0xff; + return readb((void *)port + 4*offset); +} + // Setup the debug serial port for output. void serial_debug_preinit(void) @@ -25,12 +43,12 @@ serial_debug_preinit(void) return; // setup for serial logging: 8N1 u8 oldparam, newparam = 0x03; - oldparam = inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LCR); - outb(newparam, CONFIG_DEBUG_SERIAL_PORT+SEROFF_LCR); + oldparam = serial_inb(CONFIG_DEBUG_SERIAL_PORT, SEROFF_LCR); + serial_outb(newparam, CONFIG_DEBUG_SERIAL_PORT, SEROFF_LCR); // Disable irqs u8 oldier, newier = 0; - oldier = inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_IER); - outb(newier, CONFIG_DEBUG_SERIAL_PORT+SEROFF_IER); + oldier = serial_inb(CONFIG_DEBUG_SERIAL_PORT, SEROFF_IER); + serial_outb(newier, CONFIG_DEBUG_SERIAL_PORT, SEROFF_IER); if (oldparam != newparam || oldier != newier) dprintf(1, "Changing serial settings was %x/%x now %x/%x\n" @@ -44,11 +62,11 @@ serial_debug(char c) if (!CONFIG_DEBUG_SERIAL) return; int timeout = DEBUG_TIMEOUT; - while ((inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LSR) & 0x20) != 0x20) + while ((serial_inb(CONFIG_DEBUG_SERIAL_PORT, SEROFF_LSR) & 0x20) != 0x20) if (!timeout--) // Ran out of time. return; - outb(c, CONFIG_DEBUG_SERIAL_PORT+SEROFF_DATA); + serial_outb(c, CONFIG_DEBUG_SERIAL_PORT, SEROFF_DATA); } void @@ -66,7 +84,7 @@ serial_debug_flush(void) if (!CONFIG_DEBUG_SERIAL) return; int timeout = DEBUG_TIMEOUT; - while ((inb(CONFIG_DEBUG_SERIAL_PORT+SEROFF_LSR) & 0x60) != 0x60) + while ((serial_inb(CONFIG_DEBUG_SERIAL_PORT, SEROFF_LSR) & 0x60) != 0x60) if (!timeout--) // Ran out of time. return; diff --git a/src/serial.c b/src/serial.c index 88349c8a9267..27710cb19af9 100644 --- a/src/serial.c +++ b/src/serial.c @@ -21,7 +21,7 @@ static u16 detect_serial(u16 port, u8 timeout, u8 count) { - if (CONFIG_DEBUG_SERIAL && port == CONFIG_DEBUG_SERIAL_PORT + if (CONFIG_DEBUG_SERIAL && port == (u16) CONFIG_DEBUG_SERIAL_PORT && !romfile_loadint("etc/advertise-serial-debug-port", 1)) return 0; outb(0x02, port+SEROFF_IER); -- 2.10.2

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Problems with parallel build and SeaVGABIOS
by Paul Menzel 29 Dec '16

29 Dec '16

Dear SeaBIOS folks, building SeaBIOS for coreboot with SeaVGABIOS in parallel, I get an error. > $ nproc > 8 > $ git log --oneline -1 > b98c658 drop "etc/boot-cpus" fw_cfg file and reuse legacy QEMU_CFG_NB_CPUS > $ grep VGA_COREBOOT .config > CONFIG_VGA_COREBOOT=y > $ make menuconfig && make clean && make -j > scripts/kconfig/mconf /home/pmenzel/src/seabios/src/Kconfig > > > *** End of the configuration. > *** Execute 'make' to start the build or try 'make help'. > > Compiling to assembler out/src/asm-offsets.s > Precompiling out/vgasrc/vgalayout.lds > cc1: fatal error: opening output file out/vgasrc/vgalayout.lds: No such file or directory > compilation terminated. > Makefile:138: recipe for target 'out/vgasrc/vgalayout.lds' failed > make: *** [out/vgasrc/vgalayout.lds] Error 1 > make: *** Waiting for unfinished jobs.... > Build Kconfig config file Probably the Makefile just needs some tweaking. Please find the configuration file attached. Kind regards, Paul

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iPXE on multiple chips with the same PCI ID
by Аладышев Константин 29 Dec '16

29 Dec '16

I have a board with multiple external PCIe Ethernet I350 chips. In my lspci I have: 03.00.0 (4-port I350) 03.00.1 03.00.2 03.00.3 04.00.0 (4-port I350) 04.00.1 04.00.2 04.00.3 05.00.0 (2-port I350) 05.00.1 I builtin iPXE image to coreboot and I have all of these devices in Seabios bootmenu. But the problem is that I can only boot from ports of the first appeared chip. In the example above it will be 03.00.x boot devices. If I'll physically unplug 03.00.x chip, I'll be able to boot from 04.00.x boot devices. And if I'll unplug 03.00.x and 04.00.x chip, I'll be able to boot from 05.00.x boot devices. Does someone had the same problem and is there any idea of how to solve it? Coreboot+SeaBIOS log is in attachment (it has some additional printk's)

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