SeaBIOS

seabios@seabios.org

4 participants
3801 discussions

Re: [SeaBIOS] [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer
by Paul Menzel 22 Apr '17

22 Apr '17

[For the GRUB folks, this is about coreboot commit d67c6876 (Turn CBMEM console into a ring buffer that can persist across reboots) [1]. Julius’ message can be find in the coreboot list archive [2].] Dear Julius, Am Montag, den 10.04.2017, 15:50 -0700 schrieb Julius Werner: […] > The change may also cause some hiccups if you're using a newer version of > coreboot with an older version of cbmem (or SeaBIOS or whatever else reads > the console): it will not crash and it will still print the whole log, but > if the log has rolled over (into "ring buffer mode") it will print lines > out of order. This is unfortunately the best I can do with the way current > readers are implemented. I'm of course also updating the code for cbmem so > as soon as you deploy the new version it will be able to display buffers > from both old and new coreboot versions correctly. (I'll send patches to > align SeaBIOS and the Linux memconsole driver in the same manner as soon as > the coreboot patch is approved.) Could you please also check, if GRUB’s CBMEM console driver, and the the command cbmemc to display it need any updates? Thanks, Paul PS: Where can I get your S/MIME certificate, used to sign your email? [1] https://review.coreboot.org/18301 [2] https://mail.coreboot.org/pipermail/coreboot/2017-April/083950.html

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PCI regions mapping problem
by Stas Sergeev 21 Apr '17

21 Apr '17

Hello. I tried seabios on an emulator (not qemu) and faced the PCI memory regions overlap. After some debugging I came to the conclusion that seabios simply forgets to align the base addresses, and as the result, when the device aligns the address down by clearing the "dont care" bits, it can overlap the previous region. I fixed the problem with the attached simple patch. Still it is hard to believe such a bug can exist, so I wonder if I am missing something. Any suggestions to where should I dig to narrow the problem further? Or can it be that seabios actually has the bug like that and no one have noticed? :)

2 2

BootDevice description cut off
by Rene Shuster 21 Apr '17

21 Apr '17

Please change line 485 of src/boot.c and increase the BootDevice description length 'char desc' value from [60] to [80]. Right now it's cutting off text for some devices. 80 would most likely fix the issue and provide enough space for very lengthy descriptions. Example shown here: https://github.com/coreboot/seabios/pull/1 Thanks. -- Tech III * AppControl * Endpoint Protection * Server Maintenance Buncombe County Schools Technology Department Network Group ComicSans Awareness Campaign <http://comicsanscriminal.com>

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does virtio-pci support more queues?
by Zhenwei Pi 21 Apr '17

21 Apr '17

Hi, I did a very simple test : 1, modify qemu/hw/block/virtio-blk.c, let virtio-blk use 256 queue: *s->vq = virtio_add_queue(vdev, 128, virtio_blk_handle_output);* --> *s->vq = virtio_add_queue(vdev, 256 , virtio_blk_handle_output);* ** 2, compile qemu and run a VM which boots from virtio-blk disk. The VM can NOT boot because seabios use macro MAX_QUEUE_NUM as 128. So, does virtio-pci support more queues? Looking forward your reply! -- Rather than love ,than money ,than faith,than fame,than fairness,give me truth.

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Re: [SeaBIOS] [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer
by Gerd Hoffmann 12 Apr '17

12 Apr '17

Hi, > Right, sorry, I confused something while writing the explanation > there. Nevertheless, the SeaBIOS code will require a small adjustment > (same as the libpayload driver in the patch I linked) to continue > appending correctly after the log has rolled over, and I'll provide > that patch. Is it possible to figure whenever the cbmem buffer supports rollover or not, so a updated seabios version can work correctly with both old and new coreboot? cheers, Gerd

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Re: [SeaBIOS] [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer
by Haleigh Novak 11 Apr '17

11 Apr '17

Hello, Will the ability to change the 'Room allocated for console output in CBMEM' size still be available (and functional) for those need to view the full console output due to the addition of debugging/tracing lines? HN ________________________________ From: coreboot <coreboot-bounces(a)coreboot.org> on behalf of Julius Werner via coreboot <coreboot(a)coreboot.org> Sent: Monday, April 10, 2017 3:50 PM To: Coreboot; seabios(a)seabios.org Subject: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer Hi folks, I'm planning to make some changes to coreboot's CBMEM console with https://review.coreboot.org/#/c/18301 that should make it easier to debug problems spanning multiple reboots. I'm trying my best to avoid breaking previous behavior and keeping it compatible with older code, but there'll be some edge cases so Aaron suggested I announce it here. The basic idea is to turn the console into a persistent ring buffer. If coreboot finds an already initialized console in memory during boot, it will just continue appending to it rather than begin writing from the start of the buffer again. This means that if you run cbmem -c, the most recent boot will always be at the bottom of the output, and you can scroll further up to see logs from the boot before that (assuming you didn't lose DRAM power or something). It may also give some runtime firmware components (like we have on ARM64) a good place to log stuff and persist crash dumps in the future. The console buffer will fill up eventually with enough reboots, so when that happens we will start discarding the oldest lines from the log. This means the behavior if the log buffer is too small for even a single full boot will become slightly different: we'll only keep the latest lines, whereas previously we would only keep the earliest lines and a counter of dropped characters. I don't think this should be an issue though, since we normally should have enough buffer to fit a whole boot anyway (the default is currently 128KB which ought to be enough for any board). The change may also cause some hiccups if you're using a newer version of coreboot with an older version of cbmem (or SeaBIOS or whatever else reads the console): it will not crash and it will still print the whole log, but if the log has rolled over (into "ring buffer mode") it will print lines out of order. This is unfortunately the best I can do with the way current readers are implemented. I'm of course also updating the code for cbmem so as soon as you deploy the new version it will be able to display buffers from both old and new coreboot versions correctly. (I'll send patches to align SeaBIOS and the Linux memconsole driver in the same manner as soon as the coreboot patch is approved.) Let me know if you have any concerns about this.

2 1

Re: [SeaBIOS] RFC: Changing CBMEM console to run as a persistent ring-buffer
by Gerd Hoffmann 11 Apr '17

11 Apr '17

Hi, > The change may also cause some hiccups if you're using a newer version > of coreboot with an older version of cbmem (or SeaBIOS or whatever > else reads the console): seabios doesn't read the log, instead it'll append its own messages. Which I expect will continue to work fine, except when it hits the end of the log buffer, where seabios will simply stop logging instead of rolling over. cheers, Gerd

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RFC: Changing CBMEM console to run as a persistent ring-buffer
by Julius Werner 10 Apr '17

10 Apr '17

Hi folks, I'm planning to make some changes to coreboot's CBMEM console with https://review.coreboot.org/#/c/18301 that should make it easier to debug problems spanning multiple reboots. I'm trying my best to avoid breaking previous behavior and keeping it compatible with older code, but there'll be some edge cases so Aaron suggested I announce it here. The basic idea is to turn the console into a persistent ring buffer. If coreboot finds an already initialized console in memory during boot, it will just continue appending to it rather than begin writing from the start of the buffer again. This means that if you run cbmem -c, the most recent boot will always be at the bottom of the output, and you can scroll further up to see logs from the boot before that (assuming you didn't lose DRAM power or something). It may also give some runtime firmware components (like we have on ARM64) a good place to log stuff and persist crash dumps in the future. The console buffer will fill up eventually with enough reboots, so when that happens we will start discarding the oldest lines from the log. This means the behavior if the log buffer is too small for even a single full boot will become slightly different: we'll only keep the latest lines, whereas previously we would only keep the earliest lines and a counter of dropped characters. I don't think this should be an issue though, since we normally should have enough buffer to fit a whole boot anyway (the default is currently 128KB which ought to be enough for any board). The change may also cause some hiccups if you're using a newer version of coreboot with an older version of cbmem (or SeaBIOS or whatever else reads the console): it will not crash and it will still print the whole log, but if the log has rolled over (into "ring buffer mode") it will print lines out of order. This is unfortunately the best I can do with the way current readers are implemented. I'm of course also updating the code for cbmem so as soon as you deploy the new version it will be able to display buffers from both old and new coreboot versions correctly. (I'll send patches to align SeaBIOS and the Linux memconsole driver in the same manner as soon as the coreboot patch is approved.) Let me know if you have any concerns about this.

1 0

[PATCH 0/9] add support for generic lun enumeration
by Roman Kagan 10 Apr '17

10 Apr '17

A number of SCSI drivers currently only see luns #0 in their targets. This may be a problem when drives have to be assigned bigger lun numbers, e.g. because the storage controllers don't provide enough target numbers to accomodate all drives. (In particular, I'm about to submit a driver for Hyper-V VMBus SCSI controller which is limited to 2 targets only). This series adds generic SCSI lun enumeration (either via REPORT LUNS command or sequentially trying every lun), and makes the respective drivers use it. Note that the series has only been minimally tested against a recent QEMU. Roman Kagan (9): blockcmd: accept only disks and CD-ROMs blockcmd: generic SCSI luns enumeration virtio-scsi: enumerate luns with REPORT LUNS esp-scsi: enumerate luns with REPORT LUNS usb-uas: enumerate luns with REPORT LUNS pvscsi: fix the comment about lun enumeration mpt-scsi: try to enumerate luns with REPORT LUNS lsi-scsi: reset in case of a serious problem lsi-scsi: try to enumerate luns with REPORT LUNS src/hw/blockcmd.h | 4 +++ src/hw/blockcmd.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/hw/esp-scsi.c | 35 +++++++++++++------ src/hw/lsi-scsi.c | 39 +++++++++++++++------ src/hw/mpt-scsi.c | 40 ++++++++++++++-------- src/hw/pvscsi.c | 2 +- src/hw/usb-uas.c | 45 +++++++++++++++--------- src/hw/virtio-scsi.c | 38 ++++++++++++++------- 8 files changed, 235 insertions(+), 64 deletions(-) -- 2.9.3

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Support for QEMU's virtio modern-pio-notify option?
by Jonathan Boeing 08 Apr '17

08 Apr '17

Does SeaBIOS support QEMU's modern-pio-notify option for virtio devices? My VM hangs during boot when enumerating the virtio-scsi drive if I set modern-pio-notify=on. Specifically, it spins forever in the while(!vring_more_used(vq)) loop in the call stack: scsi_drive_setup() cdb_get_inquiry() ... virtio_scsi_process_op() I get the hang with the minimal command line of: qemu-system-x86_64 -device virtio-scsi-pci,modern-pio-notify=on I'm using QEMU 2.8.0, and both SeaBIOS 1.10.1 and 1.10.2 Here's the debug log: SeaBIOS (version 1.10.1-20170402_032207-jb2) BUILD: gcc: (Gentoo 5.4.0-r3 p1.3, pie-0.6.5) 5.4.0 binutils: (Gentoo 2.27 p1.0) 2.27 No Xen hypervisor found. enabling shadow ram Running on QEMU (q35) Running on KVM Add to e820 map: 00000000 80000000 1 Add to e820 map: fffc0000 00040000 2 RamSize: 0x80000000 [cmos] malloc preinit Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Add to e820 map: 7ffc0000 00040000 2 phys_alloc zone=0x000eb2b4 size=79328 align=20 ret=7ffac980 (detail=0x7ffac950) Relocating init from 0x000d7da0 to 0x7ffac980 (size 79328) malloc init Found QEMU fw_cfg QEMU fw_cfg DMA interface supported phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac850 (detail=0x7ffac820) Add romfile: etc/show-boot-menu (size=2) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac780 (detail=0x7ffac750) Add romfile: etc/irq0-override (size=1) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac6b0 (detail=0x7ffac680) Add romfile: etc/max-cpus (size=2) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac5e0 (detail=0x7ffac5b0) Add romfile: etc/numa-cpu-map (size=16) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac510 (detail=0x7ffac4e0) Add romfile: etc/numa-nodes (size=0) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac440 (detail=0x7ffac410) Add romfile: bootorder (size=0) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac370 (detail=0x7ffac340) Add romfile: etc/acpi/rsdp (size=36) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac2a0 (detail=0x7ffac270) Add romfile: etc/acpi/tables (size=131072) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac1d0 (detail=0x7ffac1a0) Add romfile: etc/boot-fail-wait (size=4) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac100 (detail=0x7ffac0d0) Add romfile: etc/e820 (size=40) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac030 (detail=0x7ffac000) Add romfile: etc/msr_feature_control (size=8) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabf60 (detail=0x7ffabf30) Add romfile: etc/smbios/smbios-anchor (size=31) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabe90 (detail=0x7ffabe60) Add romfile: etc/smbios/smbios-tables (size=308) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabdc0 (detail=0x7ffabd90) Add romfile: etc/system-states (size=6) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabcf0 (detail=0x7ffabcc0) Add romfile: etc/table-loader (size=4096) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabc20 (detail=0x7ffabbf0) Add romfile: etc/tpm/log (size=0) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabb50 (detail=0x7ffabb20) Add romfile: genroms/kvmvapic.bin (size=9216) phys_alloc zone=0x7ffbfe94 size=41 align=10 ret=7ffabaf0 (detail=0x7ffabac0) Copying romfile 'etc/e820' (len 40) Add to e820 map: feffc000 00004000 2 RamBlock: addr 0x0000000000000000 len 0x0000000080000000 [e820] Moving pm_base to 0x600 init ivt init bda Add to e820 map: 0009fc00 00000400 2 init bios32 init PMM init PNPBIOS table init keyboard init mouse init pic math cp init pci setup === PCI bus & bridge init === PCI: pci_bios_init_bus_rec bus = 0x0 === PCI device probing === PCI probe phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffabaa0 (detail=0x7ffaba70) PCI device 00:00.0 (vd=8086:29c0 c=0600) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffaba50 (detail=0x7ffaba20) PCI device 00:01.0 (vd=1234:1111 c=0300) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffaba00 (detail=0x7ffab9d0) PCI device 00:02.0 (vd=1af4:1048 c=0100) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab9b0 (detail=0x7ffab980) PCI device 00:03.0 (vd=1af4:1041 c=0200) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab960 (detail=0x7ffab930) PCI device 00:04.0 (vd=1af4:1052 c=0980) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab910 (detail=0x7ffab8e0) PCI device 00:1f.0 (vd=8086:2918 c=0601) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab8c0 (detail=0x7ffab890) PCI device 00:1f.2 (vd=8086:2922 c=0106) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab870 (detail=0x7ffab840) PCI device 00:1f.3 (vd=8086:2930 c=0c05) Found 8 PCI devices (max PCI bus is 00) Add to e820 map: b0000000 10000000 2 === PCI new allocation pass #1 === phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab810 (detail=0x7ffab7e0) PCI: check devices phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab7b0 (detail=0x7ffab780) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab750 (detail=0x7ffab720) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab6f0 (detail=0x7ffab6c0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab690 (detail=0x7ffab660) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab630 (detail=0x7ffab600) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab5d0 (detail=0x7ffab5a0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab570 (detail=0x7ffab540) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab510 (detail=0x7ffab4e0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab4b0 (detail=0x7ffab480) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab450 (detail=0x7ffab420) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab3f0 (detail=0x7ffab3c0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab390 (detail=0x7ffab360) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab330 (detail=0x7ffab300) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab2d0 (detail=0x7ffab2a0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab270 (detail=0x7ffab240) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab210 (detail=0x7ffab1e0) === PCI new allocation pass #2 === PCI: IO: c000 - c06b PCI: 32: 00000000c0000000 - 00000000fec00000 PCI: map device bdf=00:1f.3 bar 4, addr 0000c000, size 00000040 [io] phys_free 7ffab210 (detail=0x7ffab1e0) PCI: map device bdf=00:1f.2 bar 4, addr 0000c040, size 00000020 [io] phys_free 7ffab2d0 (detail=0x7ffab2a0) PCI: map device bdf=00:02.0 bar 2, addr 0000c060, size 00000004 [io] phys_free 7ffab630 (detail=0x7ffab600) PCI: map device bdf=00:03.0 bar 2, addr 0000c064, size 00000004 [io] phys_free 7ffab510 (detail=0x7ffab4e0) PCI: map device bdf=00:04.0 bar 2, addr 0000c068, size 00000004 [io] phys_free 7ffab390 (detail=0x7ffab360) PCI: map device bdf=00:03.0 bar 6, addr feb80000, size 00040000 [mem] phys_free 7ffab450 (detail=0x7ffab420) PCI: map device bdf=00:01.0 bar 6, addr febc0000, size 00010000 [mem] phys_free 7ffab6f0 (detail=0x7ffab6c0) PCI: map device bdf=00:01.0 bar 2, addr febd0000, size 00001000 [mem] phys_free 7ffab750 (detail=0x7ffab720) PCI: map device bdf=00:02.0 bar 1, addr febd1000, size 00001000 [mem] phys_free 7ffab690 (detail=0x7ffab660) PCI: map device bdf=00:03.0 bar 1, addr febd2000, size 00001000 [mem] phys_free 7ffab570 (detail=0x7ffab540) PCI: map device bdf=00:04.0 bar 1, addr febd3000, size 00001000 [mem] phys_free 7ffab3f0 (detail=0x7ffab3c0) PCI: map device bdf=00:1f.2 bar 5, addr febd4000, size 00001000 [mem] phys_free 7ffab270 (detail=0x7ffab240) PCI: map device bdf=00:01.0 bar 0, addr c0000000, size 20000000 [prefmem] phys_free 7ffab7b0 (detail=0x7ffab780) PCI: map device bdf=00:02.0 bar 4, addr e0000000, size 00004000 [prefmem] phys_free 7ffab5d0 (detail=0x7ffab5a0) PCI: map device bdf=00:03.0 bar 4, addr e0004000, size 00004000 [prefmem] phys_free 7ffab4b0 (detail=0x7ffab480) PCI: map device bdf=00:04.0 bar 4, addr e0008000, size 00004000 [prefmem] phys_free 7ffab330 (detail=0x7ffab300) PCI: init bdf=00:00.0 id=8086:29c0 PCI: init bdf=00:01.0 id=1234:1111 PCI: init bdf=00:02.0 id=1af4:1048 PCI: init bdf=00:03.0 id=1af4:1041 PCI: init bdf=00:04.0 id=1af4:1052 PCI: init bdf=00:1f.0 id=8086:2918 Q35 LPC init: elcr=00 0c Add to e820 map: fed1c000 00004000 2 Using pmtimer, ioport 0x608 PCI: init bdf=00:1f.2 id=8086:2922 PCI: init bdf=00:1f.3 id=8086:2930 phys_free 7ffab810 (detail=0x7ffab7e0) PCI: Using 00:01.0 for primary VGA init smm init mtrr handle_smp: apic_id=0x1 Found 2 cpu(s) max supported 2 cpu(s) init PIR table phys_alloc zone=0x7ffbfe9c size=128 align=10 ret=f5a60 (detail=0x7ffab810) Copying PIR from 0x7ffbfc80 to 0x000f5a60 init MPTable phys_alloc zone=0x7ffbfe94 size=32768 align=10 ret=7ffa3810 (detail=0x7ffa37e0) phys_alloc zone=0x7ffbfe9c size=240 align=10 ret=f5970 (detail=0x7ffa37b0) Copying MPTABLE from 0x00006e4c/7ffa3810 to 0x000f5970 phys_free 7ffa3810 (detail=0x7ffa37e0) phys_alloc zone=0x7ffbfe94 size=308 align=10 ret=7ffab6d0 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe9c size=379 align=10 ret=f57f0 (detail=0x7ffab670) phys_free 7ffab6d0 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe9c size=31 align=10 ret=f57d0 (detail=0x7ffab7e0) Copying SMBIOS entry point from 0x00006e4c to 0x000f57d0 load ACPI tables phys_alloc zone=0x7ffbfe94 size=4097 align=10 ret=7ffaa660 (detail=0x7ffab7b0) Copying romfile 'etc/table-loader' (len 4096) phys_alloc zone=0x7ffbfe94 size=260 align=10 ret=7ffab6a0 (detail=0x7ffaa630) phys_alloc zone=0x7ffbfe9c size=36 align=10 ret=f57a0 (detail=0x7ffaa600) phys_alloc zone=0x7ffbfea0 size=131072 align=40 ret=7ffe0000 (detail=0x7ffaa5d0) phys_free 7ffab6a0 (detail=0x7ffaa630) phys_free 7ffaa660 (detail=0x7ffab7b0) init timer Scan for VGA option rom Attempting to init PCI bdf 00:01.0 (vd 1234:1111) Attempting to map option rom on dev 00:01.0 Option rom sizing returned febc0000 ffff0000 Inspecting possible rom at 0xfebc0000 (vd=1234:1111 bdf=00:01.0) WARNING! Found unaligned PCI rom (vd=1234:1111) Copying option rom (size 41472) from 0xfebc0000 to 0x000c0000 Checking rom 0x000c0000 (sig aa55 size 81) Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.10.1-20170402_032207-jb2) init usb init ps2port phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa9000 (detail=0x7ffab7b0) /7ffa9000\ Start thread |7ffa9000| i8042_flush |7ffa9000| i8042_command cmd=1aa |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_read |7ffa9000| i8042 param=55 |7ffa9000| i8042_command cmd=1ab |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_read |7ffa9000| i8042 param=0 |7ffa9000| ps2_command aux=0 cmd=1ff |7ffa9000| i8042 ctr old=30 new=30 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write init floppy drives init hard drives init ahci phys_alloc zone=0x7ffbfea4 size=2048 align=10 ret=ea2e0 (detail=0x7ffab780) phys_alloc zone=0x7ffbfe9c size=20 align=10 ret=f5780 (detail=0x7ffab750) AHCI controller at 00:1f.2, iobase 0xfebd4000, irq 10 AHCI: cap 0x40141f05, ports_impl 0x3f phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffab700 (detail=0x7ffab6d0) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffab000 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab500 (detail=0x7ffab640) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab400 (detail=0x7ffab610) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa8000 (detail=0x7ffaafd0) /7ffa8000\ Start thread |7ffa8000| AHCI/0: probing |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=ff |7ffa9000| i8042_kbd_write c=255 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| ps2 read aa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_command aux=0 cmd=f5 |7ffa9000| i8042 ctr old=30 new=30 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaaf80 (detail=0x7ffaaf50) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffaa800 (detail=0x7ffaaf20) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaae00 (detail=0x7ffaadd0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaac00 (detail=0x7ffaada0) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa7000 (detail=0x7ffaad70) /7ffa7000\ Start thread |7ffa7000| AHCI/1: probing |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=f5 |7ffa9000| i8042_kbd_write c=245 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_command aux=0 cmd=10f0 |7ffa9000| i8042 ctr old=30 new=30 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaad20 (detail=0x7ffaa7d0) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffaa000 (detail=0x7ffaa7a0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaa400 (detail=0x7ffaa770) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffa6f00 (detail=0x7ffaa740) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa5000 (detail=0x7ffaa710) /7ffa5000\ Start thread |7ffa5000| AHCI/2: probing |7ffa8000| AHCI/0: link down |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=f0 |7ffa9000| i8042_kbd_write c=240 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| ps2_sendbyte aux=0 cmd=2 |7ffa9000| i8042_kbd_write c=2 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_command aux=0 cmd=f4 |7ffa9000| i8042 ctr old=61 new=70 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaa6c0 (detail=0x7ffaa690) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffa6800 (detail=0x7ffaa660) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffa6e00 (detail=0x7ffaa630) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffa6d00 (detail=0x7ffaa5a0) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa4000 (detail=0x7ffaa570) /7ffa4000\ Start thread |7ffa4000| AHCI/3: probing |7ffa7000| AHCI/1: link down |7ffa8000| phys_free 7ffab000 (detail=0x7ffab6a0) |7ffa8000| phys_free 7ffab500 (detail=0x7ffab640) |7ffa8000| phys_free 7ffab400 (detail=0x7ffab610) |7ffa8000| phys_free 7ffab700 (detail=0x7ffab6d0) \7ffa8000/ End thread phys_free 7ffa8000 (detail=0x7ffaafd0) |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=f4 |7ffa9000| i8042_kbd_write c=244 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| PS2 keyboard initialized \7ffa9000/ End thread phys_free 7ffa9000 (detail=0x7ffab7b0) phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffab700 (detail=0x7ffab7b0) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffab000 (detail=0x7ffab6d0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab500 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab400 (detail=0x7ffab640) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa9000 (detail=0x7ffab610) /7ffa9000\ Start thread |7ffa9000| AHCI/4: probing |7ffa5000| AHCI/2: link down |7ffa7000| phys_free 7ffaa800 (detail=0x7ffaaf20) |7ffa7000| phys_free 7ffaae00 (detail=0x7ffaadd0) |7ffa7000| phys_free 7ffaac00 (detail=0x7ffaada0) |7ffa7000| phys_free 7ffaaf80 (detail=0x7ffaaf50) \7ffa7000/ End thread phys_free 7ffa7000 (detail=0x7ffaad70) phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaafb0 (detail=0x7ffaaf80) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffaa800 (detail=0x7ffaaf50) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaae00 (detail=0x7ffaaf20) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaac00 (detail=0x7ffaadd0) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa8000 (detail=0x7ffaada0) /7ffa8000\ Start thread |7ffa8000| AHCI/5: probing |7ffa4000| AHCI/3: link down |7ffa5000| phys_free 7ffaa000 (detail=0x7ffaa7a0) |7ffa5000| phys_free 7ffaa400 (detail=0x7ffaa770) |7ffa5000| phys_free 7ffa6f00 (detail=0x7ffaa740) |7ffa5000| phys_free 7ffaad20 (detail=0x7ffaa7d0) \7ffa5000/ End thread phys_free 7ffa5000 (detail=0x7ffaa710) init virtio-blk init virtio-scsi phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa7000 (detail=0x7ffaad70) /7ffa7000\ Start thread |7ffa7000| found virtio-scsi at 00:02.0 |7ffa7000| phys_alloc zone=0x7ffbfea0 size=55 align=10 ret=7ffdffc0 (detail=0x7ffaad40) |7ffa7000| pci dev 0:2 virtio cap at 0x98 type 5 [pci cfg access] |7ffa7000| pci dev 0:2 virtio cap at 0x84 type 2 bar 2 at 0x0000c060 off +0x0000 [io] |7ffa7000| pci dev 0:2 virtio cap at 0x60 type 4 bar 4 at 0xe0000000 off +0x2000 [mmio] |7ffa7000| pci dev 0:2 virtio cap at 0x50 type 3 bar 4 at 0xe0000000 off +0x1000 [mmio] |7ffa7000| pci dev 0:2 virtio cap at 0x40 type 1 bar 4 at 0xe0000000 off +0x0000 [mmio] |7ffa7000| pci dev 00:02.0 using modern (1.0) virtio mode |7ffa7000| phys_alloc zone=0x7ffbfea0 size=5408 align=1000 ret=7ffde000 (detail=0x7ffaad10) |7ffa7000| phys_alloc zone=0x7ffbfe9c size=52 align=10 ret=f5740 (detail=0x7ffaa7d0) |7ffa7000| Searching bootorder for: /pci@i0cf8/*@2/*@0/*@0,0 |7ffa9000| AHCI/4: link down |7ffa4000| phys_free 7ffa6800 (detail=0x7ffaa660) |7ffa4000| phys_free 7ffa6e00 (detail=0x7ffaa630) |7ffa4000| phys_free 7ffa6d00 (detail=0x7ffaa5a0) |7ffa4000| phys_free 7ffaa6c0 (detail=0x7ffaa690) \7ffa4000/ End thread phys_free 7ffa4000 (detail=0x7ffaa570) init lsi53c895a init esp init megasas init pvscsi init MPT init lpt Found 0 lpt ports init serial Found 0 serial ports i8042_command cmd=ae i8042_wait_write |7ffa8000| AHCI/5: link down |7ffa9000| phys_free 7ffab000 (detail=0x7ffab6d0) |7ffa9000| phys_free 7ffab500 (detail=0x7ffab6a0) |7ffa9000| phys_free 7ffab400 (detail=0x7ffab640) |7ffa9000| phys_free 7ffab700 (detail=0x7ffab7b0) \7ffa9000/ End thread phys_free 7ffa9000 (detail=0x7ffab610) |7ffa8000| phys_free 7ffaa800 (detail=0x7ffaaf50) |7ffa8000| phys_free 7ffaae00 (detail=0x7ffaaf20) |7ffa8000| phys_free 7ffaac00 (detail=0x7ffaadd0) |7ffa8000| phys_free 7ffaafb0 (detail=0x7ffaaf80) \7ffa8000/ End thread phys_free 7ffa8000 (detail=0x7ffaada0) Thanks, Jonathan Boeing

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