SeaBIOS

seabios@seabios.org

3783 discussions

[PATCH 0/9] add support for generic lun enumeration
by Roman Kagan 10 Apr '17

10 Apr '17

A number of SCSI drivers currently only see luns #0 in their targets. This may be a problem when drives have to be assigned bigger lun numbers, e.g. because the storage controllers don't provide enough target numbers to accomodate all drives. (In particular, I'm about to submit a driver for Hyper-V VMBus SCSI controller which is limited to 2 targets only). This series adds generic SCSI lun enumeration (either via REPORT LUNS command or sequentially trying every lun), and makes the respective drivers use it. Note that the series has only been minimally tested against a recent QEMU. Roman Kagan (9): blockcmd: accept only disks and CD-ROMs blockcmd: generic SCSI luns enumeration virtio-scsi: enumerate luns with REPORT LUNS esp-scsi: enumerate luns with REPORT LUNS usb-uas: enumerate luns with REPORT LUNS pvscsi: fix the comment about lun enumeration mpt-scsi: try to enumerate luns with REPORT LUNS lsi-scsi: reset in case of a serious problem lsi-scsi: try to enumerate luns with REPORT LUNS src/hw/blockcmd.h | 4 +++ src/hw/blockcmd.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/hw/esp-scsi.c | 35 +++++++++++++------ src/hw/lsi-scsi.c | 39 +++++++++++++++------ src/hw/mpt-scsi.c | 40 ++++++++++++++-------- src/hw/pvscsi.c | 2 +- src/hw/usb-uas.c | 45 +++++++++++++++--------- src/hw/virtio-scsi.c | 38 ++++++++++++++------- 8 files changed, 235 insertions(+), 64 deletions(-) -- 2.9.3

5 26

Support for QEMU's virtio modern-pio-notify option?
by Jonathan Boeing 09 Apr '17

09 Apr '17

Does SeaBIOS support QEMU's modern-pio-notify option for virtio devices? My VM hangs during boot when enumerating the virtio-scsi drive if I set modern-pio-notify=on. Specifically, it spins forever in the while(!vring_more_used(vq)) loop in the call stack: scsi_drive_setup() cdb_get_inquiry() ... virtio_scsi_process_op() I get the hang with the minimal command line of: qemu-system-x86_64 -device virtio-scsi-pci,modern-pio-notify=on I'm using QEMU 2.8.0, and both SeaBIOS 1.10.1 and 1.10.2 Here's the debug log: SeaBIOS (version 1.10.1-20170402_032207-jb2) BUILD: gcc: (Gentoo 5.4.0-r3 p1.3, pie-0.6.5) 5.4.0 binutils: (Gentoo 2.27 p1.0) 2.27 No Xen hypervisor found. enabling shadow ram Running on QEMU (q35) Running on KVM Add to e820 map: 00000000 80000000 1 Add to e820 map: fffc0000 00040000 2 RamSize: 0x80000000 [cmos] malloc preinit Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Add to e820 map: 7ffc0000 00040000 2 phys_alloc zone=0x000eb2b4 size=79328 align=20 ret=7ffac980 (detail=0x7ffac950) Relocating init from 0x000d7da0 to 0x7ffac980 (size 79328) malloc init Found QEMU fw_cfg QEMU fw_cfg DMA interface supported phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac850 (detail=0x7ffac820) Add romfile: etc/show-boot-menu (size=2) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac780 (detail=0x7ffac750) Add romfile: etc/irq0-override (size=1) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac6b0 (detail=0x7ffac680) Add romfile: etc/max-cpus (size=2) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac5e0 (detail=0x7ffac5b0) Add romfile: etc/numa-cpu-map (size=16) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac510 (detail=0x7ffac4e0) Add romfile: etc/numa-nodes (size=0) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac440 (detail=0x7ffac410) Add romfile: bootorder (size=0) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac370 (detail=0x7ffac340) Add romfile: etc/acpi/rsdp (size=36) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac2a0 (detail=0x7ffac270) Add romfile: etc/acpi/tables (size=131072) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac1d0 (detail=0x7ffac1a0) Add romfile: etc/boot-fail-wait (size=4) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac100 (detail=0x7ffac0d0) Add romfile: etc/e820 (size=40) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffac030 (detail=0x7ffac000) Add romfile: etc/msr_feature_control (size=8) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabf60 (detail=0x7ffabf30) Add romfile: etc/smbios/smbios-anchor (size=31) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabe90 (detail=0x7ffabe60) Add romfile: etc/smbios/smbios-tables (size=308) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabdc0 (detail=0x7ffabd90) Add romfile: etc/system-states (size=6) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabcf0 (detail=0x7ffabcc0) Add romfile: etc/table-loader (size=4096) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabc20 (detail=0x7ffabbf0) Add romfile: etc/tpm/log (size=0) phys_alloc zone=0x7ffbfe94 size=148 align=10 ret=7ffabb50 (detail=0x7ffabb20) Add romfile: genroms/kvmvapic.bin (size=9216) phys_alloc zone=0x7ffbfe94 size=41 align=10 ret=7ffabaf0 (detail=0x7ffabac0) Copying romfile 'etc/e820' (len 40) Add to e820 map: feffc000 00004000 2 RamBlock: addr 0x0000000000000000 len 0x0000000080000000 [e820] Moving pm_base to 0x600 init ivt init bda Add to e820 map: 0009fc00 00000400 2 init bios32 init PMM init PNPBIOS table init keyboard init mouse init pic math cp init pci setup === PCI bus & bridge init === PCI: pci_bios_init_bus_rec bus = 0x0 === PCI device probing === PCI probe phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffabaa0 (detail=0x7ffaba70) PCI device 00:00.0 (vd=8086:29c0 c=0600) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffaba50 (detail=0x7ffaba20) PCI device 00:01.0 (vd=1234:1111 c=0300) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffaba00 (detail=0x7ffab9d0) PCI device 00:02.0 (vd=1af4:1048 c=0100) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab9b0 (detail=0x7ffab980) PCI device 00:03.0 (vd=1af4:1041 c=0200) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab960 (detail=0x7ffab930) PCI device 00:04.0 (vd=1af4:1052 c=0980) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab910 (detail=0x7ffab8e0) PCI device 00:1f.0 (vd=8086:2918 c=0601) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab8c0 (detail=0x7ffab890) PCI device 00:1f.2 (vd=8086:2922 c=0106) phys_alloc zone=0x7ffbfe94 size=32 align=10 ret=7ffab870 (detail=0x7ffab840) PCI device 00:1f.3 (vd=8086:2930 c=0c05) Found 8 PCI devices (max PCI bus is 00) Add to e820 map: b0000000 10000000 2 === PCI new allocation pass #1 === phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab810 (detail=0x7ffab7e0) PCI: check devices phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab7b0 (detail=0x7ffab780) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab750 (detail=0x7ffab720) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab6f0 (detail=0x7ffab6c0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab690 (detail=0x7ffab660) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab630 (detail=0x7ffab600) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab5d0 (detail=0x7ffab5a0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab570 (detail=0x7ffab540) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab510 (detail=0x7ffab4e0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab4b0 (detail=0x7ffab480) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab450 (detail=0x7ffab420) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab3f0 (detail=0x7ffab3c0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab390 (detail=0x7ffab360) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab330 (detail=0x7ffab300) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab2d0 (detail=0x7ffab2a0) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab270 (detail=0x7ffab240) phys_alloc zone=0x7ffbfe94 size=40 align=10 ret=7ffab210 (detail=0x7ffab1e0) === PCI new allocation pass #2 === PCI: IO: c000 - c06b PCI: 32: 00000000c0000000 - 00000000fec00000 PCI: map device bdf=00:1f.3 bar 4, addr 0000c000, size 00000040 [io] phys_free 7ffab210 (detail=0x7ffab1e0) PCI: map device bdf=00:1f.2 bar 4, addr 0000c040, size 00000020 [io] phys_free 7ffab2d0 (detail=0x7ffab2a0) PCI: map device bdf=00:02.0 bar 2, addr 0000c060, size 00000004 [io] phys_free 7ffab630 (detail=0x7ffab600) PCI: map device bdf=00:03.0 bar 2, addr 0000c064, size 00000004 [io] phys_free 7ffab510 (detail=0x7ffab4e0) PCI: map device bdf=00:04.0 bar 2, addr 0000c068, size 00000004 [io] phys_free 7ffab390 (detail=0x7ffab360) PCI: map device bdf=00:03.0 bar 6, addr feb80000, size 00040000 [mem] phys_free 7ffab450 (detail=0x7ffab420) PCI: map device bdf=00:01.0 bar 6, addr febc0000, size 00010000 [mem] phys_free 7ffab6f0 (detail=0x7ffab6c0) PCI: map device bdf=00:01.0 bar 2, addr febd0000, size 00001000 [mem] phys_free 7ffab750 (detail=0x7ffab720) PCI: map device bdf=00:02.0 bar 1, addr febd1000, size 00001000 [mem] phys_free 7ffab690 (detail=0x7ffab660) PCI: map device bdf=00:03.0 bar 1, addr febd2000, size 00001000 [mem] phys_free 7ffab570 (detail=0x7ffab540) PCI: map device bdf=00:04.0 bar 1, addr febd3000, size 00001000 [mem] phys_free 7ffab3f0 (detail=0x7ffab3c0) PCI: map device bdf=00:1f.2 bar 5, addr febd4000, size 00001000 [mem] phys_free 7ffab270 (detail=0x7ffab240) PCI: map device bdf=00:01.0 bar 0, addr c0000000, size 20000000 [prefmem] phys_free 7ffab7b0 (detail=0x7ffab780) PCI: map device bdf=00:02.0 bar 4, addr e0000000, size 00004000 [prefmem] phys_free 7ffab5d0 (detail=0x7ffab5a0) PCI: map device bdf=00:03.0 bar 4, addr e0004000, size 00004000 [prefmem] phys_free 7ffab4b0 (detail=0x7ffab480) PCI: map device bdf=00:04.0 bar 4, addr e0008000, size 00004000 [prefmem] phys_free 7ffab330 (detail=0x7ffab300) PCI: init bdf=00:00.0 id=8086:29c0 PCI: init bdf=00:01.0 id=1234:1111 PCI: init bdf=00:02.0 id=1af4:1048 PCI: init bdf=00:03.0 id=1af4:1041 PCI: init bdf=00:04.0 id=1af4:1052 PCI: init bdf=00:1f.0 id=8086:2918 Q35 LPC init: elcr=00 0c Add to e820 map: fed1c000 00004000 2 Using pmtimer, ioport 0x608 PCI: init bdf=00:1f.2 id=8086:2922 PCI: init bdf=00:1f.3 id=8086:2930 phys_free 7ffab810 (detail=0x7ffab7e0) PCI: Using 00:01.0 for primary VGA init smm init mtrr handle_smp: apic_id=0x1 Found 2 cpu(s) max supported 2 cpu(s) init PIR table phys_alloc zone=0x7ffbfe9c size=128 align=10 ret=f5a60 (detail=0x7ffab810) Copying PIR from 0x7ffbfc80 to 0x000f5a60 init MPTable phys_alloc zone=0x7ffbfe94 size=32768 align=10 ret=7ffa3810 (detail=0x7ffa37e0) phys_alloc zone=0x7ffbfe9c size=240 align=10 ret=f5970 (detail=0x7ffa37b0) Copying MPTABLE from 0x00006e4c/7ffa3810 to 0x000f5970 phys_free 7ffa3810 (detail=0x7ffa37e0) phys_alloc zone=0x7ffbfe94 size=308 align=10 ret=7ffab6d0 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe9c size=379 align=10 ret=f57f0 (detail=0x7ffab670) phys_free 7ffab6d0 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe9c size=31 align=10 ret=f57d0 (detail=0x7ffab7e0) Copying SMBIOS entry point from 0x00006e4c to 0x000f57d0 load ACPI tables phys_alloc zone=0x7ffbfe94 size=4097 align=10 ret=7ffaa660 (detail=0x7ffab7b0) Copying romfile 'etc/table-loader' (len 4096) phys_alloc zone=0x7ffbfe94 size=260 align=10 ret=7ffab6a0 (detail=0x7ffaa630) phys_alloc zone=0x7ffbfe9c size=36 align=10 ret=f57a0 (detail=0x7ffaa600) phys_alloc zone=0x7ffbfea0 size=131072 align=40 ret=7ffe0000 (detail=0x7ffaa5d0) phys_free 7ffab6a0 (detail=0x7ffaa630) phys_free 7ffaa660 (detail=0x7ffab7b0) init timer Scan for VGA option rom Attempting to init PCI bdf 00:01.0 (vd 1234:1111) Attempting to map option rom on dev 00:01.0 Option rom sizing returned febc0000 ffff0000 Inspecting possible rom at 0xfebc0000 (vd=1234:1111 bdf=00:01.0) WARNING! Found unaligned PCI rom (vd=1234:1111) Copying option rom (size 41472) from 0xfebc0000 to 0x000c0000 Checking rom 0x000c0000 (sig aa55 size 81) Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.10.1-20170402_032207-jb2) init usb init ps2port phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa9000 (detail=0x7ffab7b0) /7ffa9000\ Start thread |7ffa9000| i8042_flush |7ffa9000| i8042_command cmd=1aa |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_read |7ffa9000| i8042 param=55 |7ffa9000| i8042_command cmd=1ab |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_read |7ffa9000| i8042 param=0 |7ffa9000| ps2_command aux=0 cmd=1ff |7ffa9000| i8042 ctr old=30 new=30 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write init floppy drives init hard drives init ahci phys_alloc zone=0x7ffbfea4 size=2048 align=10 ret=ea2e0 (detail=0x7ffab780) phys_alloc zone=0x7ffbfe9c size=20 align=10 ret=f5780 (detail=0x7ffab750) AHCI controller at 00:1f.2, iobase 0xfebd4000, irq 10 AHCI: cap 0x40141f05, ports_impl 0x3f phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffab700 (detail=0x7ffab6d0) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffab000 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab500 (detail=0x7ffab640) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab400 (detail=0x7ffab610) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa8000 (detail=0x7ffaafd0) /7ffa8000\ Start thread |7ffa8000| AHCI/0: probing |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=ff |7ffa9000| i8042_kbd_write c=255 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| ps2 read aa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_command aux=0 cmd=f5 |7ffa9000| i8042 ctr old=30 new=30 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaaf80 (detail=0x7ffaaf50) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffaa800 (detail=0x7ffaaf20) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaae00 (detail=0x7ffaadd0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaac00 (detail=0x7ffaada0) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa7000 (detail=0x7ffaad70) /7ffa7000\ Start thread |7ffa7000| AHCI/1: probing |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=f5 |7ffa9000| i8042_kbd_write c=245 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_command aux=0 cmd=10f0 |7ffa9000| i8042 ctr old=30 new=30 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaad20 (detail=0x7ffaa7d0) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffaa000 (detail=0x7ffaa7a0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaa400 (detail=0x7ffaa770) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffa6f00 (detail=0x7ffaa740) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa5000 (detail=0x7ffaa710) /7ffa5000\ Start thread |7ffa5000| AHCI/2: probing |7ffa8000| AHCI/0: link down |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=f0 |7ffa9000| i8042_kbd_write c=240 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| ps2_sendbyte aux=0 cmd=2 |7ffa9000| i8042_kbd_write c=2 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_command aux=0 cmd=f4 |7ffa9000| i8042 ctr old=61 new=70 |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaa6c0 (detail=0x7ffaa690) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffa6800 (detail=0x7ffaa660) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffa6e00 (detail=0x7ffaa630) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffa6d00 (detail=0x7ffaa5a0) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa4000 (detail=0x7ffaa570) /7ffa4000\ Start thread |7ffa4000| AHCI/3: probing |7ffa7000| AHCI/1: link down |7ffa8000| phys_free 7ffab000 (detail=0x7ffab6a0) |7ffa8000| phys_free 7ffab500 (detail=0x7ffab640) |7ffa8000| phys_free 7ffab400 (detail=0x7ffab610) |7ffa8000| phys_free 7ffab700 (detail=0x7ffab6d0) \7ffa8000/ End thread phys_free 7ffa8000 (detail=0x7ffaafd0) |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| ps2_sendbyte aux=0 cmd=f4 |7ffa9000| i8042_kbd_write c=244 |7ffa9000| i8042_wait_write |7ffa9000| ps2 read fa |7ffa9000| i8042_command cmd=1060 |7ffa9000| i8042_wait_write |7ffa9000| i8042_wait_write |7ffa9000| PS2 keyboard initialized \7ffa9000/ End thread phys_free 7ffa9000 (detail=0x7ffab7b0) phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffab700 (detail=0x7ffab7b0) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffab000 (detail=0x7ffab6d0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab500 (detail=0x7ffab6a0) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffab400 (detail=0x7ffab640) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa9000 (detail=0x7ffab610) /7ffa9000\ Start thread |7ffa9000| AHCI/4: probing |7ffa5000| AHCI/2: link down |7ffa7000| phys_free 7ffaa800 (detail=0x7ffaaf20) |7ffa7000| phys_free 7ffaae00 (detail=0x7ffaadd0) |7ffa7000| phys_free 7ffaac00 (detail=0x7ffaada0) |7ffa7000| phys_free 7ffaaf80 (detail=0x7ffaaf50) \7ffa7000/ End thread phys_free 7ffa7000 (detail=0x7ffaad70) phys_alloc zone=0x7ffbfe94 size=68 align=10 ret=7ffaafb0 (detail=0x7ffaaf80) phys_alloc zone=0x7ffbfe94 size=1024 align=400 ret=7ffaa800 (detail=0x7ffaaf50) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaae00 (detail=0x7ffaaf20) phys_alloc zone=0x7ffbfe94 size=256 align=100 ret=7ffaac00 (detail=0x7ffaadd0) phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa8000 (detail=0x7ffaada0) /7ffa8000\ Start thread |7ffa8000| AHCI/5: probing |7ffa4000| AHCI/3: link down |7ffa5000| phys_free 7ffaa000 (detail=0x7ffaa7a0) |7ffa5000| phys_free 7ffaa400 (detail=0x7ffaa770) |7ffa5000| phys_free 7ffa6f00 (detail=0x7ffaa740) |7ffa5000| phys_free 7ffaad20 (detail=0x7ffaa7d0) \7ffa5000/ End thread phys_free 7ffa5000 (detail=0x7ffaa710) init virtio-blk init virtio-scsi phys_alloc zone=0x7ffbfe94 size=4096 align=1000 ret=7ffa7000 (detail=0x7ffaad70) /7ffa7000\ Start thread |7ffa7000| found virtio-scsi at 00:02.0 |7ffa7000| phys_alloc zone=0x7ffbfea0 size=55 align=10 ret=7ffdffc0 (detail=0x7ffaad40) |7ffa7000| pci dev 0:2 virtio cap at 0x98 type 5 [pci cfg access] |7ffa7000| pci dev 0:2 virtio cap at 0x84 type 2 bar 2 at 0x0000c060 off +0x0000 [io] |7ffa7000| pci dev 0:2 virtio cap at 0x60 type 4 bar 4 at 0xe0000000 off +0x2000 [mmio] |7ffa7000| pci dev 0:2 virtio cap at 0x50 type 3 bar 4 at 0xe0000000 off +0x1000 [mmio] |7ffa7000| pci dev 0:2 virtio cap at 0x40 type 1 bar 4 at 0xe0000000 off +0x0000 [mmio] |7ffa7000| pci dev 00:02.0 using modern (1.0) virtio mode |7ffa7000| phys_alloc zone=0x7ffbfea0 size=5408 align=1000 ret=7ffde000 (detail=0x7ffaad10) |7ffa7000| phys_alloc zone=0x7ffbfe9c size=52 align=10 ret=f5740 (detail=0x7ffaa7d0) |7ffa7000| Searching bootorder for: /pci@i0cf8/*@2/*@0/*@0,0 |7ffa9000| AHCI/4: link down |7ffa4000| phys_free 7ffa6800 (detail=0x7ffaa660) |7ffa4000| phys_free 7ffa6e00 (detail=0x7ffaa630) |7ffa4000| phys_free 7ffa6d00 (detail=0x7ffaa5a0) |7ffa4000| phys_free 7ffaa6c0 (detail=0x7ffaa690) \7ffa4000/ End thread phys_free 7ffa4000 (detail=0x7ffaa570) init lsi53c895a init esp init megasas init pvscsi init MPT init lpt Found 0 lpt ports init serial Found 0 serial ports i8042_command cmd=ae i8042_wait_write |7ffa8000| AHCI/5: link down |7ffa9000| phys_free 7ffab000 (detail=0x7ffab6d0) |7ffa9000| phys_free 7ffab500 (detail=0x7ffab6a0) |7ffa9000| phys_free 7ffab400 (detail=0x7ffab640) |7ffa9000| phys_free 7ffab700 (detail=0x7ffab7b0) \7ffa9000/ End thread phys_free 7ffa9000 (detail=0x7ffab610) |7ffa8000| phys_free 7ffaa800 (detail=0x7ffaaf50) |7ffa8000| phys_free 7ffaae00 (detail=0x7ffaaf20) |7ffa8000| phys_free 7ffaac00 (detail=0x7ffaadd0) |7ffa8000| phys_free 7ffaafb0 (detail=0x7ffaaf80) \7ffa8000/ End thread phys_free 7ffa8000 (detail=0x7ffaada0) Thanks, Jonathan Boeing

2 1

tpm: TPM 2 support
by Wim Vervoorn 07 Apr '17

07 Apr '17

Hello, I am planning to implement coreboot with SeaBIOS payload and using the Infineon 9665 TPM (in 2.0 mode). Can I assume this to work or should I expect issues with it that need to be solved? Best Regards, Wim Vervoorn

1 0

issues about keyboard in the safe mode of windows 7
by fulaiyang 31 Mar '17

31 Mar '17

I use the qemu-2.7 and seabios-1.10.1 to start the windows 7 guest. And the xhci controller is passthroughed to the guest. When the safe mode interface of the windows 7 appears, keyboard sometimes doesn't work and I can not choose any mode. I have referred to seabios code about xhci configuration and find that after initializing USB keyboard, the timer ISR will check usb event periodically. Normally, the "xhci_process_events" function can process the keyboard events, but now TRB_C bit of xhci controller has been unchanged and "xhci_process_events" function derectly return. So keyboard didn't work. I want to know why TRB_C bit of xhci controller is always unchanged. Hope somebody can help me. Sorry for my poor English. static void xhci_process_events(struct usb_xhci_s *xhci) { struct xhci_ring *evts = xhci->evts; for (;;) { /* check for event */ u32 nidx = evts->nidx; u32 cs = evts->cs; struct xhci_trb *etrb = evts->ring + nidx; u32 control = etrb->control; if ((control & TRB_C) != (cs ? 1 : 0)) return;//stop here .... ....}

1 0

[PATCH v3] config: Add function to check if fw_cfg exists
by Petr Berky 30 Mar '17

30 Mar '17

It was found qemu_get_present_cpus_count may return impossible number of cpus because of not checking if fw_cfg exists before using it. That may lead to undefined behavior of emulator, in particular Bochs that freezes. Signed-off-by: Petr Berky <petr.berky(a)email.cz> --- src/fw/paravirt.c | 12 +++++++++++- src/fw/paravirt.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 707502d..5b23d78 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -32,9 +32,16 @@ u32 RamSize; u64 RamSizeOver4G; // Type of emulator platform. int PlatformRunningOn VARFSEG; +// cfg enabled +int cfg_enabled = 0; // cfg_dma enabled int cfg_dma_enabled = 0; +inline int qemu_cfg_enabled(void) +{ + return cfg_enabled; +} + inline int qemu_cfg_dma_enabled(void) { return cfg_dma_enabled; @@ -392,7 +399,9 @@ u16 qemu_get_present_cpus_count(void) { u16 smp_count = 0; - qemu_cfg_read_entry(&smp_count, QEMU_CFG_NB_CPUS, sizeof(smp_count)); + if (qemu_cfg_enabled()) { + qemu_cfg_read_entry(&smp_count, QEMU_CFG_NB_CPUS, sizeof(smp_count)); + } u16 cmos_cpu_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1; if (smp_count < cmos_cpu_count) { smp_count = cmos_cpu_count; @@ -571,6 +580,7 @@ void qemu_cfg_init(void) return; dprintf(1, "Found QEMU fw_cfg\n"); + cfg_enabled = 1; // Detect DMA interface. u32 id; diff --git a/src/fw/paravirt.h b/src/fw/paravirt.h index 16f3d9a..a14d83e 100644 --- a/src/fw/paravirt.h +++ b/src/fw/paravirt.h @@ -49,6 +49,7 @@ static inline int runningOnKVM(void) { // QEMU_CFG_DMA ID bit #define QEMU_CFG_VERSION_DMA 2 +int qemu_cfg_enabled(void); int qemu_cfg_dma_enabled(void); void qemu_preinit(void); void qemu_platform_setup(void); -- 2.11.0

3 2

[PATCH] config: Add function to check if fw_cfg exists
by petr.berky＠email.cz 29 Mar '17

29 Mar '17

>From 405de6e571a2bf332452a17ae98f7b3a0613365e Mon Sep 17 00:00:00 2001 From: Petr Berky <petr.berky(a)email.cz> Date: Tue, 14 Mar 2017 20:30:52 +0100 Subject: [PATCH] config: Add function to check if fw_cfg exists It was found qemu_get_present_cpus_count may return impossible number of cpus because of not checking if fw_cfg exists before using it. That may lead to undefined behavior of emulator, in particular Bochs that freezes. Signed-off-by: Petr Berky <petr.berky(a)email.cz> --- src/fw/paravirt.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 707502d..b2cfc23 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -220,6 +220,21 @@ qemu_cfg_select(u16 f) outw(f, PORT_QEMU_CFG_CTL); } +static int +qemu_cfg_check_signature(void) +{ + int i; + char *sig = "QEMU"; + + qemu_cfg_select(QEMU_CFG_SIGNATURE); + for (i = 0; i < 4; i++) { + if (inb(PORT_QEMU_CFG_DATA) != sig[i]) { + return -1; + } + } + return 0; +} + static void qemu_cfg_dma_transfer(void *address, u32 length, u32 control) { @@ -392,7 +407,9 @@ u16 qemu_get_present_cpus_count(void) { u16 smp_count = 0; - qemu_cfg_read_entry(&smp_count, QEMU_CFG_NB_CPUS, sizeof(smp_count)); + if (qemu_cfg_check_signature() == 0) { + qemu_cfg_read_entry(&smp_count, QEMU_CFG_NB_CPUS, sizeof(smp_count)); + } u16 cmos_cpu_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1; if (smp_count < cmos_cpu_count) { smp_count = cmos_cpu_count; @@ -563,12 +580,9 @@ void qemu_cfg_init(void) return; // Detect fw_cfg interface. - qemu_cfg_select(QEMU_CFG_SIGNATURE); - char *sig = "QEMU"; - int i; - for (i = 0; i < 4; i++) - if (inb(PORT_QEMU_CFG_DATA) != sig[i]) - return; + if (qemu_cfg_check_signature() != 0) { + return; + } dprintf(1, "Found QEMU fw_cfg\n"); -- 2.11.0

4 6

Bootsplash
by Gert Menke 27 Mar '17

27 Mar '17

Hi, I recently installed Coreboot and SeaBIOS on my Thinkpad X230. After sorting out a little problem with suspend/resume, I am quite happy with it. Now I would like to add a bootsplash image, but SeaBIOS seems unable to find any vesa modes. However, HDT (http://www.hdt-project.org) shows several modes, including the native display resolution (1366x768x32) and the resolution of my bootsplash.bmp (1024x768x32). I am using the proprietary vesa bios blob extracted from the original X230 BIOS and it seems to work fine, except for the bootsplash. Thanks for any help, Gert

2 4

[Bochs] [PATCH RFC] shadow: Change order of PCI writes
by petr.berky＠email.cz 25 Mar '17

25 Mar '17

I am working on an issue with SeaBIOS running in Bochs emulator. I found I need to revert SeaBIOS patch d449a11, otherwise Bochs freezes. After the further investigation, I narrowed down the problem to those lines: File: src/fw/shadow.c Function: __make_bios_writable_intel 48 // Write PAM settings back to pci config space 49 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); 50 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); File: src/fw/shadow.c Function: make_bios_readonly_intel 109 // Write PAM settings back to pci config space 110 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); 111 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); What has changed, comparing to the code before patch d449a11 is the order of writes to PAM registers. Before d449a11 the order was: 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x59 After d449a11 the order is : 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f I believe also the 0x58 (DRAMT?) register is written after the patch d449a11 and was not before. I checked, and the registers values after write are exactly the same in both cases (before/after patch). This lead me to think the order of writes matters. So I prepared the patch that restores the old order. I works well and fixes the issue with Bochs. But there is still one think I cannot explain and I hope I can find some help here. If you look on the patch below, you will see I had to use different pci write functions in __make_bios_writable_intel and make_bios_readonly_intel. The only difference in those functions (I think) is the size of data that is written at one call. Still It does not work for me when written some other way. Again, I would appreciate if someone could explain it to me or point me some documentation. Just to summarize, I have two questions: 1. Why the order of pci writes makes a difference here? 2. Why the size of pci writes matters? >From 953c133a6ade49e9148a0734ffefc0fb27c116fb Mon Sep 17 00:00:00 2001 From: Petr Berky <petr.berky(a)email.cz> Date: Sun, 19 Mar 2017 10:14:49 +0100 Subject: [PATCH RFC] shadow: Change order of PCI writes This change solves the problem with Bochs freeze --- src/fw/shadow.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/fw/shadow.c b/src/fw/shadow.c index c80b266..508af20 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -23,6 +23,7 @@ union pamdata_u { u8 data8[8]; + u16 data16[4]; u32 data32[2]; }; @@ -46,8 +47,9 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) pam[0] = 0x30; // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 2, pamdata.data16[1]); pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 1, pamdata.data8[1]); if (!ram_present) // Copy bios. @@ -107,8 +109,11 @@ make_bios_readonly_intel(u16 bdf, u32 pam0) pam[0] = 0x10; // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 2, pamdata.data16[1]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data16[2]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 6, pamdata.data8[6]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 7, pamdata.data8[7]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 1, pamdata.data8[1]); } static int ShadowBDF = -1; -- 2.11.0

2 2

Re: [SeaBIOS] [PATCH 0/8] SeaVGABIOS improvments for coreboot's framebuffer v2
by Patrick Rudolph 25 Mar '17

25 Mar '17

On Fri, 24 Mar 2017 20:51:56 -0400 Kevin O'Connor <kevin(a)koconnor.net> wrote: > On Fri, Mar 24, 2017 at 05:27:19PM +0100, Patrick Rudolph wrote: > > This series add several fixes to coreboot's framebuffer > > implementation and it main purpose is to fix Microsoft's Windows as > > supported OS. > > > > The series fixes the following issues: > > * Windows shows no image in text-mode > > * Windows NTLDR/bootmgr shows no image in VESA mode > > * Windows shows no image in VESA mode > > * Windows legacy Intel VGA driver requires VBT in VGA option ROM > > * Clear screen broken due to INT 15h replaced by OS > > > > I was able to boot Windows with the following configurations: > > * using VgaSave driver in text-mode with a > > fixed display resolution of 640x480 at 4Bpp. > > * using VgaSave driver in VESA mode and > > set a display resolution up to 1600x1200 at 24Bpp. > > * using VgaSave driver in Windows's "Safe Mode" in VESA mode and > > set a display resolution up to 1600x1200 at 24Bpp. > > * using the Intel VGA driver with up to the panel native > > resolution of 1680x1050 at 24Bpp. > > > > Most likely other VESA compatible bootloaders and operating systems > > will be fixed, too. > > > > Changes since v1: > > Thanks, but I didn't see a response to my comments on patches 1 and 2 > from the last series. > Sorry, I'll will fix the issues in patches 1 and 2. > > * Add crash detection handler for INT 15h modifications. > > Can you explain how this works? If int1587 is disabled, why is it a > priority to not clear the screen? To prevent a crash on the next mode change. Windows will iterate over modes and finaly end with mode 12, which isn't a compatible VESA mode. > > > * Copy Intel VBT to VGA option ROM if provided by ASLS > > As a high level comment, I think it would be great to have further > support for Intel video in SeaVGABIOS, but I wonder if extending cbvga > is the right approach. Seems like we could make an intel-seavgabios > and it would be a better platfrom for future intel specific features > (like auto-detecting the framebuffer and maybe even switching modes). > Having a seperate vga option rom would require additional configuration overhead in coreboot. As for now autodetecting the card at runtime seems to be prefereable. I'm not planing to include any intel specific features. > Cheers, > -Kevin

1 0

[PATCH 0/8] SeaVGABIOS improvments for coreboot's framebuffer v2
by Patrick Rudolph 25 Mar '17

25 Mar '17

This series add several fixes to coreboot's framebuffer implementation and it main purpose is to fix Microsoft's Windows as supported OS. The series fixes the following issues: * Windows shows no image in text-mode * Windows NTLDR/bootmgr shows no image in VESA mode * Windows shows no image in VESA mode * Windows legacy Intel VGA driver requires VBT in VGA option ROM * Clear screen broken due to INT 15h replaced by OS I was able to boot Windows with the following configurations: * using VgaSave driver in text-mode with a fixed display resolution of 640x480 at 4Bpp. * using VgaSave driver in VESA mode and set a display resolution up to 1600x1200 at 24Bpp. * using VgaSave driver in Windows's "Safe Mode" in VESA mode and set a display resolution up to 1600x1200 at 24Bpp. * using the Intel VGA driver with up to the panel native resolution of 1680x1050 at 24Bpp. Most likely other VESA compatible bootloaders and operating systems will be fixed, too. Changes since v1: * Add crash detection handler for INT 15h modifications. * Disable VESA modes in cbvga_init * Make memcpy_high method public * Copy Intel VBT to VGA option ROM if provided by ASLS Patrick Rudolph (8): SeaVGABios/cbvga: Advertise correct pixel format SeaVGABios/cbvga: Assume VGA compatible GPU in text-mode SeaVGABIOS/vbe: Query driver for scanline pitch SeaVGABios/cbvga: Use active mode to clear screen SeaVGABios/cbvga: Advertise compatible VESA modes SeaVGABios/vgafb: Make memcpy_high public SeaVGABios/cbvga:: Add Intel VBT support SeaVGABios/cbvga: Add crash detection handler vgasrc/bochsvga.c | 5 + vgasrc/bochsvga.h | 1 + vgasrc/cbvga.c | 274 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- vgasrc/clext.c | 5 + vgasrc/stdvga.c | 5 + vgasrc/vbe.c | 2 +- vgasrc/vgaentry.S | 2 +- vgasrc/vgafb.c | 2 +- vgasrc/vgafb.h | 2 +- vgasrc/vgahw.h | 10 ++ vgasrc/vgautil.h | 3 + 11 files changed, 301 insertions(+), 10 deletions(-) -- 2.9.3

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