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[PATCH] ahci: Disable Native Command Queueing
by Zeh, Werner 23 Jun '17

23 Jun '17

The AHCI driver currently sets the NCQ bit for every command that is issued to the SATA drive. This is not needed as there is always only one command active at a time and in turn can lead to a hanging AHCI controller (true for Marvel 88SE9170). The following patch disables the usage of NCQ completely. With this patch the Marvel AHCI controller works just fine without any issues. Werner diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 2eee192..b9043b9 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -130,7 +130,6 @@ static int ahci_command(struct ahci_port_s *port_gf, int iswrite, int isatapi, intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT); if (intbits) ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits); - ahci_port_writel(ctrl, pnr, PORT_SCR_ACT, 1); ahci_port_writel(ctrl, pnr, PORT_CMD_ISSUE, 1); u32 end = timer_calc(AHCI_REQUEST_TIMEOUT);

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Re: [SeaBIOS] Seabios can only detect one disk when two disks are attached to one scsi controller
by Gerd Hoffmann 16 Jun '17

16 Jun '17

Hi, > <address type='drive' controller='0' bus='0' target='0' unit='0'/> > <address type='drive' controller='0' bus='0' target='0' unit='1'/> Fixed in master branch (added lun support), no release yet with that. For released versions you can use "target='1' unit='0'" as address, so the disk is attached as separate target not as lun. cheers, Gerd

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How to run AHCI option rom in Seabios?
by Аладышев Константин 15 Jun '17

15 Jun '17

I'm trying to enable SATA hotplug (in OS) feature on my board. And one of my attempts is to run AHCI option rom from original BIOS. I use coreboot/seabios bundle with seabios responsible for option ROM execution. And I stuck with a problem, that seabios doesn't want to run ROM on SATA controllers cause of pci->have_driver check: optionroms.c : // Find and deploy PCI roms. struct pci_device *pci; foreachpci(pci) { if (pci->class == PCI_CLASS_DISPLAY_VGA || pci->have_driver) continue; init_pcirom(pci, 0, sources); } : ata.c: :. // Handle controllers on an ATA PCI device. static void init_pciata(struct pci_device *pci, u8 prog_if) { pci->have_driver = 1; :. So, what is a proper way to run roms like AHCI on SATA controllers? (in my case SATA controller is embedded device in southbridge)

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Seabios can only detect one disk when two disks are attached to one scsi controller
by fengyd 14 Jun '17

14 Jun '17

Hi, Two disks are configured and attached to on scsi controller, but only on disk can be detected by seabios. </disk> <disk type='block' device='disk'> <driver name='qemu' type='raw' cache='none' io='native'/> <source dev='/dev/disk/by-path/ip-192.168.13.7:3260-iscsi-iqn.2010-10.org.openstack:volume-7b894c9d-fe25-4ee4-96fa-2b5947f7758f-lun-0'/> <target dev='sda' bus='scsi'/> <serial>7b894c9d-fe25-4ee4-96fa-2b5947f7758f</serial> <address type='drive' controller='0' bus='0' target='0' unit='0'/> </disk> <disk type='block' device='disk'> <driver name='qemu' type='raw' cache='none' io='native'/> <source dev='/dev/disk/by-path/ip-192.168.13.7:3260-iscsi-iqn.2010-10.org.openstack:volume-6d75e7b8-39b2-4209-9fe9-b2de953a7e01-lun-0'/> <target dev='sdb' bus='scsi'/> <serial>6d75e7b8-39b2-4209-9fe9-b2de953a7e01</serial> <address type='drive' controller='0' bus='0' target='0' unit='1'/> </disk> <controller type='usb' index='0'> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x2'/> </controller> <controller type='pci' index='0' model='pci-root'/> <controller type='scsi' index='0'> <address type='pci' domain='0x0000' bus='0x00' slot='0x08' function='0x0'/> </controller> Could you help check it? Thanks in advance. BR. Yafeng

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Re: [SeaBIOS] [PATCH] boot: boot menu up to 35 devices with letters and possible pages
by Kevin O'Connor 13 Jun '17

13 Jun '17

On Sun, Jun 11, 2017 at 12:41:22AM +0300, Ivan Ivanov wrote: > Extend boot menu: make it possible to select the boot menu entries > with ID larger than 10 by pressing a corresponding letter key. If > there are more than 18 devices, then a boot menu splits into two > pages; you can switch between the pages by pressing the ENTER key. > NOTE: now to access the TPM you need to press the M key. It makes more > sense, because Trusted is adjective while Module is noun - and adds > more convenience, because M letter is at the end of keyboard's 3rd row > of letters, not in the middle of them Thanks. Can you describe a real-world situation where one would have more than 10 boot devices and one would be using the boot menu? -Kevin

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Re: [SeaBIOS] [PATCH] hw/nvme: Enable NVMe support for non-qemu hardware
by Kevin O'Connor 13 Jun '17

13 Jun '17

On Mon, Jun 12, 2017 at 05:53:24PM -0600, Youness Alaoui wrote: > I submitted this a while back (April 25th) here : > https://review.coreboot.org/#/c/19443/ > And I was just told that it wasn't the right place for it! So I'm > sending you an updated patch to enable NVMe. > I noticed that this was already submitted on May 10th by Kevin > O'Connor (https://mail.coreboot.org/pipermail/seabios/2017-May/011356.html) > but the patch was incomplete, so I've updated mine to mention it. > Patch is inlined below for review. Thanks. I committed this. -Kevin

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[PATCH] hw/nvme: Enable NVMe support for non-qemu hardware
by Youness Alaoui 12 Jun '17

12 Jun '17

I submitted this a while back (April 25th) here : https://review.coreboot.org/#/c/19443/ And I was just told that it wasn't the right place for it! So I'm sending you an updated patch to enable NVMe. I noticed that this was already submitted on May 10th by Kevin O'Connor (https://mail.coreboot.org/pipermail/seabios/2017-May/011356.html) but the patch was incomplete, so I've updated mine to mention it. Patch is inlined below for review. Thanks! Youness. ---- >From ff8e3f40cbf5a4cc6035635ae23462505265a74a Mon Sep 17 00:00:00 2001 From: Youness Alaoui <youness.alaoui(a)puri.sm> Date: Tue, 25 Apr 2017 11:21:05 -0400 Subject: [PATCH] hw/nvme: Enable NVMe support for non-qemu hardware NVMe support was tested on purism/librem13 laptops and SeaBIOS has no problems in detecting and booting the drives. This is a continuation of commit 235a8190 which was incomplete. Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- src/hw/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hw/nvme.c b/src/hw/nvme.c index 1c2bce5..11583ad 100644 --- a/src/hw/nvme.c +++ b/src/hw/nvme.c @@ -599,7 +599,7 @@ nvme_cmd_readwrite(struct nvme_namespace *ns, struct disk_op_s *op, int write) int nvme_process_op(struct disk_op_s *op) { - if (!CONFIG_NVME || !runningOnQEMU()) + if (!CONFIG_NVME) return DISK_RET_SUCCESS; struct nvme_namespace *ns = container_of(op->drive_gf, struct nvme_namespace, -- 2.4.11

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[PATCH 0/5] SeaVGABIOS improvments for coreboot's framebuffer v3
by Patrick Rudolph 12 Jun '17

12 Jun '17

This series add several fixes to coreboot's framebuffer implementation and it main purpose is to fix Microsoft's Windows as supported OS. Tests showed that it also fixes ISOLINUX and gfxboot. The series fixes the following issues: * Windows shows no image in text-mode * Windows NTLDR/bootmgr shows no image in VESA mode * Windows shows no image in VESA mode * ISOLINUX requires VESA mode 640x480 * GFXBOOT requires 32bpp VESA modes I was able to boot Windows with the following configurations: * using VgaSave driver in text-mode with a fixed display resolution of 640x480 at 4Bpp. * using VgaSave driver in VESA mode and set a display resolution up to 1600x1200 at 24Bpp. * using VgaSave driver in Windows's "Safe Mode" in VESA mode and set a display resolution up to 1600x1200 at 24Bpp. Most likely other VESA compatible bootloaders and operating systems will be fixed, too. Changes since v2: * Disable VESA modes in cbvga_init * No Intel or Windows specific patches * Update commit message of "Assume VGA compatible GPU in text-mode" * Tested and dokumented more bootloaders Patrick Rudolph (5): SeaVGABios/cbvga: Advertise correct pixel format SeaVGABios/cbvga: Assume VGA compatible GPU in text-mode SeaVGABIOS/vbe: Query driver for scanline pitch v2 SeaVGABios/cbvga: Use active mode to clear screen SeaVGABios/cbvga: Advertise compatible VESA modes vgasrc/cbvga.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- vgasrc/stdvga.c | 5 ++ vgasrc/vbe.c | 2 +- vgasrc/vgahw.h | 6 +++ vgasrc/vgautil.h | 2 + 5 files changed, 144 insertions(+), 7 deletions(-) -- 2.9.3

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[PATCH 1/4] smm: Backup and restore A20 on an SMI based mode switch
by Kevin O'Connor 12 Jun '17

12 Jun '17

QEMU does not store the A20 setting in the SMM cpu environment area (and it does not look like real CPUs do either). So, manually backup and restore A20 on a mode switch. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/fw/smm.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/fw/smm.c b/src/fw/smm.c index 95f6ba7..178959c 100644 --- a/src/fw/smm.c +++ b/src/fw/smm.c @@ -52,7 +52,8 @@ struct smm_state { struct smm_layout { struct smm_state backup1; struct smm_state backup2; - u8 stack[0x7c00]; + u32 backup_a20; + u8 stack[0x8000 - sizeof(struct smm_state)*2 - sizeof(u32)]; u64 codeentry; u8 pad_8008[0x7df8]; struct smm_state cpu; @@ -102,10 +103,13 @@ handle_smi(u16 cs) memcpy(&smm->cpu, &smm->backup1, sizeof(smm->cpu)); memcpy(&smm->cpu.i32.eax, regs, sizeof(regs)); smm->cpu.i32.eip = regs[3]; + // Enable a20 and backup its previous state + smm->backup_a20 = set_a20(1); } else if (smm->cpu.i32.ecx == CALL32SMM_RETURNID) { dprintf(9, "smm cpu ret %x esp=%x\n", regs[3], regs[4]); memcpy(&smm->cpu, &smm->backup2, sizeof(smm->cpu)); memcpy(&smm->cpu.i32.eax, regs, sizeof(regs)); + set_a20(smm->backup_a20); smm->cpu.i32.eip = regs[3]; } } else if (rev == SMM_REV_I64) { @@ -116,9 +120,12 @@ handle_smi(u16 cs) memcpy(&smm->cpu, &smm->backup1, sizeof(smm->cpu)); memcpy(&smm->cpu.i64.rdi, regs, sizeof(regs)); smm->cpu.i64.rip = (u32)regs[4]; + // Enable a20 and backup its previous state + smm->backup_a20 = set_a20(1); } else if ((u32)smm->cpu.i64.rcx == CALL32SMM_RETURNID) { memcpy(&smm->cpu, &smm->backup2, sizeof(smm->cpu)); memcpy(&smm->cpu.i64.rdi, regs, sizeof(regs)); + set_a20(smm->backup_a20); smm->cpu.i64.rip = (u32)regs[4]; } } -- 2.9.3

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[PATCH 0/2] fix non-bootable lsi-scsi
by Roman Kagan 12 Jun '17

12 Jun '17

As reported by Maciej Józefczyk, one can't boot a QEMU vm off a storage device hanging on an lsi53c895a controller. The problem was introduced by my series adding SCSI device enumeration with REPORT_LUNS command. This series fixes the issue. Roman Kagan (2): blockcmd: start REPORT_LUNS with the smallest buffer Revert "lsi-scsi: reset in case of a serious problem" src/hw/blockcmd.c | 4 +++- src/hw/lsi-scsi.c | 2 -- 2 files changed, 3 insertions(+), 3 deletions(-) -- 2.9.4

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