SeaBIOS

seabios@seabios.org

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3801 discussions

[PATCH v2 1/4][SeaBios] Add bitmap for CPU EJ0 callback
by Vasilis Liaskovitis 24 Jan '12

24 Jan '12

Add bitmap for CPU EJ0 callback and write to it on a cpu _EJ0 callback. Remove Sleep() call. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- src/acpi-dsdt.dsl | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index 7082b65..5138c2a 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -650,9 +650,15 @@ DefinitionBlock ( Store(DerefOf(Index(CPON, Arg0)), Local0) If (Local0) { Return(0xF) } Else { Return(0x0) } } + /* CPU eject notify method */ + OperationRegion(PREJ, SystemIO, 0xaf20, 32) + Field (PREJ, ByteAcc, NoLock, Preserve) + { + PRE, 256 + } Method (CPEJ, 2, NotSerialized) { // _EJ0 method - eject callback - Sleep(200) + Store(ShiftLeft(1, Arg0), PRE) } /* CPU hotplug notify method */ -- 1.7.7.3

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[PATCH v2 0/4] acpi_piix4: Add CPU eject infrastructure for pc-1.1
by Vasilis Liaskovitis 24 Jan '12

24 Jan '12

This patch series adds support for CPU ejection callbacks in Seabios and qemu. This will be needed for proper ACPI vcpu destruction/unplug in conjunction with the vcpu lifecycle patches. v1->v2: Add pc-1.1 model with cpu acpi ejection property. Add documentation. v1 of the series also defined the eject method to handle the CPU_DEAD event in the cpu lifecycle/destruction series. That patch has been dropped from the patchset and will be sent separately as lifecycle/unplug series matures. v2 patches are based on uq/master, plus a patch from the first version of vcpu-hotplug qemu upstream series, specifically: http://patchwork.ozlabs.org/patch/136463/ Vasilis Liaskovitis (3): uq/master: Add machine model pc-1.1 uq/master: Add CPU eject handling for acpi_piix4 uq/master: Add acpi cpu interface documentation docs/specs/acpi_hotplug.txt | 49 +++++++++++++++++++++++++++++++++++++++ docs/specs/acpi_pci_hotplug.txt | 37 ----------------------------- hw/acpi_piix4.c | 20 ++++++++++++++++ hw/pc_piix.c | 16 ++++++++++++ 4 files changed, 85 insertions(+), 37 deletions(-) create mode 100644 docs/specs/acpi_hotplug.txt delete mode 100644 docs/specs/acpi_pci_hotplug.txt -- 1.7.7.3

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Re: [SeaBIOS] [PATCH 1/4] vgabios: Don't have geode code peak into stdvga mode struct.
by Nils 22 Jan '12

22 Jan '12

Hi Kevin, You wrote: >Create a wrapper (stdvga_override_crtc) so the Geode code doesn't need >to access the stdvga mode tables directly. > >Signed-off-by: Kevin O'Connor <kevin at koconnor.net> >--- > vgasrc/geodevga.c | 10 ++-------- > vgasrc/stdvga.h | 1 + > vgasrc/stdvgamodes.c | 11 +++++++++++ Patch set 1/4 - 4/4 tested on Geode GX2 Wyse S50. Works fine. Thanks, Nils.

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S3 resume is broken on QEMU
by Gleb Natapov 22 Jan '12

22 Jan '12

Hi Kevin, Commit 8b0c509e7cdb broke S3 resume on QEMU. Before this commit QEMU compiled bios with S3_RESUME_VGA_INIT enabled. After it this is no longer an option. -- Gleb.

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[PATCH 4/4] vgabios: Check that the PCI BDF passed in is valid before using.
by Kevin O'Connor 21 Jan '12

21 Jan '12

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/bochsvga.c | 9 ++++----- vgasrc/clext.c | 5 +++-- vgasrc/geodevga.c | 3 +++ vgasrc/vgabios.c | 11 +++++++++-- vgasrc/vgabios.h | 2 +- 5 files changed, 20 insertions(+), 10 deletions(-) diff --git a/vgasrc/bochsvga.c b/vgasrc/bochsvga.c index 82629b9..cbd0b41 100644 --- a/vgasrc/bochsvga.c +++ b/vgasrc/bochsvga.c @@ -123,12 +123,11 @@ bochsvga_init(void) dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5); - u32 lfb_addr; - if (CONFIG_VGA_PCI) - lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0) + u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS; + int bdf = GET_GLOBAL(VgaBDF); + if (CONFIG_VGA_PCI && bdf >= 0) + lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0) & PCI_BASE_ADDRESS_MEM_MASK); - else - lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS; SET_VGA(VBE_framebuffer, lfb_addr); u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K); diff --git a/vgasrc/clext.c b/vgasrc/clext.c index f08294a..5468db3 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -737,8 +737,9 @@ clext_init(void) dprintf(1, "cirrus init 2\n"); u32 lfb_addr = 0; - if (CONFIG_VGA_PCI) - lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0) + int bdf = GET_GLOBAL(VgaBDF); + if (CONFIG_VGA_PCI && bdf >= 0) + lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0) & PCI_BASE_ADDRESS_MEM_MASK); SET_VGA(VBE_framebuffer, lfb_addr); u16 totalmem = cirrus_get_memsize(); diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index ce754a5..5c6caf0 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -363,6 +363,9 @@ int geodevga_init(void) stdvga_override_crtc(i, crtc); } + if (GET_GLOBAL(VgaBDF) < 0) + // Device should be at 00:01.1 + SET_VGA(VgaBDF, pci_to_bdf(0, 1, 1)); ret |= vp_setup(); ret |= dc_setup(); diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index 449f3c4..5ce7c0c 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -20,6 +20,8 @@ #include "stdvga.h" // stdvga_set_cursor_shape #include "clext.h" // clext_1012 #include "vgahw.h" // vgahw_set_mode +#include "pci.h" // pci_config_readw +#include "pci_regs.h" // PCI_VENDOR_ID // XXX #define DEBUG_VGA_POST 1 @@ -1226,14 +1228,19 @@ init_bios_area(void) SET_BDA(video_msr, 0x09); } -u16 VgaBDF VAR16; +int VgaBDF VAR16 = -1; void VISIBLE16 vga_post(struct bregs *regs) { debug_enter(regs, DEBUG_VGA_POST); - SET_VGA(VgaBDF, regs->ax); + if (CONFIG_VGA_PCI) { + u16 bdf = regs->ax; + if (pci_config_readw(bdf, PCI_VENDOR_ID) == CONFIG_VGA_VID + && pci_config_readw(bdf, PCI_DEVICE_ID) == CONFIG_VGA_DID) + SET_VGA(VgaBDF, bdf); + } int ret = vgahw_init(); if (ret) { diff --git a/vgasrc/vgabios.h b/vgasrc/vgabios.h index 403e7ce..6895a39 100644 --- a/vgasrc/vgabios.h +++ b/vgasrc/vgabios.h @@ -73,7 +73,7 @@ extern u8 vgafont14alt[]; extern u8 vgafont16alt[]; // vgabios.c -extern u16 VgaBDF; +extern int VgaBDF; #define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val)) struct carattr { u8 car, attr, use_attr; -- 1.7.6.4

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[PATCH 3/4] vgabios: Simplify planar4 vgafb code.
by Kevin O'Connor 21 Jan '12

21 Jan '12

Don't bother programming the vga registers to manipulate the framebuffer when in planar4 mode. Instead, just switch between the four planes and do the manipulation with regular reads and writes. This makes the code simpler to understand (the vga hardware manipulations are arcane and complex). Note, this could make text scrolling in planar4 mode slower and more likely to result in tearing. However, it's unlikely anything important uses the vgabios in planar4 mode. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/stdvga.c | 14 ++++++++ vgasrc/stdvga.h | 1 + vgasrc/vgafb.c | 93 ++++++++++++++++++++++++++----------------------------- 3 files changed, 59 insertions(+), 49 deletions(-) diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index d1841bf..0fab905 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -159,6 +159,20 @@ stdvga_set_text_block_specifier(u8 spec) stdvga_sequ_write(0x03, spec); } +// Enable reads and writes to the given "plane" when in planar4 mode. +void +stdvga_planar4_plane(int plane) +{ + if (plane < 0) { + // Return to default mode (read plane0, write all planes) + stdvga_sequ_write(0x02, 0x0f); + stdvga_grdc_write(0x04, 0); + } else { + stdvga_sequ_write(0x02, 1<<plane); + stdvga_grdc_write(0x04, plane); + } +} + /**************************************************************** * Font loading diff --git a/vgasrc/stdvga.h b/vgasrc/stdvga.h index c19b21f..ee14358 100644 --- a/vgasrc/stdvga.h +++ b/vgasrc/stdvga.h @@ -124,6 +124,7 @@ void stdvga_save_dac_state(u16 seg, struct saveDACcolors *info); void stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info); void stdvga_perform_gray_scale_summing(u16 start, u16 count); void stdvga_set_text_block_specifier(u8 spec); +void stdvga_planar4_plane(int plane); void stdvga_load_font(u16 seg, void *src_far, u16 count , u16 start, u8 destflags, u8 fontsize); u16 stdvga_get_crtc(void); diff --git a/vgasrc/vgafb.c b/vgasrc/vgafb.c index b6daba6..71a5719 100644 --- a/vgasrc/vgafb.c +++ b/vgasrc/vgafb.c @@ -8,7 +8,7 @@ #include "biosvar.h" // GET_BDA #include "util.h" // memset_far #include "vgahw.h" // vgahw_find_mode -#include "stdvga.h" // stdvga_grdc_write +#include "stdvga.h" // stdvga_planar4_plane /**************************************************************** @@ -55,19 +55,22 @@ scroll_pl4(struct vgamode_s *vmode_g, int nblines, int attr src_far = dest_far - nblines * cheight * stride; stride = -stride; } + if (attr < 0) + attr = 0; int cols = lr.x - ul.x + 1; int rows = lr.y - ul.y + 1; - if (nblines < rows) { - stdvga_grdc_write(0x05, 0x01); - dest_far = memcpy_stride(SEG_GRAPH, dest_far, src_far, cols * cwidth + int i; + for (i=0; i<4; i++) { + stdvga_planar4_plane(i); + void *dest = dest_far; + if (nblines < rows) + dest = memcpy_stride(SEG_GRAPH, dest, src_far, cols * cwidth , stride, (rows - nblines) * cheight); + u8 pixels = (attr & (1<<i)) ? 0xff : 0x00; + memset_stride(SEG_GRAPH, dest, pixels, cols * cwidth + , stride, nblines * cheight); } - if (attr < 0) - attr = 0; - stdvga_grdc_write(0x05, 0x02); - memset_stride(SEG_GRAPH, dest_far, attr, cols * cwidth - , stride, nblines * cheight); - stdvga_grdc_write(0x05, 0x00); + stdvga_planar4_plane(-1); } static void @@ -88,6 +91,8 @@ scroll_cga(struct vgamode_s *vmode_g, int nblines, int attr src_far = dest_far - nblines * cheight * stride; stride = -stride; } + if (attr < 0) + attr = 0; int cols = lr.x - ul.x + 1; int rows = lr.y - ul.y + 1; if (nblines < rows) { @@ -96,8 +101,6 @@ scroll_cga(struct vgamode_s *vmode_g, int nblines, int attr dest_far = memcpy_stride(SEG_CTEXT, dest_far, src_far, cols * cwidth , stride, (rows - nblines) * cheight); } - if (attr < 0) - attr = 0; memset_stride(SEG_CTEXT, dest_far + 0x2000, attr, cols * cwidth , stride, nblines * cheight); memset_stride(SEG_CTEXT, dest_far, attr, cols * cwidth @@ -122,13 +125,13 @@ scroll_lin(struct vgamode_s *vmode_g, int nblines, int attr src_far = dest_far - nblines * cheight * stride; stride = -stride; } + if (attr < 0) + attr = 0; int cols = lr.x - ul.x + 1; int rows = lr.y - ul.y + 1; if (nblines < rows) dest_far = memcpy_stride(SEG_GRAPH, dest_far, src_far, cols * cwidth , stride, (rows - nblines) * cheight); - if (attr < 0) - attr = 0; memset_stride(SEG_GRAPH, dest_far, attr, cols * cwidth , stride, nblines * cheight); } @@ -151,15 +154,15 @@ scroll_text(struct vgamode_s *vmode_g, int nblines, int attr src_far = dest_far - nblines * cheight * stride; stride = -stride; } + if (attr < 0) + attr = 0x07; + attr = (attr << 8) | ' '; int cols = lr.x - ul.x + 1; int rows = lr.y - ul.y + 1; u16 seg = GET_GLOBAL(vmode_g->sstart); if (nblines < rows) dest_far = memcpy_stride(seg, dest_far, src_far, cols * cwidth , stride, (rows - nblines) * cheight); - if (attr < 0) - attr = 0x07; - attr = (attr << 8) | ' '; memset16_stride(seg, dest_far, attr, cols * cwidth , stride, nblines * cheight); } @@ -217,29 +220,20 @@ write_gfx_char_pl4(struct vgamode_s *vmode_g } u16 addr = cp.x + cp.y * cheight * nbcols; u16 src = ca.car * cheight; - stdvga_sequ_write(0x02, 0x0f); - stdvga_grdc_write(0x05, 0x02); - if (ca.attr & 0x80) - stdvga_grdc_write(0x03, 0x18); - else - stdvga_grdc_write(0x03, 0x00); - u8 i; - for (i = 0; i < cheight; i++) { - u8 *dest_far = (void*)(addr + i * nbcols); - u8 j; - for (j = 0; j < 8; j++) { - u8 mask = 0x80 >> j; - stdvga_grdc_write(0x08, mask); - GET_FARVAR(SEG_GRAPH, *(volatile u8*)dest_far); - if (GET_GLOBAL(fdata_g[src + i]) & mask) - SET_FARVAR(SEG_GRAPH, *dest_far, ca.attr & 0x0f); - else - SET_FARVAR(SEG_GRAPH, *dest_far, 0x00); + int i; + for (i=0; i<4; i++) { + stdvga_planar4_plane(i); + u8 colors = ((ca.attr & (1<<i)) ? 0xff : 0x00); + int j; + for (j = 0; j < cheight; j++) { + u8 *dest_far = (void*)(addr + j * nbcols); + u8 pixels = colors & GET_GLOBAL(fdata_g[src + j]); + if (ca.attr & 0x80) + pixels ^= GET_FARVAR(SEG_GRAPH, *dest_far); + SET_FARVAR(SEG_GRAPH, *dest_far, pixels); } } - stdvga_grdc_write(0x08, 0xff); - stdvga_grdc_write(0x05, 0x00); - stdvga_grdc_write(0x03, 0x00); + stdvga_planar4_plane(-1); } static void @@ -407,20 +401,20 @@ vgafb_write_pixel(u8 color, u16 x, u16 y) if (!vmode_g) return; - u8 *addr_far, mask, attr, data; + u8 *addr_far, mask, attr, data, i; switch (GET_GLOBAL(vmode_g->memmodel)) { case MM_PLANAR: addr_far = (void*)(x / 8 + y * GET_BDA(video_cols)); mask = 0x80 >> (x & 0x07); - stdvga_grdc_write(0x08, mask); - stdvga_grdc_write(0x05, 0x02); - GET_FARVAR(SEG_GRAPH, *(volatile u8*)addr_far); - if (color & 0x80) - stdvga_grdc_write(0x03, 0x18); - SET_FARVAR(SEG_GRAPH, *addr_far, color); - stdvga_grdc_write(0x08, 0xff); - stdvga_grdc_write(0x05, 0x00); - stdvga_grdc_write(0x03, 0x00); + for (i=0; i<4; i++) { + stdvga_planar4_plane(i); + u8 colors = (color & (1<<i)) ? 0xff : 0x00; + u8 orig = GET_FARVAR(SEG_GRAPH, *addr_far); + if (color & 0x80) + colors ^= orig; + SET_FARVAR(SEG_GRAPH, *addr_far, (colors & mask) | (orig & ~mask)); + } + stdvga_planar4_plane(-1); break; case MM_CGA: if (GET_GLOBAL(vmode_g->depth) == 2) @@ -470,11 +464,12 @@ vgafb_read_pixel(u16 x, u16 y) mask = 0x80 >> (x & 0x07); attr = 0x00; for (i = 0; i < 4; i++) { - stdvga_grdc_write(0x04, i); + stdvga_planar4_plane(i); data = GET_FARVAR(SEG_GRAPH, *addr_far) & mask; if (data > 0) attr |= (0x01 << i); } + stdvga_planar4_plane(-1); break; case MM_CGA: addr_far = (void*)((x >> 2) + (y >> 1) * 80); -- 1.7.6.4

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[PATCH 2/4] vgabios: Use regular pci_config_readl func in geode code.
by Kevin O'Connor 21 Jan '12

21 Jan '12

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/geodevga.c | 13 ++++++------- vgasrc/geodevga.h | 6 ------ 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index d326eda..ce754a5 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -7,12 +7,13 @@ // This file may be distributed under the terms of the GNU LGPLv3 license. #include "geodevga.h" // geodevga_init -#include "ioport.h" // outb #include "farptr.h" // SET_FARVAR #include "biosvar.h" // GET_BDA #include "vgabios.h" // VGAREG_* #include "util.h" // memset #include "stdvga.h" // stdvga_crtc_write +#include "pci.h" // pci_config_readl +#include "pci_regs.h" // PCI_BASE_ADDRESS_0 /**************************************************************** @@ -226,8 +227,7 @@ static int dc_setup(void) /* read fb-bar from pci, then point dc to the fb base */ dc_fb = dc_read(seg,DC_GLIU0_MEM_OFFSET); - outl(GEODE_PCI_FB,PORT_PCI_CMD); - fb = inl(PORT_PCI_DATA); + fb = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0); if (fb!=dc_fb) { dc_write(seg,DC_GLIU0_MEM_OFFSET,fb); } @@ -254,13 +254,12 @@ int vp_setup(void) dprintf(2,"VP_SETUP\n"); /* set output to crt and RGB/YUV */ if (CONFIG_VGA_GEODEGX2) - geode_msrWrite(VP_MSR_CONFIG_GX2,~0 ,~0xf8,0,0); + geode_msrWrite(VP_MSR_CONFIG_GX2, ~0, ~0xf8, 0, 0); else - geode_msrWrite(VP_MSR_CONFIG_LX,~0 ,~0xf8,0,0); + geode_msrWrite(VP_MSR_CONFIG_LX, ~0, ~0xf8, 0, 0); /* get vp register base from pci */ - outl(GEODE_PCI_VP,PORT_PCI_CMD); - vp = inl(PORT_PCI_DATA); + vp = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3); /* Set mmio registers * there may be some timing issues here, the reads seem diff --git a/vgasrc/geodevga.h b/vgasrc/geodevga.h index ec019a4..fd7ce43 100644 --- a/vgasrc/geodevga.h +++ b/vgasrc/geodevga.h @@ -26,12 +26,6 @@ #define OEM_BAR2 0x58 #define OEM_BAR3 0x5C -#define GEODE_PCI_ADDR 0x80000900 -#define GEODE_PCI_CMD (GEODE_PCI_ADDR + 0x04) -#define GEODE_PCI_FB (GEODE_PCI_ADDR + 0x10) -#define GEODE_PCI_DC (GEODE_PCI_ADDR + 0x18) -#define GEODE_PCI_VP (GEODE_PCI_ADDR + 0x1c) - #define DC_LOCK_LOCK 0x00000000 #define DC_LOCK_UNLOCK 0x00004758 -- 1.7.6.4

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[PATCH 1/4] vgabios: Don't have geode code peak into stdvga mode struct.
by Kevin O'Connor 21 Jan '12

21 Jan '12

Create a wrapper (stdvga_override_crtc) so the Geode code doesn't need to access the stdvga mode tables directly. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/geodevga.c | 10 ++-------- vgasrc/stdvga.h | 1 + vgasrc/stdvgamodes.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index 3da1b7c..d326eda 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -360,14 +360,8 @@ int geodevga_init(void) int i; for (i=0; i<ARRAY_SIZE(new_crtc); i++) { u8 *crtc = GET_GLOBAL(new_crtc[i]); - if (!crtc) - continue; - struct vgamode_s *vmode_g = stdvga_find_mode(i); - if (!vmode_g) - continue; - struct stdvga_mode_s *stdmode_g = container_of( - vmode_g, struct stdvga_mode_s, info); - SET_VGA(stdmode_g->crtc_regs, crtc); + if (crtc) + stdvga_override_crtc(i, crtc); } ret |= vp_setup(); diff --git a/vgasrc/stdvga.h b/vgasrc/stdvga.h index 9372127..c19b21f 100644 --- a/vgasrc/stdvga.h +++ b/vgasrc/stdvga.h @@ -85,6 +85,7 @@ struct saveDACcolors { // stdvgamodes.c struct vgamode_s *stdvga_find_mode(int mode); void stdvga_build_video_param(void); +void stdvga_override_crtc(int mode, u8 *crtc); // stdvgaio.c u8 stdvga_pelmask_read(void); diff --git a/vgasrc/stdvgamodes.c b/vgasrc/stdvgamodes.c index 94e273f..08c3a58 100644 --- a/vgasrc/stdvgamodes.c +++ b/vgasrc/stdvgamodes.c @@ -360,3 +360,14 @@ stdvga_build_video_param(void) , ARRAY_SIZE(vparam_g->grdc_regs)); } } + +void +stdvga_override_crtc(int mode, u8 *crtc) +{ + struct vgamode_s *vmode_g = stdvga_find_mode(mode); + if (!vmode_g) + return; + struct stdvga_mode_s *stdmode_g = container_of( + vmode_g, struct stdvga_mode_s, info); + SET_VGA(stdmode_g->crtc_regs, crtc); +} -- 1.7.6.4

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Re: [SeaBIOS] Geode vga pci code
by Kevin O'Connor 21 Jan '12

21 Jan '12

On Tue, Jan 17, 2012 at 12:06:54AM +0100, Nils wrote: > Op maandag 16-01-2012 om 00:23 uur [tijdzone -0500], schreef Kevin > O'Connor: > > Oh - it was on top of the recent patches I sent to the mailing list. > OK sorry! > > Now that i used that patch set also everything compiles. > > First i used your instructions and named the vgarom: "pci100b,0030.rom" > but then the vgabios is not run. (See attachment v475.log) Make sure you have CONFIG_VGA_BRIDGE_SETUP set in coreboot. Otherwise, I don't understand why it wouldn't run. (Your logs seem to indicate that optionroms.c:is_pci_vga() is failing - which I think would only happen if CONFIG_VGA_BRIDGE_SETUP isn't set.) > Second i used vgaroms/vgabios.bin as the vgabios name. > The vgabios gets run but i get no display output and SeaBIOS reboots > over and over. (see attachment v475-2.log) Yeah - it will break if it gets run via "vgaroms/" - I'll change the vgabios code to check for this. > This could have to do with vga region setup. > I wil investigate in the next day's (when i find time) how to initialize > MSR's to get pci access set up. > > Should the E820 table also reflect the vga range? > (I have no clue how to fix that) The e820 shouldn't have anything to do with this. -Kevin

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Error booting from USB Storage Device in QEMU-KVM GIT MASTER
by Dyweni - Qemu-Devel 20 Jan '12

20 Jan '12

Hi, I am unable to boot KVM using a usb flash drive. I'm using QEMU-KVM built from GIT MASTER as of this morning. Here's my QEMU-KVM startup options: qemu-system-x86_64 \ -curses \ -m 512 \ -snapshot \ -device piix3-usb-uhci \ -drive id=usbflash,file=flash.img,if=none,boot=on,cache=writeback \ -device usb-storage,drive=usbflash \ -net nic,macaddr=$(getmacpublic),vlan=0 -net tap,vlan=0,ifname=$publictap,script=no \ -net nic,macaddr=$(getmacprivate),vlan=1 -net tap,vlan=1,ifname=$privatetap,script=no \ $* Here's the debugging output from SeaBIOS. (Notice the 'Unable to configure USB MSC device.' message): + qemu-system-x86_64 -m 512 -snapshot -device piix3-usb-uhci -drive id=usbflash,file=flash.img,if=none,boot=on,cache=writeback -device usb-storage,drive=usbflash -net nic,macaddr=00:AA:00:AA:62:AA,vlan=0 -net tap,vlan=0,ifname=tap0,script=no -net nic,macaddr=00:AA:00:D2:D1:BB,vlan=1 -net tap,vlan=1,ifname=tap1,script=no -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios qemu-kvm: boot=on|off is deprecated and will be ignored. Future versions will reject this parameter. Please update your scripts. Start bios (version 1.6.3) Ram Size=0x20000000 (0x0000000000000000 high) Relocating init from 0x000e3b20 to 0x1ffe12e0 (size 60412) CPU Mhz=3601 === PCI bus & bridge init === PCI: pci_bios_init_bus_rec bus = 0x0 === PCI device probing === Found 8 PCI devices (max PCI bus is 00) === PCI new allocation pass #1 === PCI: check devices bus 0 === PCI new allocation pass #2 === PCI: init bases bus 0 (primary) type io max 100 sum 230 base c000 size 100: 2 bar(s), c000 -> c1ff size 20: 1 bar(s), c200 -> c21f size 10: 1 bar(s), c220 -> c22f type mem max 10000 sum 33000 base febc0000 size 10000: 3 bar(s), febc0000 -> febeffff size 1000: 3 bar(s), febf0000 -> febf2fff type prefmem max 2000000 sum 2000000 base fc000000 size 2000000: 1 bar(s), fc000000 -> fdffffff PCI: map device bus 0, bfd 0x0 PCI: map device bus 0, bfd 0x8 PCI: map device bus 0, bfd 0x9 bar 4, addr c220, size 10 [io] PCI: map device bus 0, bfd 0xb PCI: map device bus 0, bfd 0x10 bar 0, addr fc000000, size 2000000 [mem] bar 1, addr febf0000, size 1000 [mem] bar 6, addr febc0000, size 10000 [mem] PCI: map device bus 0, bfd 0x18 bar 0, addr c000, size 100 [io] bar 1, addr febf1000, size 100 [mem] bar 6, addr febd0000, size 10000 [mem] PCI: map device bus 0, bfd 0x20 bar 0, addr c100, size 100 [io] bar 1, addr febf2000, size 100 [mem] bar 6, addr febe0000, size 10000 [mem] PCI: map device bus 0, bfd 0x28 bar 4, addr c200, size 20 [io] PCI: bus=0 devfn=0x00: vendor_id=0x8086 device_id=0x1237 PCI: bus=0 devfn=0x08: vendor_id=0x8086 device_id=0x7000 PCI: bus=0 devfn=0x09: vendor_id=0x8086 device_id=0x7010 PCI: bus=0 devfn=0x0b: vendor_id=0x8086 device_id=0x7113 PCI: bus=0 devfn=0x10: vendor_id=0x1013 device_id=0x00b8 PCI: bus=0 devfn=0x18: vendor_id=0x10ec device_id=0x8139 PCI: bus=0 devfn=0x20: vendor_id=0x10ec device_id=0x8139 PCI: bus=0 devfn=0x28: vendor_id=0x8086 device_id=0x7020 PIIX3/PIIX4 init: elcr=00 0c Found 1 cpu(s) max supported 1 cpu(s) MP table addr=0x000fd620 MPC table addr=0x000fd630 size=240 SMBIOS ptr=0x000fd600 table=0x000fd4f0 size=263 ACPI tables: RSDP=0x000fd4c0 RSDT=0x1fffd7b0 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.6.3) UHCI init on dev 00:05.0 (io=c200) Found 1 lpt ports Found 1 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 ebda moved from 9fc00 to 9f800 USB MSC vendor='QEMU' product='QEMU HARDDISK' rev='1.0.' type=0 removable=0 Unable to configure USB MSC device. PS2 keyboard initialized All threads complete. Scan for option roms Running option rom at c900:0003 pmm call arg1=1 pmm call arg1=0 pmm call arg1=1 pmm call arg1=0 Running option rom at ca00:0003 pmm call arg1=1 pmm call arg1=1 Searching bootorder for: /pci@i0cf8/*@3 Searching bootorder for: /pci@i0cf8/*@4 Searching bootorder for: /rom(a)genroms/vapic.bin Running option rom at cb00:0003 ebda moved from 9f800 to 9f000 Returned 53248 bytes of ZoneHigh e820 map has 7 items: 0: 0000000000000000 - 000000000009f000 = 1 RAM 1: 000000000009f000 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000001fffd000 = 1 RAM 4: 000000001fffd000 - 0000000020000000 = 2 RESERVED 5: 00000000feffc000 - 00000000ff000000 = 2 RESERVED 6: 00000000fffc0000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... Device reports MEDIUM NOT PRESENT atapi_is_ready returned -1 Boot failed: Could not read from CDROM (code 0003) enter handle_18: NULL Booting from ROM... Booting from c900:0372 enter handle_18: NULL Booting from ROM... Booting from ca00:0372 In resume (status=0) In 32bit resume Attempting a hard reboot -- Thanks, Dyweni

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