SeaBIOS

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3801 discussions

Re: [SeaBIOS] [coreboot] One ROM for multiple devices
by Peter Stuge 13 Jun '12

13 Jun '12

Steve Goodrich wrote: > I would like to see is some mechanism in both coreboot and SeaBIOS > that would allow a given ROM to be used for multiple devices. .. > Since this problem exists in both codebases, is it reasonable to > come up with a solution that will work in both codebases? I think this should happen in CBFS. The proposal is basically a special case symlink. It would be nice to have generic symlinks instead. Another special case solution yet still CBFS-centered could be to search for wildcard option ROMs at runtime. (V and D below are hexits, while x is a literal x.) 1. pciVVVV,DDDD.rom 2. pciVVVV,DDDx.rom 3. pciVVVV,DDxx.rom 4. pciVVVV,Dxxx.rom 5. pciVVVV,xxxx.rom 6. pciVVVx,xxxx.rom 7. pciVVxx,xxxx.rom 8. pciVxxx,xxxx.rom 9. pcixxxx,xxxx.rom 6 through 9 may be debatable, but I'm not neccessarily against them! //Peter

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Re: [SeaBIOS] [coreboot] One ROM for multiple devices
by Kevin O'Connor 13 Jun '12

13 Jun '12

On Tue, Jun 12, 2012 at 05:06:11PM -0600, Steve Goodrich wrote: > Please be aware that this is cross-posted to both the SeaBIOS and coreboot > mailing lists. I know this is generally frowned upon, but I believe the > subject is valid for discussion in both forums. > > > I have a coreboot/SeaBIOS image containing an option ROM that works for > multiple graphics devices (seven or eight of them). These graphics devices > come from the same vendor but each device has its own (unique) PCI Device > ID. If I'm going to load the driver from SeaBIOS, I need to have a copy of > the option ROM file, each with the name of the target PCI device (e.g. > "pci1234,5678.rom"). Having seven or eight copies in the BIOS image file is > a waste of space. For the SeaBIOS case, is there any reason you can't simply place the rom in a cbfs file "vgaroms/myrom.rom"? -Kevin

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Re: [SeaBIOS] [coreboot] AMD Persimmon VGA Option ROM
by Wolfgang Kamp - datakamp 12 Jun '12

12 Jun '12

Hi, now I have debugged the seabios pci probing. The things happen in pci.c. The pci_next function probes all possible Bus:Device:Function combinations in the right manner. The behavior is that the bdf 00:01:0 returns 0xffff as vendor id. So the device is really not present at this time. But coreboot earlier has enumerated these device correctly. How could it be that the graphics unit of the AMD G-series APU T40E is hidden from the pci bus? The device is only present to seabios when coreboot executes the VGA ROM bios. Wolfgang -----Ursprüngliche Nachricht----- Von: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] Im Auftrag von Kevin O'Connor Gesendet: Dienstag, 12. Juni 2012 03:35 An: Stefan Reinauer Cc: coreboot(a)coreboot.org Betreff: Re: [coreboot] VGA Option ROM On Sat, Jun 09, 2012 at 02:21:50PM -0700, Stefan Reinauer wrote: > On 6/9/12 6:43 AM, Kevin O'Connor wrote: > >On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote: > >>I wonder if we need another option :-( to configure the rom but not run it? > >Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but > >CONFIG_VGA_ROM_RUN is not? > > > >-Kevin > > > CONFIG_VGA_BRIDGE_SETUP routes VGA legacy IO through the (PCI) > bridge with the VGA card attached. It does not influence option rom > handling. Right. Wolfgang is reporting that his VGA card isn't mapped at all if he doesn't select CONFIG_VGA_ROM_RUN (it doesn't show up as a PCI device at all). It should get mapped even if CONFIG_VGA_ROM_RUN isn't set. -Kevin -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [SeaBIOS] freedos images
by Kevin O'Connor 12 Jun '12

12 Jun '12

On Mon, Jun 11, 2012 at 02:59:30PM -0700, ron minnich wrote: > I'm trying to find a freedos usb image I can boot on seabios. > > I am trying these: http://derek.chezmarcotte.ca/?p=188 but I am > finding the usb keyboard performance is really terrible, for some > reason. Anyone have pointers to something that works really well? If I recall correctly, what I did was create a 20Meg harddisk image with qemu-img, then install freedos onto the harddrive image, and then dd the image to the USB stick. -Kevin

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freedos images
by ron minnich 11 Jun '12

11 Jun '12

I'm trying to find a freedos usb image I can boot on seabios. I am trying these: http://derek.chezmarcotte.ca/?p=188 but I am finding the usb keyboard performance is really terrible, for some reason. Anyone have pointers to something that works really well? thanks ron

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Re: [SeaBIOS] [coreboot] VGA Option ROM
by Kevin O'Connor 10 Jun '12

10 Jun '12

On Sat, Jun 09, 2012 at 09:17:34PM +0200, Wolfgang Kamp - datakamp wrote: > Hi, > > When execution of VGA option ROM is configured in seabios, > seabios first scans all PCI devices and looks for a vga type device as you can see in my attached log. > If seabios finds a pci vga device then it looks for a suitable VGA BIOS (Vendor id:Device id / 1002:9804) in CBFS. > But if seabios does not find a vga device, it doesn't look for the VGA BIOS. That is what happens. > In my issue seabios can only find the pci VGA device if I first enabled VGA ROM execution in coreboot. > If seabios finds the vga device it will also find the correct VGA BIOS in CBFS and executes it. > The log shows this. The issue is that the pci enumertion fails in seabios and it does not list all available devices. > Why is it broken? It could be a coreboot or seabios problem. Looks like a coreboot issue to me. The PCI device does not appear to be present when SeaBIOS doesn't find it. As Ron indicated in another email, it looks like coreboot needs an option to enable the vga but not run the rom for your board. -Kevin

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[PATCH] Remove SMBIOS generation on coreboot hack.
by Kevin O'Connor 09 Jun '12

09 Jun '12

Early versions of coreboot did not create an SMBIOS table (which Linux needs in order to use the ACPI tables), so SeaBIOS had a hack to generate an SMBIOS table. However, recent versions of coreboot can generate an SMBIOS table, so there is no longer a reason to support this hack. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/Kconfig | 4 +--- src/coreboot.c | 4 ---- 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 53fda9b..25b2b1b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -303,14 +303,13 @@ menu "BIOS interfaces" endmenu menu "BIOS Tables" + depends on !COREBOOT config PIRTABLE - depends on !COREBOOT bool "PIR table" default y help Support generation of a PIR table in 0xf000 segment. config MPTABLE - depends on !COREBOOT bool "MPTable" default y help @@ -322,7 +321,6 @@ menu "BIOS Tables" Support generation of SM BIOS tables. This is also sometimes called DMI. config ACPI - depends on !COREBOOT bool "ACPI" default y help diff --git a/src/coreboot.c b/src/coreboot.c index 9de99af..55590ce 100644 --- a/src/coreboot.c +++ b/src/coreboot.c @@ -218,10 +218,6 @@ coreboot_copy_biostable(void) if (m->type == CB_MEM_TABLE) scan_tables(m->start, m->size); } - - // XXX - create a dummy smbios table for now. - if (!SMBiosAddr) - smbios_init(); } -- 1.7.6.5

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[PATCH 0/4] pci: 64bit pci window patches
by Gerd Hoffmann 09 Jun '12

09 Jun '12

Hi, Time to repost, aiming for merge. The patches survived my local testing and win2k8 testing by Alexey. Patch #4 got some finishing touches: Tries two 64bit I/O window sizes only, also added a comment explaining why it is done. Rebased to latest master. cheers, Gerd Gerd Hoffmann (4): update bios date pciinit: make pci ressources configurable update dsdt ressources at runtime pci: runtime i/o window sizing src/acpi-dsdt.dsl | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-- src/acpi.c | 28 ++++++++++++++++++++++- src/acpi.h | 9 +++++++ src/pci.h | 2 + src/pciinit.c | 46 +++++++++++++++++++++++++++++++------ src/smbios.c | 2 +- 6 files changed, 139 insertions(+), 13 deletions(-)

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[PATCH] Avoid runtime relocation of 16bit "low" mem - calculate at build instead.
by Kevin O'Connor 09 Jun '12

09 Jun '12

Some 16bit accesses to "low" mem variables use 16bit relocations instead of the normal 32bit relocations. This causes build problems if the "low" mem sections move more than 64K during relocation. The final location of the "low" memory can be determined during the build, so link the 16bit code with the final post-reloc location of the "low" mem variables instead. This eliminates the need to do these runtime relocations on the 16bit code. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/biosvar.h | 4 ++-- src/pmm.c | 14 ++++---------- src/post.c | 24 ++++++++++-------------- tools/layoutrom.py | 25 +++++++++++++------------ 4 files changed, 29 insertions(+), 38 deletions(-) diff --git a/src/biosvar.h b/src/biosvar.h index fd2f1bf..eceee54 100644 --- a/src/biosvar.h +++ b/src/biosvar.h @@ -250,13 +250,13 @@ static inline u16 get_global_seg(void) { * "Low" memory variables ****************************************************************/ -extern u8 _datalow_seg, _datalow_base[]; +extern u8 _datalow_seg, datalow_base[]; #define SEG_LOW ((u32)&_datalow_seg) #if MODESEGMENT #define GET_LOW(var) GET_FARVAR(SEG_LOW, (var)) #define SET_LOW(var, val) SET_FARVAR(SEG_LOW, (var), (val)) -#define LOWFLAT2LOW(var) ((typeof(var))((void*)(var) - (u32)_datalow_base)) +#define LOWFLAT2LOW(var) ((typeof(var))((void*)(var) - (u32)datalow_base)) #else #define GET_LOW(var) (var) #define SET_LOW(var, val) do { (var) = (val); } while (0) diff --git a/src/pmm.c b/src/pmm.c index 5d43645..1addb41 100644 --- a/src/pmm.c +++ b/src/pmm.c @@ -170,13 +170,6 @@ static struct allocinfo_s *RomBase; #define OPROM_HEADER_RESERVE 16 -// Return maximum address of read/writable "low mem" space. -static inline u32 lowmemend(void) { - extern u8 code32flat_start[], code32init_end[]; - u32 end = CONFIG_RELOCATE_INIT ? (u32)code32init_end : (u32)code32flat_start; - return end > BUILD_BIOS_ADDR ? BUILD_BIOS_ADDR : end; -} - // Return the memory position up to which roms may be located. u32 rom_get_top(void) @@ -199,8 +192,8 @@ rom_reserve(u32 size) u32 newend = ALIGN(RomEnd + size, OPTION_ROM_ALIGN) + OPROM_HEADER_RESERVE; if (newend > (u32)RomBase->allocend) return NULL; - if (newend < (u32)_datalow_base + OPROM_HEADER_RESERVE) - newend = (u32)_datalow_base + OPROM_HEADER_RESERVE; + if (newend < (u32)datalow_base + OPROM_HEADER_RESERVE) + newend = (u32)datalow_base + OPROM_HEADER_RESERVE; RomBase->data = RomBase->dataend = (void*)newend; return (void*)RomEnd; } @@ -253,7 +246,8 @@ malloc_setup(void) // Populate other regions addSpace(&ZoneTmpLow, (void*)BUILD_STACK_ADDR, (void*)BUILD_EBDA_MINIMUM); addSpace(&ZoneFSeg, BiosTableSpace, &BiosTableSpace[CONFIG_MAX_BIOSTABLE]); - addSpace(&ZoneLow, _datalow_base + OPROM_HEADER_RESERVE, (void*)lowmemend()); + extern u8 final_datalow_start[]; + addSpace(&ZoneLow, datalow_base + OPROM_HEADER_RESERVE, final_datalow_start); RomBase = findLast(&ZoneLow); if (highram) { addSpace(&ZoneHigh, (void*)highram diff --git a/src/post.c b/src/post.c index 1d0d35a..3101505 100644 --- a/src/post.c +++ b/src/post.c @@ -97,7 +97,7 @@ init_bda(void) , E820_RESERVED); // Init extra stack - StackPos = (void*)(&ExtraStack[BUILD_EXTRA_STACK_SIZE] - _datalow_base); + StackPos = (void*)(&ExtraStack[BUILD_EXTRA_STACK_SIZE] - datalow_base); } static void @@ -293,14 +293,14 @@ maininit(void) // Relocation fixup code that runs at new address after relocation complete. static void -afterReloc(void *datalow) +afterReloc(void) { // Running at new code address - do code relocation fixups malloc_fixupreloc(); // Move low-memory initial variable content to new location. - extern u8 datalow_start[], datalow_end[]; - memmove(datalow, datalow_start, datalow_end - datalow_start); + extern u8 datalow_start[], datalow_end[], final_datalow_start[]; + memmove(final_datalow_start, datalow_start, datalow_end - datalow_start); // Run main code maininit(); @@ -331,24 +331,20 @@ reloc_init(void) extern u32 _reloc_init_start[], _reloc_init_end[]; extern u8 code32init_start[], code32init_end[]; extern u32 _reloc_datalow_start[], _reloc_datalow_end[]; - extern u8 _datalow_min_align; - extern u8 datalow_start[], datalow_end[]; + extern u8 datalow_start[], datalow_end[], final_datalow_start[]; // Allocate space for init code. u32 initsize = code32init_end - code32init_start; u32 codealign = (u32)&_reloc_min_align; void *codedest = memalign_tmp(codealign, initsize); - u32 datalowsize = datalow_end - datalow_start; - u32 datalowalign = (u32)&_datalow_min_align; - void *datalow = memalign_low(datalowalign, datalowsize); - if (!codedest || !datalow) + if (!codedest) panic("No space for init relocation.\n"); // Copy code and update relocs (init absolute, init relative, and runtime) dprintf(1, "Relocating low data from %p to %p (size %d)\n" - , datalow_start, datalow, datalowsize); + , datalow_start, final_datalow_start, datalow_end - datalow_start); updateRelocs(code32flat_start, _reloc_datalow_start, _reloc_datalow_end - , datalow - (void*)datalow_start); + , final_datalow_start - datalow_start); dprintf(1, "Relocating init from %p to %p (size %d)\n" , code32init_start, codedest, initsize); s32 delta = codedest - (void*)code32init_start; @@ -358,9 +354,9 @@ reloc_init(void) updateRelocs(code32flat_start, _reloc_init_start, _reloc_init_end, delta); // Call maininit() in relocated code. - void (*func)(void*) = (void*)afterReloc + delta; + void (*func)(void) = (void*)afterReloc + delta; barrier(); - func(datalow); + func(); } // Setup for code relocation and then call reloc_init diff --git a/tools/layoutrom.py b/tools/layoutrom.py index 74b410f..7a7d08c 100755 --- a/tools/layoutrom.py +++ b/tools/layoutrom.py @@ -48,8 +48,6 @@ def setSectionsStart(sections, endaddr, minalign=1, segoffset=0): totspace = alignpos(totspace, section.align) + section.size startaddr = (endaddr - totspace) / minalign * minalign curaddr = startaddr - # out = [(addr, sectioninfo), ...] - out = [] for section in sections: curaddr = alignpos(curaddr, section.align) section.finalloc = curaddr @@ -159,7 +157,7 @@ class LayoutInfo: sections32flat = sec32flat_start = sec32flat_align = None sections32init = sec32init_start = sec32init_align = None sections32low = sec32low_start = sec32low_align = None - datalow_base = None + datalow_base = final_sec32low_start = None # Determine final memory addresses for sections def doLayout(sections, genreloc): @@ -219,13 +217,17 @@ def doLayout(sections, genreloc): li.sections32low = getSectionsCategory(sections, '32low') if genreloc: sec32low_top = li.sec32init_start - datalow_base = min(BUILD_BIOS_ADDR, li.sec32flat_start) - 64*1024 + final_sec32low_top = min(BUILD_BIOS_ADDR, li.sec32flat_start) else: sec32low_top = min(BUILD_BIOS_ADDR, li.sec32init_start) - datalow_base = sec32low_top - 64*1024 + final_sec32low_top = sec32low_top + relocdelta = final_sec32low_top - sec32low_top + datalow_base = final_sec32low_top - 64*1024 li.datalow_base = max(BUILD_ROM_START, alignpos(datalow_base, 2*1024)) li.sec32low_start, li.sec32low_align = setSectionsStart( - li.sections32low, sec32low_top, 16, segoffset=li.datalow_base) + li.sections32low, sec32low_top, 16 + , segoffset=li.datalow_base - relocdelta) + li.final_sec32low_start = li.sec32low_start + relocdelta # Print statistics size16 = BUILD_BIOS_ADDR + BUILD_BIOS_SIZE - li.sec16_start @@ -311,7 +313,7 @@ def getSectionsStart(sections, defaddr=0): def writeLinkerScripts(li, entrysym, genreloc, out16, out32seg, out32flat): # Write 16bit linker script out = outXRefs(li.sections16, useseg=1) + """ - _datalow_base = 0x%x ; + datalow_base = 0x%x ; _datalow_seg = 0x%x ; code16_start = 0x%x ; @@ -352,8 +354,7 @@ def writeLinkerScripts(li, entrysym, genreloc, out16, out32seg, out32flat): initrelocs = getRelocs( li.sections32flat + li.sections32low + li.sections16 + li.sections32seg, category='32init') - lowrelocs = getRelocs( - li.sections16 + li.sections32seg + sections32all, category='32low') + lowrelocs = getRelocs(sections32all, category='32low') relocstr = (strRelocs("_reloc_abs", "code32init_start", absrelocs) + strRelocs("_reloc_rel", "code32init_start", relrelocs) + strRelocs("_reloc_init", "code32flat_start", initrelocs) @@ -363,8 +364,8 @@ def writeLinkerScripts(li, entrysym, genreloc, out16, out32seg, out32flat): out = outXRefs(sections32all) + """ %s = 0x%x ; _reloc_min_align = 0x%x ; - _datalow_base = 0x%x ; - _datalow_min_align = 0x%x ; + datalow_base = 0x%x ; + final_datalow_start = 0x%x ; code32flat_start = 0x%x ; .text code32flat_start : { @@ -385,7 +386,7 @@ def writeLinkerScripts(li, entrysym, genreloc, out16, out32seg, out32flat): """ % (entrysym.name, entrysympos, li.sec32init_align, li.datalow_base, - li.sec32low_align, + li.final_sec32low_start, sec32all_start, relocstr, outRelSections(li.sections32low, 'code32flat_start'), -- 1.7.6.5

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Re: [SeaBIOS] [PATCH] Boot from multiple USB drives as well as an HDD
by Kevin O'Connor 08 Jun '12

08 Jun '12

On Thu, Jun 07, 2012 at 01:58:06PM -0600, Steve Goodrich wrote: > This change adds support for multiple USB mass storage devices in the boot > sequence. Previously, only one HDD device (which included both USB and SATA > drives) was allowed in the boot sequence; USB drives were treated as HDDs. > This code allows USB drives to be treated separately from SATA drives. Only > one HDD is allowed to boot (0x80) as has always been the case. However, > multiple USB drives can be tried in the order they are selected in the > Bootlist. I don't understand how this works. The problem with HD booting from anything other than 0x80 is that boot loaders don't know which hard drive to boot from, so they always try drive 0x80. Since USB images use the same boot loaders as hard drives, I don't see how your patch works. [...] > @@ -655,11 +674,15 @@ do_boot(int seq_nr) > break; > case IPL_TYPE_HARDDISK: > printf("Booting from Hard Disk...\n"); > - boot_disk(0x80, 1); > + boot_disk(EXTSTART_HD, 1); > break; > case IPL_TYPE_CDROM: > boot_cdrom((void*)ie->vector); > break; In the above, CDROMs can boot from any drive because the CD booting spec (El-Torito) clearly states the boot loader must use the drive specified in the dl register. > + case IPL_TYPE_USB: > + printf("Booting from USB drive...\n"); > + boot_disk(EXTSTART_USB + USB_Drive_Number++, 1); > + break; This will set the 'dl' register to something (eg, 0xc0), but we can't be sure the boot loader will honor it. So, as far as I understand, this wont work. What images did you test with? -Kevin

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