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Re: [SeaBIOS] [RFC PATCH v3 00/19] ACPI memory hotplug
by Blue Swirl 22 Sep '12

22 Sep '12

On Fri, Sep 21, 2012 at 11:17 AM, Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> wrote: > This is v3 of the ACPI memory hotplug functionality. Only x86_64 target is supported > for now. > > Overview: > > Dimm device layout is modeled with a new qemu command line > > "-dimm id=name,size=sz,node=pxm,populated=on|off" > > The starting physical address for all dimms is calculated automatically from > top of memory, skipping the pci hole at [PCI_HOLE_START, 4G). > Node is defining numa proximity for this dimm. When not defined it defaults > to zero. > "-dimm id=dimm0,size=512M,node=0,populated=off" > will define a 512M memory slot belonging to numa node 0. > > Dimms are added or removed with normal device_add, device_del operations: > Hot-add syntax: "device_add dimm,id=mydimm0" > Hot-remove syntax: "dimm_del dimm,id=mydimm0" > > Changes v2->v3 > > - qdev integration. Dimms are attached to a dimmbus. The dimmbus is a child > of i440fx device in the pc machine. Hot-add and hot-remove are done with normal > device_add / device_del operations on the dimmbus. New commands "dimm_add" and > "dimm_del" are obsolete. (In previous versions, dimms were always present on the > qdev tree, and dimm_add/del simply meant allocating or deallocating memory for > the devices. This version actually does hot-operations on the qdev tree) > - Add _PS3 method to allow OSPM-induced hot operations. > - pci-window calculation in Seabios takes dimms into account(for both 32-bit and > 64-bit windows) > - rename new qmp commands: query-memory-total and query-memory-hotplug > - balloon driver can see the hotplugged memory > > Changes v1->v2 > > - memory map is automatically calculated for hotplug dimms. Dimms are added from > top-of-memory skipping the pci hole at [PCI_HOLE_START, 4G). > - Renamed from "-memslot" to "-dimm". Commands changed to "dimm_add", "dimm_del". > - Seabios ejection array reduced to a byte. Use extraction macros for dimm ssdt. > - additional SRAT paravirt info does not break previous SRAT fw_cfg layout. > - Documentation of new acpi_piix4 registers and paravirt data. > - add ACPI _OST support for _OST enabled guests. This allows qemu to receive > notification for success / failure of memory hot-add and hot-remove operations. > Guest needs to support _OST (https://lkml.org/lkml/2012/6/25/321) > - add monitor info command to report total guest memory (initial + hot-added) > - add command line options and monitor commands for batch dimm > creation/population (obsolete from v3 onwards) > > Issues: > > - A main blocker issue is windows guest functionality. The patchset does not work for > windows currently. My guess is the windows pnpmem driver does not like the > seabios dimm device implementation (or the seabios dimm implementation is not > fully ACPI-compliant). If someone can review the seabios patches or has any > ideas to debug this, let me know. > > Testing on win2012 server RC or windows2008 consumer prerelease. When adding a > DIMM, the device shows up in DeviceManager but does not work. > Relevant messages: > > " This device cannot start. (Code 10) > Device configured(memory.inf) (UserPnP eventID 400) > Device installed (memory.inf) ACPI/PNP0C80\2&daba3ff&1 was configured > Device not started(PNPMEM) (Kernel-PnP eventID 411, kernelID) > Device ACPI\PNP0C80\2&daba3ff&1 had a problem starting Driver Name: memory.inf > (c:\Windows\system32\DRIVERS\pnpmem.sys 6.2.8400 winmain_win8rc)) > Memory range:0x80000000 - 0x90000000 (Initial memory of VM is 2GB. The hotplugged DIMM > was a 256GB with physical address range starting at 2GB ) > Conflicting device list: No conflicts. " > > Adding a 2nd or more dimms causes a crash (PNP_DETECTED_FATAL_ERROR with blue > screen of death) and makes windows reboot. After this, the VM keeps rebooting with > ACPI_BIOS_ERROR. The VM refuses to boot anymore once a 2nd (or more) extra dimm is > plugged-in. > > - Is the dimmbus the correct way to go about integrating into qdev/qom? In a v1 > comment, Anthony mentioned attaching dimms directly to an i440fx device as > children. Is this possible without a bus? > > - Live migration works as long as the dimm layout (-dimm command line args) are > identical at the source and destination qemu command line. Patch 10/19 > creates the DimmDevice that corresponds to the unknown incoming ramblock. > Ramblocks are migrated before qdev VMStates are migrated (the DimmDevice structure > currently does not define a VMStateDescription). So the DimmDevice is handled > diferrently than other devices. If this is not acceptable, any suggestions on > how should it be reworked? > > - Hot-operation notification lists need to be added to migration state. > > Please review. Could people state which other issues they consider blocker for > including this upstream? Please check the patches with checkpatch.pl, there are plenty of missing braces and uses of __FUNCTION__ etc. I also have other comments to specific patches, especially the architecture does not look correct. > > Does this patchset need to wait for 1.4 or could this be considered for 1.3 (assuming > blockers are resolved)? The patchset has been revised every few months, but > I will provide quicker version updates onwards. I can also bring this up on a weekly > meeting agenda if needed. > > series is based on uq/master for qemu-kvm, and master for seabios. Can be found > also at: > > http://github.com/vliaskov/qemu-kvm/commits/memhp-v3 > http://github.com/vliaskov/seabios/commits/memhp-v3 > > Vasilis Liaskovitis (12): > Implement dimm device abstraction > Implement "-dimm" command line option > acpi_piix4: Implement memory device hotplug registers > pc: calculate dimm physical addresses and adjust memory map > pc: Add dimm paravirt SRAT info > fix live-migration when "populated=on" is missing > Implement qmp and hmp commands for notification lists > Implement "info memory-total" and "query-memory-total" > balloon: update with hotplugged memory > Add _OST dimm support > Update dimm state on reset > Implement _PS3 for dimm > > arch_init.c | 24 ++- > docs/specs/acpi_hotplug.txt | 54 ++++++ > docs/specs/fwcfg.txt | 28 +++ > hmp-commands.hx | 4 + > hmp.c | 24 +++ > hmp.h | 2 + > hw/Makefile.objs | 2 +- > hw/acpi_piix4.c | 114 +++++++++++- > hw/dimm.c | 435 +++++++++++++++++++++++++++++++++++++++++++ > hw/dimm.h | 101 ++++++++++ > hw/pc.c | 55 ++++++- > hw/pc.h | 6 + > hw/pc_piix.c | 20 ++- > hw/virtio-balloon.c | 13 +- > monitor.c | 14 ++ > qapi-schema.json | 37 ++++ > qemu-config.c | 25 +++ > qemu-options.hx | 5 + > qmp-commands.hx | 57 ++++++ > sysemu.h | 1 + > vl.c | 51 +++++ > 21 files changed, 1051 insertions(+), 21 deletions(-) > create mode 100644 docs/specs/acpi_hotplug.txt > create mode 100644 docs/specs/fwcfg.txt > create mode 100644 hw/dimm.c > create mode 100644 hw/dimm.h > > Vasilis Liaskovitis (7): > Add ACPI_EXTRACT_DEVICE* macros > Subject: [PATCH 02/18] Add SSDT memory device support > acpi-dsdt: Implement functions for memory hotplug > acpi: generate hotplug memory devices > Add _OST dimm method > Implement _PS3 method for memory device > Calculate pcimem_start and pcimem64_start from SRAT entries > > Makefile | 2 +- > src/acpi-dsdt.dsl | 135 ++++++++++++++++++++++++++++++- > src/acpi.c | 216 ++++++++++++++++++++++++++++++++++++++++++++---- > src/acpi.h | 3 + > src/pciinit.c | 6 +- > src/post.c | 3 + > src/smp.c | 4 + > src/ssdt-mem.dsl | 73 +++++++++++++++++ > tools/acpi_extract.py | 28 +++++++ > 9 files changed, 447 insertions(+), 23 deletions(-) > create mode 100644 src/ssdt-mem.dsl > > > -- > 1.7.9 >

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Re: [SeaBIOS] [RFC PATCH v3 08/19] pc: calculate dimm physical addresses and adjust memory map
by Blue Swirl 22 Sep '12

22 Sep '12

On Fri, Sep 21, 2012 at 11:17 AM, Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> wrote: > Dimm physical address offsets are calculated automatically and memory map is > adjusted accordingly. If a DIMM can fit before the PCI_HOLE_START (currently > 0xe0000000), it will be added normally, otherwise its physical address will be > above 4GB. > > Also create memory bus on i440fx-pcihost device. > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > hw/pc.c | 41 +++++++++++++++++++++++++++++++++++++++++ > hw/pc.h | 6 ++++++ > hw/pc_piix.c | 20 ++++++++++++++------ > vl.c | 1 + > 4 files changed, 62 insertions(+), 6 deletions(-) > > diff --git a/hw/pc.c b/hw/pc.c > index 112739a..2c9664d 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -52,6 +52,7 @@ > #include "arch_init.h" > #include "bitmap.h" > #include "vga-pci.h" > +#include "dimm.h" > > /* output Bochs bios info messages */ > //#define DEBUG_BIOS > @@ -93,6 +94,9 @@ struct e820_table { > static struct e820_table e820_table; > struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; > > +ram_addr_t below_4g_hp_mem_size = 0; > +ram_addr_t above_4g_hp_mem_size = 0; > +extern target_phys_addr_t ram_hp_offset; extern declarations belong to headers only. > void gsi_handler(void *opaque, int n, int level) > { > GSIState *s = opaque; > @@ -1160,3 +1164,40 @@ void pc_pci_device_init(PCIBus *pci_bus) > pci_create_simple(pci_bus, -1, "lsi53c895a"); > } > } > + > + > +/* Function to configure memory offsets of hotpluggable dimms */ > + > +target_phys_addr_t pc_set_hp_memory_offset(uint64_t size) > +{ > + target_phys_addr_t ret; > + > + /* on first call, initialize ram_hp_offset */ > + if (!ram_hp_offset) { > + if (ram_size >= PCI_HOLE_START ) { > + ram_hp_offset = 0x100000000LL + (ram_size - PCI_HOLE_START); > + } else { > + ram_hp_offset = ram_size; > + } > + } > + > + if (ram_hp_offset >= 0x100000000LL) { > + ret = ram_hp_offset; > + above_4g_hp_mem_size += size; > + ram_hp_offset += size; > + } > + /* if dimm fits before pci hole, append it normally */ > + else if (ram_hp_offset + size <= PCI_HOLE_START) { } else if ... > + ret = ram_hp_offset; > + below_4g_hp_mem_size += size; > + ram_hp_offset += size; > + } > + /* otherwise place it above 4GB */ > + else { } else { > + ret = 0x100000000LL; > + above_4g_hp_mem_size += size; > + ram_hp_offset = 0x100000000LL + size; > + } > + > + return ret; > +} But the function and use of lots of global variables is ugly. The dimm devices should be just created in piix_pci.c (i440fx) directly with correct offsets and sizes, so all below_4g_mem_size etc. calculations should be moved there. That would implement the PMC part of i440fx. For ISA PC, probably the board should create the DIMMs since there may not be a memory controller. The >4G logic does not make sense there anyway. > diff --git a/hw/pc.h b/hw/pc.h > index e4db071..f3304fc 100644 > --- a/hw/pc.h > +++ b/hw/pc.h > @@ -10,6 +10,7 @@ > #include "memory.h" > #include "ioapic.h" > > +#define PCI_HOLE_START 0xe0000000 > /* PC-style peripherals (also used by other machines). */ > > /* serial.c */ > @@ -214,6 +215,11 @@ static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) > /* pc_sysfw.c */ > void pc_system_firmware_init(MemoryRegion *rom_memory); > > +/* memory hotplug */ > +target_phys_addr_t pc_set_hp_memory_offset(uint64_t size); > +extern ram_addr_t below_4g_hp_mem_size; > +extern ram_addr_t above_4g_hp_mem_size; > + > /* e820 types */ > #define E820_RAM 1 > #define E820_RESERVED 2 > diff --git a/hw/pc_piix.c b/hw/pc_piix.c > index 88ff041..d1fd276 100644 > --- a/hw/pc_piix.c > +++ b/hw/pc_piix.c > @@ -43,6 +43,7 @@ > #include "xen.h" > #include "memory.h" > #include "exec-memory.h" > +#include "dimm.h" > #ifdef CONFIG_XEN > # include <xen/hvm/hvm_info_table.h> > #endif > @@ -155,9 +156,9 @@ static void pc_init1(MemoryRegion *system_memory, > kvmclock_create(); > } > > - if (ram_size >= 0xe0000000 ) { > - above_4g_mem_size = ram_size - 0xe0000000; > - below_4g_mem_size = 0xe0000000; > + if (ram_size >= PCI_HOLE_START ) { > + above_4g_mem_size = ram_size - PCI_HOLE_START; > + below_4g_mem_size = PCI_HOLE_START; > } else { > above_4g_mem_size = 0; > below_4g_mem_size = ram_size; > @@ -172,6 +173,9 @@ static void pc_init1(MemoryRegion *system_memory, > rom_memory = system_memory; > } > > + /* adjust memory map for hotplug dimms */ > + dimm_calc_offsets(pc_set_hp_memory_offset); > + > /* allocate ram and load rom/bios */ > if (!xen_enabled()) { > fw_cfg = pc_memory_init(system_memory, > @@ -192,9 +196,11 @@ static void pc_init1(MemoryRegion *system_memory, > if (pci_enabled) { > pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, > system_memory, system_io, ram_size, > - below_4g_mem_size, > - 0x100000000ULL - below_4g_mem_size, > - 0x100000000ULL + above_4g_mem_size, > + below_4g_mem_size + below_4g_hp_mem_size, > + 0x100000000ULL - below_4g_mem_size > + - below_4g_hp_mem_size, > + 0x100000000ULL + above_4g_mem_size > + + above_4g_hp_mem_size, > (sizeof(target_phys_addr_t) == 4 > ? 0 > : ((uint64_t)1 << 62)), > @@ -223,6 +229,8 @@ static void pc_init1(MemoryRegion *system_memory, > ioapic_init(gsi_state); > } > > + main_memory_bus_create(object_resolve_path("i440fx", NULL)); > + > pc_register_ferr_irq(gsi[13]); > > pc_vga_init(isa_bus, pci_enabled ? pci_bus : NULL); > diff --git a/vl.c b/vl.c > index af1745c..2282910 100644 > --- a/vl.c > +++ b/vl.c > @@ -184,6 +184,7 @@ DisplayType display_type = DT_DEFAULT; > int display_remote = 0; > const char* keyboard_layout = NULL; > ram_addr_t ram_size; > +ram_addr_t ram_hp_offset; > const char *mem_path = NULL; > #ifdef MAP_POPULATE > int mem_prealloc = 0; /* force preallocation of physical target memory */ > -- > 1.7.9 >

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Re: [SeaBIOS] [RFC PATCH v3 07/19] acpi_piix4: Implement memory device hotplug registers
by Blue Swirl 22 Sep '12

22 Sep '12

On Fri, Sep 21, 2012 at 11:17 AM, Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> wrote: > A 32-byte register is used to present up to 256 hotplug-able memory devices > to BIOS and OSPM. Hot-add and hot-remove functions trigger an ACPI hotplug > event through these. Only reads are allowed from these registers. > > An ACPI hot-remove event but needs to wait for OSPM to eject the device. > We use a single-byte register to know when OSPM has called the _EJ function > for a particular dimm. A write to this byte will depopulate the respective dimm. > Only writes are allowed to this byte. > > v1->v2: > mems_sts address moved from 0xaf20 to 0xaf80 (to accomodate more space for > cpu-hotplugging in the future). > _EJ array is reduced to a single byte. > Add documentation in docs/specs/acpi_hotplug.txt > > v2->v3: > minor name changes > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > docs/specs/acpi_hotplug.txt | 22 +++++++++++++ > hw/acpi_piix4.c | 73 ++++++++++++++++++++++++++++++++++++++++-- > 2 files changed, 91 insertions(+), 4 deletions(-) > create mode 100644 docs/specs/acpi_hotplug.txt > > diff --git a/docs/specs/acpi_hotplug.txt b/docs/specs/acpi_hotplug.txt > new file mode 100644 > index 0000000..cf86242 > --- /dev/null > +++ b/docs/specs/acpi_hotplug.txt > @@ -0,0 +1,22 @@ > +QEMU<->ACPI BIOS hotplug interface > +-------------------------------------- > +This document describes the interface between QEMU and the ACPI BIOS for non-PCI > +space. For the PCI interface please look at docs/specs/acpi_pci_hotplug.txt > + > +QEMU<->ACPI BIOS memory hotplug interface > +-------------------------------------- > + > +Memory Dimm status array (IO port 0xaf80-0xaf9f, 1-byte access): > +--------------------------------------------------------------- > +Dimm hot-plug notification pending. One bit per slot. > + > +Read by ACPI BIOS GPE.3 handler to notify OS of memory hot-add or hot-remove > +events. Read-only. > + > +Memory Dimm ejection success notification (IO port 0xafa0, 1-byte access): > +--------------------------------------------------------------- > +Dimm hot-remove _EJ0 notification. Byte value indicates Dimm slot that was > +ejected. > + > +Written by ACPI memory device _EJ0 method to notify qemu of successfull > +hot-removal. Write-only. > diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c > index c56220b..8776669 100644 > --- a/hw/acpi_piix4.c > +++ b/hw/acpi_piix4.c > @@ -28,6 +28,8 @@ > #include "range.h" > #include "ioport.h" > #include "fw_cfg.h" > +#include "sysbus.h" > +#include "dimm.h" > > //#define DEBUG > > @@ -45,9 +47,15 @@ > #define PCI_DOWN_BASE 0xae04 > #define PCI_EJ_BASE 0xae08 > #define PCI_RMV_BASE 0xae0c > +#define MEM_BASE 0xaf80 > +#define MEM_EJ_BASE 0xafa0 > > +#define PIIX4_MEM_HOTPLUG_STATUS 8 > #define PIIX4_PCI_HOTPLUG_STATUS 2 > > +struct gpe_regs { GPERegs > + uint8_t mems_sts[DIMM_BITMAP_BYTES]; > +}; > struct pci_status { > uint32_t up; /* deprecated, maintained for migration compatibility */ > uint32_t down; > @@ -69,6 +77,7 @@ typedef struct PIIX4PMState { > Notifier machine_ready; > > /* for pci hotplug */ > + struct gpe_regs gperegs; > struct pci_status pci0_status; > uint32_t pci0_hotplug_enable; > uint32_t pci0_slot_device_present; > @@ -93,8 +102,8 @@ static void pm_update_sci(PIIX4PMState *s) > ACPI_BITMASK_POWER_BUTTON_ENABLE | > ACPI_BITMASK_GLOBAL_LOCK_ENABLE | > ACPI_BITMASK_TIMER_ENABLE)) != 0) || > - (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) > - & PIIX4_PCI_HOTPLUG_STATUS) != 0); > + (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & > + (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_MEM_HOTPLUG_STATUS)) != 0); > > qemu_set_irq(s->irq, sci_level); > /* schedule a timer interruption if needed */ > @@ -499,7 +508,16 @@ type_init(piix4_pm_register_types) > static uint32_t gpe_readb(void *opaque, uint32_t addr) > { > PIIX4PMState *s = opaque; > - uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); > + uint32_t val = 0; > + struct gpe_regs *g = &s->gperegs; > + > + switch (addr) { > + case MEM_BASE ... MEM_BASE+DIMM_BITMAP_BYTES: > + val = g->mems_sts[addr - MEM_BASE]; > + break; > + default: > + val = acpi_gpe_ioport_readb(&s->ar, addr); > + } > > PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); > return val; > @@ -509,7 +527,13 @@ static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) > { > PIIX4PMState *s = opaque; > > - acpi_gpe_ioport_writeb(&s->ar, addr, val); > + switch (addr) { > + case MEM_EJ_BASE: > + dimm_notify(val, DIMM_REMOVE_SUCCESS); > + break; > + default: > + acpi_gpe_ioport_writeb(&s->ar, addr, val); > + } > pm_update_sci(s); > > PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); > @@ -560,9 +584,11 @@ static uint32_t pcirmv_read(void *opaque, uint32_t addr) > > static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, > PCIHotplugState state); > +static int piix4_dimm_hotplug(DeviceState *qdev, DimmDevice *dev, int add); > > static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) > { > + int i = 0; > > register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); > register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); > @@ -576,7 +602,15 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) > > register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); > > + register_ioport_read(MEM_BASE, DIMM_BITMAP_BYTES, 1, gpe_readb, s); > + register_ioport_write(MEM_EJ_BASE, 1, 1, gpe_writeb, s); > + > + for(i = 0; i < DIMM_BITMAP_BYTES; i++) { > + s->gperegs.mems_sts[i] = 0; > + } > + > pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); > + dimm_bus_hotplug(piix4_dimm_hotplug, &s->dev.qdev); > } > > static void enable_device(PIIX4PMState *s, int slot) > @@ -591,6 +625,37 @@ static void disable_device(PIIX4PMState *s, int slot) > s->pci0_status.down |= (1U << slot); > } > > +static void enable_mem_device(PIIX4PMState *s, int memdevice) > +{ > + struct gpe_regs *g = &s->gperegs; > + s->ar.gpe.sts[0] |= PIIX4_MEM_HOTPLUG_STATUS; > + g->mems_sts[memdevice/8] |= (1 << (memdevice%8)); > +} > + > +static void disable_mem_device(PIIX4PMState *s, int memdevice) > +{ > + struct gpe_regs *g = &s->gperegs; > + s->ar.gpe.sts[0] |= PIIX4_MEM_HOTPLUG_STATUS; > + g->mems_sts[memdevice/8] &= ~(1 << (memdevice%8)); > +} > + > +static int piix4_dimm_hotplug(DeviceState *qdev, DimmDevice *dev, int > + add) > +{ > + PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, qdev); > + PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, pci_dev); > + DimmDevice *slot = DIMM(dev); > + > + if (add) { > + enable_mem_device(s, slot->idx); > + } > + else { } else { > + disable_mem_device(s, slot->idx); > + } > + pm_update_sci(s); > + return 0; > +} > + > static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, > PCIHotplugState state) > { > -- > 1.7.9 >

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Re: [SeaBIOS] [RFC PATCH v3 06/19] Implement "-dimm" command line option
by Blue Swirl 22 Sep '12

22 Sep '12

On Fri, Sep 21, 2012 at 11:17 AM, Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> wrote: > Example: > "-dimm id=dimm0,size=512M,node=0,populated=off" There should not be a need to introduce a new top level option, instead you should just use -device, like -device dimm,base=0,id=dimm0,size=512M,node=0,populated=off That would also specify the start address. > will define a 512M memory slot belonging to numa node 0. > > When "populated=on", a DimmDevice is created and hot-plugged at system startup. > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > hw/Makefile.objs | 2 +- > qemu-config.c | 25 +++++++++++++++++++++++++ > qemu-options.hx | 5 +++++ > sysemu.h | 1 + > vl.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 82 insertions(+), 1 deletions(-) > > diff --git a/hw/Makefile.objs b/hw/Makefile.objs > index 6dfebd2..8c5c39a 100644 > --- a/hw/Makefile.objs > +++ b/hw/Makefile.objs > @@ -26,7 +26,7 @@ hw-obj-$(CONFIG_I8254) += i8254_common.o i8254.o > hw-obj-$(CONFIG_PCSPK) += pcspk.o > hw-obj-$(CONFIG_PCKBD) += pckbd.o > hw-obj-$(CONFIG_FDC) += fdc.o > -hw-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o > +hw-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o dimm.o > hw-obj-$(CONFIG_APM) += pm_smbus.o apm.o > hw-obj-$(CONFIG_DMA) += dma.o > hw-obj-$(CONFIG_I82374) += i82374.o > diff --git a/qemu-config.c b/qemu-config.c > index eba977e..4022d64 100644 > --- a/qemu-config.c > +++ b/qemu-config.c > @@ -646,6 +646,30 @@ QemuOptsList qemu_boot_opts = { > }, > }; > > +static QemuOptsList qemu_dimm_opts = { > + .name = "dimm", > + .head = QTAILQ_HEAD_INITIALIZER(qemu_dimm_opts.head), > + .desc = { > + { > + .name = "id", > + .type = QEMU_OPT_STRING, > + .help = "id of this dimm device", > + },{ > + .name = "size", > + .type = QEMU_OPT_SIZE, > + .help = "memory size for this dimm", > + },{ > + .name = "populated", > + .type = QEMU_OPT_BOOL, > + .help = "populated for this dimm", > + },{ > + .name = "node", > + .type = QEMU_OPT_NUMBER, > + .help = "NUMA node number (i.e. proximity) for this dimm", > + }, > + { /* end of list */ } > + }, > +}; > static QemuOptsList *vm_config_groups[32] = { > &qemu_drive_opts, > &qemu_chardev_opts, > @@ -662,6 +686,7 @@ static QemuOptsList *vm_config_groups[32] = { > &qemu_boot_opts, > &qemu_iscsi_opts, > &qemu_sandbox_opts, > + &qemu_dimm_opts, > NULL, > }; > > diff --git a/qemu-options.hx b/qemu-options.hx > index 804a2d1..3687722 100644 > --- a/qemu-options.hx > +++ b/qemu-options.hx > @@ -2842,3 +2842,8 @@ HXCOMM This is the last statement. Insert new options before this line! > STEXI > @end table > ETEXI > + > +DEF("dimm", HAS_ARG, QEMU_OPTION_dimm, > + "-dimm id=dimmid,size=sz,node=nd,populated=on|off\n" > + "specify memory dimm device with name dimmid, size sz on node nd", > + QEMU_ARCH_ALL) > diff --git a/sysemu.h b/sysemu.h > index 65552ac..7baf9c9 100644 > --- a/sysemu.h > +++ b/sysemu.h > @@ -139,6 +139,7 @@ extern QEMUClock *rtc_clock; > extern int nb_numa_nodes; > extern uint64_t node_mem[MAX_NODES]; > extern unsigned long *node_cpumask[MAX_NODES]; > +extern int nb_hp_dimms; > > #define MAX_OPTION_ROMS 16 > typedef struct QEMUOptionRom { > diff --git a/vl.c b/vl.c > index 7c577fa..af1745c 100644 > --- a/vl.c > +++ b/vl.c > @@ -126,6 +126,7 @@ int main(int argc, char **argv) > #include "hw/xen.h" > #include "hw/qdev.h" > #include "hw/loader.h" > +#include "hw/dimm.h" > #include "bt-host.h" > #include "net.h" > #include "net/slirp.h" > @@ -248,6 +249,7 @@ QTAILQ_HEAD(, FWBootEntry) fw_boot_order = QTAILQ_HEAD_INITIALIZER(fw_boot_order > int nb_numa_nodes; > uint64_t node_mem[MAX_NODES]; > unsigned long *node_cpumask[MAX_NODES]; > +int nb_hp_dimms; This counter (if needed) should be private to dimm.c. > > uint8_t qemu_uuid[16]; > > @@ -530,6 +532,37 @@ static void configure_rtc_date_offset(const char *startdate, int legacy) > } > } > > +static void configure_dimm(QemuOpts *opts) > +{ > + const char *id; > + uint64_t size, node; > + bool populated; > + QemuOpts *devopts; > + char buf[256]; > + if (nb_hp_dimms == MAX_DIMMS) { Why should there be any limit of DIMMS? Please use lists etc. to avoid restrictions. > + fprintf(stderr, "qemu: maximum number of DIMMs (%d) exceeded\n", > + MAX_DIMMS); > + exit(1); > + } > + id = qemu_opts_id(opts); > + size = qemu_opt_get_size(opts, "size", DEFAULT_DIMMSIZE); > + populated = qemu_opt_get_bool(opts, "populated", 0); > + node = qemu_opt_get_number(opts, "node", 0); > + > + dimm_config_create((char*)id, size, node, nb_hp_dimms, 0); > + > + if (populated) { > + devopts = qemu_opts_create(qemu_find_opts("device"), id, 0, NULL); > + qemu_opt_set(devopts, "driver", "dimm"); > + snprintf(buf, sizeof(buf), "%lu", size); > + qemu_opt_set(devopts, "size", buf); > + snprintf(buf, sizeof(buf), "%lu", node); > + qemu_opt_set(devopts, "node", buf); > + qemu_opt_set(devopts, "bus", "membus"); > + } > + nb_hp_dimms++; > +} > + > static void configure_rtc(QemuOpts *opts) > { > const char *value; > @@ -2354,6 +2387,8 @@ int main(int argc, char **argv, char **envp) > DisplayChangeListener *dcl; > int cyls, heads, secs, translation; > QemuOpts *hda_opts = NULL, *opts, *machine_opts; > + QemuOpts *dimm_opts[MAX_DIMMS]; > + int nb_dimm_opts = 0; > QemuOptsList *olist; > int optind; > const char *optarg; > @@ -3288,6 +3323,18 @@ int main(int argc, char **argv, char **envp) > exit(0); > } > break; > + case QEMU_OPTION_dimm: > + if (nb_dimm_opts == MAX_DIMMS) { > + fprintf(stderr, "qemu: maximum number of DIMMs (%d) exceeded\n", > + MAX_DIMMS); > + } > + dimm_opts[nb_dimm_opts] = > + qemu_opts_parse(qemu_find_opts("dimm"), optarg, 0); > + if (!dimm_opts[nb_dimm_opts]) { > + exit(1); > + } > + nb_dimm_opts++; > + break; > default: > os_parse_cmd_args(popt->index, optarg); > } > @@ -3611,6 +3658,9 @@ int main(int argc, char **argv, char **envp) > } > qemu_add_globals(); > > + for (i = 0; i < nb_dimm_opts; i++) Missing braces, please read CODING_STYLE. > + configure_dimm(dimm_opts[i]); > + > qdev_machine_init(); > > machine->init(ram_size, boot_devices, > -- > 1.7.9 >

1 0

Re: [SeaBIOS] [RFC PATCH v3 12/19] Implement "info memory-total" and "query-memory-total"
by Eric Blake 22 Sep '12

22 Sep '12

On 09/21/2012 05:17 AM, Vasilis Liaskovitis wrote: > Returns total physical memory available to guest in bytes, including hotplugged > memory. Note that the number reported here may be different from what the guest > sees e.g. if the guest has not logically onlined hotplugged memory. > > This functionality is provided independently of a balloon device, since a > guest can be using ACPI memory hotplug without using a balloon device. > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > +++ b/hmp-commands.hx > @@ -1464,6 +1464,8 @@ show qdev device model list > show roms > @item info memory-hotplug > show memory-hotplug > +@item info memory-total > +show memory-total > +++ b/monitor.c > @@ -2747,6 +2747,13 @@ static mon_cmd_t info_cmds[] = { > .mhandler.info = hmp_info_memory_hotplug, > }, > { > + .name = "memory-total", We're split on HMP naming conventions ('-' vs. '_'); we have 'show migrate_capabilities' but 'show block-jobs'. Oh well, that's life. Reviewed-by: Eric Blake <eblake(a)redhat.com> -- Eric Blake eblake(a)redhat.com +1-919-301-3266 Libvirt virtualization library http://libvirt.org

1 0

[RFC PATCH v3 20/19] alternative: Use paravirt interface for pci windows
by Vasilis Liaskovitis 21 Sep '12

21 Sep '12

Initialize the 32-bit and 64-bit pci starting offsets from values passed in by the qemu paravirt interface QEMU_CFG_PCI_WINDOW. Qemu calculates the starting offsets based on initial memory and hotplug-able dimms. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- src/paravirt.c | 6 ++++++ src/paravirt.h | 2 ++ src/pciinit.c | 5 ++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/paravirt.c b/src/paravirt.c index 2a98d53..390ef30 100644 --- a/src/paravirt.c +++ b/src/paravirt.c @@ -346,3 +346,9 @@ void qemu_cfg_romfile_setup(void) dprintf(3, "Found fw_cfg file: %s (size=%d)\n", file->name, file->size); } } + +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start) +{ + qemu_cfg_read_entry(pcimem_start, QEMU_CFG_PCI_WINDOW, sizeof(u64)); + qemu_cfg_read((u8*)(pcimem64_start), sizeof(u64)); +} diff --git a/src/paravirt.h b/src/paravirt.h index a284c41..b53ff88 100644 --- a/src/paravirt.h +++ b/src/paravirt.h @@ -35,6 +35,7 @@ static inline int kvm_para_available(void) #define QEMU_CFG_BOOT_MENU 0x0e #define QEMU_CFG_MAX_CPUS 0x0f #define QEMU_CFG_FILE_DIR 0x19 +#define QEMU_CFG_PCI_WINDOW 0x1a #define QEMU_CFG_ARCH_LOCAL 0x8000 #define QEMU_CFG_ACPI_TABLES (QEMU_CFG_ARCH_LOCAL + 0) #define QEMU_CFG_SMBIOS_ENTRIES (QEMU_CFG_ARCH_LOCAL + 1) @@ -65,5 +66,6 @@ struct e820_reservation { u32 qemu_cfg_e820_entries(void); void* qemu_cfg_e820_load_next(void *addr); void qemu_cfg_romfile_setup(void); +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start); #endif diff --git a/src/pciinit.c b/src/pciinit.c index 68f302a..64468a0 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -592,8 +592,7 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) static void pci_bios_map_devices(struct pci_bus *busses) { - pcimem_start = RamSize; - + qemu_cfg_get_pci_offsets(&pcimem_start, &pcimem64_start); if (pci_bios_init_root_regions(busses)) { struct pci_region r64_mem, r64_pref; r64_mem.list = NULL; @@ -611,7 +610,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) u64 align_mem = pci_region_align(&r64_mem); u64 align_pref = pci_region_align(&r64_pref); - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); + r64_mem.base = ALIGN(pcimem64_start, align_mem); r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); pcimem64_start = r64_mem.base; pcimem64_end = r64_pref.base + sum_pref; -- 1.7.9

1 0

[RFC PATCH v3 19/19] alternative: Introduce paravirt interface QEMU_CFG_PCI_WINDOW
by Vasilis Liaskovitis 21 Sep '12

21 Sep '12

Qemu already calculates the 32-bit and 64-bit PCI starting offsets based on initial memory and hotplug-able dimms. This info needs to be passed to Seabios for PCI initialization. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- docs/specs/fwcfg.txt | 9 +++++++++ hw/fw_cfg.h | 1 + hw/pc_piix.c | 10 ++++++++++ 3 files changed, 20 insertions(+), 0 deletions(-) diff --git a/docs/specs/fwcfg.txt b/docs/specs/fwcfg.txt index 55f96d9..d9fa215 100644 --- a/docs/specs/fwcfg.txt +++ b/docs/specs/fwcfg.txt @@ -26,3 +26,12 @@ Entry max_cpus+nb_numa_nodes+1 contains the number of memory dimms (nb_hp_dimms) The last 3 * nb_hp_dimms entries are organized in triplets: Each triplet contains the physical address offset, size (in bytes), and node proximity for the respective dimm. + +FW_CFG_PCI_WINDOW paravirt info +-------------------- +QEMU passes the starting address for the 32-bit and 64-bit PCI windows to BIOS. +The following layouts are followed: + +-------------------------------- +pcimem32_start | pcimem64_start | +-------------------------------- diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h index 856bf91..6c8c151 100644 --- a/hw/fw_cfg.h +++ b/hw/fw_cfg.h @@ -27,6 +27,7 @@ #define FW_CFG_SETUP_SIZE 0x17 #define FW_CFG_SETUP_DATA 0x18 #define FW_CFG_FILE_DIR 0x19 +#define FW_CFG_PCI_WINDOW 0x1a #define FW_CFG_FILE_FIRST 0x20 #define FW_CFG_FILE_SLOTS 0x10 diff --git a/hw/pc_piix.c b/hw/pc_piix.c index d1fd276..034761f 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -44,6 +44,7 @@ #include "memory.h" #include "exec-memory.h" #include "dimm.h" +#include "fw_cfg.h" #ifdef CONFIG_XEN # include <xen/hvm/hvm_info_table.h> #endif @@ -149,6 +150,7 @@ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *pci_memory; MemoryRegion *rom_memory; void *fw_cfg = NULL; + uint64_t *pci_window_fw_cfg; pc_cpus_init(cpu_model); @@ -205,6 +207,14 @@ static void pc_init1(MemoryRegion *system_memory, ? 0 : ((uint64_t)1 << 62)), pci_memory, ram_memory); + + pci_window_fw_cfg = g_malloc0(2 * 8); + pci_window_fw_cfg[0] = cpu_to_le64(below_4g_mem_size + + below_4g_hp_mem_size); + pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL + above_4g_mem_size + + above_4g_hp_mem_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW, + (uint8_t *)pci_window_fw_cfg, 2 * 8); } else { pci_bus = NULL; i440fx_state = NULL; -- 1.7.9

1 0

[RFC PATCH v3 19/19] Calculate pcimem_start and pcimem64_start from SRAT entries
by Vasilis Liaskovitis 21 Sep '12

21 Sep '12

pcimem_start and pcimem64_start are adjusted from srat entries. For this reason, paravirt info (NUMA SRAT entries and number of cpus) need to be read before pci_setup. Imho, this is an ugly code change since SRAT bios tables and number of cpus have to be read earlier. But the advantage is that no new paravirt interface is introduced. Suggestions to make the code change cleaner are welcome. The alternative patch (will be sent as a reply to this patch) implements a paravirt interface to read the starting values of pcimem_start and pcimem64_start from QEMU. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- src/acpi.c | 82 ++++++++++++++++++++++++++++++++++++++++---------------- src/acpi.h | 3 ++ src/pciinit.c | 6 +++- src/post.c | 3 ++ src/smp.c | 4 +++ 5 files changed, 72 insertions(+), 26 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index 1223b52..9e99aa7 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -428,7 +428,10 @@ encodeLen(u8 *ssdt_ptr, int length, int bytes) #define MEM_OFFSET_END 63 #define MEM_OFFSET_SIZE 79 -u64 nb_hp_memslots = 0; +u64 nb_hp_memslots = 0, nb_numanodes; +u64 *numa_data, *hp_memdata; +u64 below_4g_hp_mem_size = 0; +u64 above_4g_hp_mem_size = 0; struct srat_memory_affinity *mem; #define SSDT_SIGNATURE 0x54445353 // SSDT @@ -763,17 +766,7 @@ acpi_build_srat_memory(struct srat_memory_affinity *numamem, static void * build_srat(void) { - int nb_numa_nodes = qemu_cfg_get_numa_nodes(); - - u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes)); - if (!numadata) { - warn_noalloc(); - return NULL; - } - - qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes); - - qemu_cfg_get_numa_data(&nb_hp_memslots, 1); + int nb_numa_nodes = nb_numanodes; struct system_resource_affinity_table *srat; int srat_size = sizeof(*srat) + sizeof(struct srat_processor_affinity) * MaxCountCPUs + @@ -782,7 +775,7 @@ build_srat(void) srat = malloc_high(srat_size); if (!srat) { warn_noalloc(); - free(numadata); + free(numa_data); return NULL; } @@ -791,6 +784,7 @@ build_srat(void) struct srat_processor_affinity *core = (void*)(srat + 1); int i; u64 curnode; + u64 *numadata = numa_data; for (i = 0; i < MaxCountCPUs; ++i) { core->type = SRAT_PROCESSOR; @@ -847,15 +841,7 @@ build_srat(void) mem = (void*)numamem; if (nb_hp_memslots) { - u64 *hpmemdata = malloc_tmphigh(sizeof(u64) * (3 * nb_hp_memslots)); - if (!hpmemdata) { - warn_noalloc(); - free(hpmemdata); - free(numadata); - return NULL; - } - - qemu_cfg_get_numa_data(hpmemdata, 3 * nb_hp_memslots); + u64 *hpmemdata = hp_memdata; for (i = 1; i < nb_hp_memslots + 1; ++i) { mem_base = *hpmemdata++; @@ -865,7 +851,7 @@ build_srat(void) numamem++; slots++; } - free(hpmemdata); + free(hp_memdata); } for (; slots < nb_numa_nodes + nb_hp_memslots + 2; slots++) { @@ -875,10 +861,58 @@ build_srat(void) build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1); - free(numadata); + free(numa_data); return srat; } +/* QEMU paravirt SRAT entries need to be read in before pci initilization */ +void read_srat_early(void) +{ + int i; + + nb_numanodes = qemu_cfg_get_numa_nodes(); + u64 *hpmemdata; + u64 mem_len, mem_base; + + numa_data = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numanodes)); + if (!numa_data) { + warn_noalloc(); + } + + qemu_cfg_get_numa_data(numa_data, MaxCountCPUs + nb_numanodes); + qemu_cfg_get_numa_data(&nb_hp_memslots, 1); + + if (nb_hp_memslots) { + hp_memdata = malloc_tmphigh(sizeof(u64) * (3 * nb_hp_memslots)); + if (!hp_memdata) { + warn_noalloc(); + free(hp_memdata); + free(numa_data); + } + + qemu_cfg_get_numa_data(hp_memdata, 3 * nb_hp_memslots); + hpmemdata = hp_memdata; + + for (i = 1; i < nb_hp_memslots + 1; ++i) { + mem_base = *hpmemdata++; + mem_len = *hpmemdata++; + hpmemdata++; + if (mem_base >= 0x100000000LL) { + above_4g_hp_mem_size += mem_len; + } + /* if dimm fits before pci hole, append it normally */ + else if (mem_base + mem_len <= BUILD_PCIMEM_START) { + below_4g_hp_mem_size += mem_len; + } + /* otherwise place it above 4GB */ + else { + above_4g_hp_mem_size += mem_len; + } + } + + } +} + static const struct pci_device_id acpi_find_tbl[] = { /* PIIX4 Power Management device. */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL), diff --git a/src/acpi.h b/src/acpi.h index cb21561..d29837f 100644 --- a/src/acpi.h +++ b/src/acpi.h @@ -5,6 +5,9 @@ void acpi_bios_init(void); u32 find_resume_vector(void); +void read_srat_early(void); +extern u64 below_4g_hp_mem_size; +extern u64 above_4g_hp_mem_size; #define RSDP_SIGNATURE 0x2052545020445352LL // "RSD PTR " diff --git a/src/pciinit.c b/src/pciinit.c index 31115ee..c5a4b24 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -12,6 +12,7 @@ #include "ioport.h" // PORT_ATA1_CMD_BASE #include "config.h" // CONFIG_* #include "xen.h" // usingXen +#include "acpi.h" #define PCI_DEVICE_MEM_MIN 0x1000 #define PCI_BRIDGE_IO_MIN 0x1000 @@ -597,7 +598,7 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) static void pci_bios_map_devices(struct pci_bus *busses) { - pcimem_start = RamSize; + pcimem_start = RamSize + below_4g_hp_mem_size; if (pci_bios_init_root_regions(busses)) { struct pci_region r64_mem, r64_pref; @@ -616,7 +617,8 @@ static void pci_bios_map_devices(struct pci_bus *busses) u64 align_mem = pci_region_align(&r64_mem); u64 align_pref = pci_region_align(&r64_pref); - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); + r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G + + above_4g_hp_mem_size, align_mem); r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); pcimem64_start = r64_mem.base; pcimem64_end = r64_pref.base + sum_pref; diff --git a/src/post.c b/src/post.c index 924b311..c37730b 100644 --- a/src/post.c +++ b/src/post.c @@ -234,6 +234,9 @@ maininit(void) // Initialize mtrr mtrr_setup(); + smp_get_ncpus(); + read_srat_early(); + // Initialize pci pci_setup(); smm_init(); diff --git a/src/smp.c b/src/smp.c index 4975412..3922776 100644 --- a/src/smp.c +++ b/src/smp.c @@ -138,7 +138,11 @@ smp_probe(void) // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; +} +void +smp_get_ncpus(void) +{ MaxCountCPUs = qemu_cfg_get_max_cpus(); if (!MaxCountCPUs || MaxCountCPUs < CountCPUs) MaxCountCPUs = CountCPUs; -- 1.7.9

1 0

[RFC PATCH v3 18/19] Implement _PS3 for dimm
by Vasilis Liaskovitis 21 Sep '12

21 Sep '12

This will allow us to update dimm state on OSPM-initiated eject operations e.g. with "echo 1 > /sys/bus/acpi/devices/PNP0C80\:00/eject" Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- docs/specs/acpi_hotplug.txt | 7 +++++++ hw/acpi_piix4.c | 5 +++++ hw/dimm.c | 3 +++ hw/dimm.h | 3 ++- 4 files changed, 17 insertions(+), 1 deletions(-) diff --git a/docs/specs/acpi_hotplug.txt b/docs/specs/acpi_hotplug.txt index 536da16..69868fe 100644 --- a/docs/specs/acpi_hotplug.txt +++ b/docs/specs/acpi_hotplug.txt @@ -45,3 +45,10 @@ insertion failed. Written by ACPI memory device _OST method to notify qemu of failed hot-add. Write-only. +Memory Dimm _PS3 power-off initiated by OSPM (IO port 0xafa4, 1-byte access): +--------------------------------------------------------------- +Dimm hot-add _PS3 initiated by OSPM. Byte value indicates Dimm slot which +entered D3 state. + +Written by ACPI memory device _PS3 method to notify qemu of power-off state for +the dimm. Write-only. diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 8bf58a6..aad78ca 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -52,6 +52,7 @@ #define MEM_OST_REMOVE_FAIL 0xafa1 #define MEM_OST_ADD_SUCCESS 0xafa2 #define MEM_OST_ADD_FAIL 0xafa3 +#define MEM_PS3 0xafa4 #define PIIX4_MEM_HOTPLUG_STATUS 8 #define PIIX4_PCI_HOTPLUG_STATUS 2 @@ -545,6 +546,9 @@ static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) case MEM_OST_ADD_FAIL: dimm_notify(val, DIMM_ADD_FAIL); break; + case MEM_PS3: + dimm_notify(val, DIMM_OSPM_POWEROFF); + break; default: acpi_gpe_ioport_writeb(&s->ar, addr, val); } @@ -621,6 +625,7 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) register_ioport_write(MEM_OST_REMOVE_FAIL, 1, 1, gpe_writeb, s); register_ioport_write(MEM_OST_ADD_SUCCESS, 1, 1, gpe_writeb, s); register_ioport_write(MEM_OST_ADD_FAIL, 1, 1, gpe_writeb, s); + register_ioport_write(MEM_PS3, 1, 1, gpe_writeb, s); for(i = 0; i < DIMM_BITMAP_BYTES; i++) { s->gperegs.mems_sts[i] = 0; diff --git a/hw/dimm.c b/hw/dimm.c index b993668..08f66d5 100644 --- a/hw/dimm.c +++ b/hw/dimm.c @@ -319,6 +319,9 @@ void dimm_notify(uint32_t idx, uint32_t event) qdev_simple_unplug_cb((DeviceState*)s); QTAILQ_INSERT_TAIL(&bus->dimm_hp_result_queue, result, next); break; + case DIMM_OSPM_POWEROFF: + if (bus->dimm_revert) + bus->dimm_revert(bus->dimm_hotplug_qdev, s, 1); default: g_free(result); break; diff --git a/hw/dimm.h b/hw/dimm.h index ce091fe..8d73b8f 100644 --- a/hw/dimm.h +++ b/hw/dimm.h @@ -15,7 +15,8 @@ typedef enum { DIMM_REMOVE_SUCCESS = 0, DIMM_REMOVE_FAIL = 1, DIMM_ADD_SUCCESS = 2, - DIMM_ADD_FAIL = 3 + DIMM_ADD_FAIL = 3, + DIMM_OSPM_POWEROFF = 4 } dimm_hp_result_code; typedef enum { -- 1.7.9

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[RFC PATCH v3 17/19] Implement _PS3 method for memory device
by Vasilis Liaskovitis 21 Sep '12

21 Sep '12

Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- src/acpi-dsdt.dsl | 15 +++++++++++++++ src/ssdt-mem.dsl | 4 ++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index 0d37bbc..8a18770 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -784,6 +784,13 @@ DefinitionBlock ( MIF, 8 } + /* Memory _PS3 byte */ + OperationRegion(MPSB, SystemIO, 0xafa4, 1) + Field (MPSB, ByteAcc, NoLock, Preserve) + { + MPS, 8 + } + Method(MESC, 0) { // Local5 = active memdevice bitmap Store (MES, Local5) @@ -824,6 +831,14 @@ DefinitionBlock ( Store(Arg0, MPE) Sleep(200) } + + Method (MPS3, 1, NotSerialized) { + // _PS3 method - power-off method + Store(Arg0, MPS) + Store(Zero, Index(MEON, Arg0)) + Sleep(200) + } + Method (MOST, 3, Serialized) { // _OST method - OS status indication Switch (And(Arg0, 0xFF)) { diff --git a/src/ssdt-mem.dsl b/src/ssdt-mem.dsl index 041d301..7423fc6 100644 --- a/src/ssdt-mem.dsl +++ b/src/ssdt-mem.dsl @@ -39,6 +39,7 @@ DefinitionBlock ("ssdt-mem.aml", "SSDT", 0x02, "BXPC", "CSSDT", 0x1) External(CMST, MethodObj) External(MPEJ, MethodObj) External(MOST, MethodObj) + External(MPS3, MethodObj) Name(_CRS, ResourceTemplate() { QwordMemory( @@ -64,6 +65,9 @@ DefinitionBlock ("ssdt-mem.aml", "SSDT", 0x02, "BXPC", "CSSDT", 0x1) Method (_OST, 3) { MOST(Arg0, Arg1, ID) } + Method (_PS3, 0) { + MPS3(ID) + } } } -- 1.7.9

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