SeaBIOS

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Re: [SeaBIOS] [RFC PATCH v3 06/19] Implement "-dimm" command line option
by Blue Swirl 29 Sep '12

29 Sep '12

On Mon, Sep 24, 2012 at 10:42 AM, Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> wrote: > On Sat, Sep 22, 2012 at 01:46:57PM +0000, Blue Swirl wrote: >> On Fri, Sep 21, 2012 at 11:17 AM, Vasilis Liaskovitis >> <vasilis.liaskovitis(a)profitbricks.com> wrote: >> > Example: >> > "-dimm id=dimm0,size=512M,node=0,populated=off" >> >> There should not be a need to introduce a new top level option, >> instead you should just use -device, like >> -device dimm,base=0,id=dimm0,size=512M,node=0,populated=off >> >> That would also specify the start address. > > What is "base"? the start address? I think the start address should be calculated by the > chipset / board, not by the user. Yes. > > The "-dimm" option is supposed to specify the dimm/memory layout, and not create > any devices. > > If we don't want this new option, I have a question: > > A "-device/device_add" means we create a new qdev device at startup or as a > hotplug operation respectively. So, the semantics of > "-device dimm,id=dimm0,size=512M,node=0,populated=on" are clear to me. > > What does "-device dimm,populated=off" mean from a qdev perspective? There are 2 > alternatives: > > - The device is created on the dimmbus, but is not used/populated yet. Than the > activation/acpi-hotplug of the dimm may require a separate command (we used to have > "dimm_add" in versions < 3). "device_add" handling always hotplugs a new qdev > device, so this wouldn't fit this usecase, because the device already exists. In > this case, the actual "acpi hotplug" operation is decoupled from qdev device > creation. The bus exists but the devices do not, device_add would add DIMMs to the bus. This matches PCI bus created by the host bridge and PCI device hotplug. A more complex setup would be dimm bus, dimm slot devices and DIMM devices. The intermediate slot device would contain one DIMM device if plugged. > > - The dimmdevice is not created when "-device dimm,populated=off" (this would > require some ugly checking in normal -device argument handling). Only the dimm > layout is saved. The hotplug is triggered from a normal device_add later. So in > this case, the "acpi hotplug" happens at the same time as the qdev hotplug. > > Do you see a simpler alternative without introducing a new option? > > Using the "-dimm" option follows the second semantic and avoids changing the "-device" > semantics. Dimm layout description is decoupled from dimmdevice creation, and qdev > hotplug coincides with acpi hotplug. Maybe even the dimmbus device shouldn't exist by itself after all, or it should be pretty much invisible to users. On real HW, the memory controller or south bridge handles the memory. For i440fx, it's part of the same chipset. So I think we should just add qdev properties to i440fx to specify the sizes, nodes etc. Then i440fx should create the dimmbus device unconditionally using the properties. The default properties should create a sane configuration, otherwise -global i440fx.dimm_size=512M etc. could be used. Then the bus would be populated as before or with device_add. > > thanks, > > - Vasilis

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Re: [SeaBIOS] GeodeVGA global variable access
by Christian Gmeiner 28 Sep '12

28 Sep '12

ping --- Christian Gmeiner, MSc 2012/9/17 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > everything works - feel free to commit :) > > Will rework my patches (VESA support and Flat Panel Support) and hope > to send them during this > week. Finally I will look into EDID. > --- > Christian Gmeiner, MSc > > > 2012/9/16 Christian Gmeiner <christian.gmeiner(a)gmail.com>: >> looks... fine... will comile it tomorrow in the office >> >> --- >> Christian Gmeiner, MSc >> >> >> 2012/9/16 Kevin O'Connor <kevin(a)koconnor.net>: >>> Hi Christian, >>> >>> I just noticed that a recent Geode patch introduced global variables >>> that are accessed without GET_GLOBAL/SET_VGA macros. This will cause >>> random memory corruption. Please see the patch below. >>> >>> -Kevin >>> >>> >>> From ef7f73fa23e42953932920d39f729df82605b2a8 Mon Sep 17 00:00:00 2001 >>> From: Kevin O'Connor <kevin(a)koconnor.net> >>> Date: Sun, 16 Sep 2012 13:24:30 -0400 >>> Subject: [PATCH] geodevga: Access global variables using GET_GLOBAL/SET_VGA >>> macros. >>> To: seabios(a)seabios.org >>> >>> The vgabios runs in 16bit mode so all global variables must be >>> accessed via macros. >>> >>> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> >>> --- >>> vgasrc/geodevga.c | 76 ++++++++++++++++++++++++++++--------------------------- >>> 1 file changed, 39 insertions(+), 37 deletions(-) >>> >>> diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c >>> index ed41be6..cf1382d 100644 >>> --- a/vgasrc/geodevga.c >>> +++ b/vgasrc/geodevga.c >>> @@ -86,55 +86,58 @@ static void geode_mem_mask(u32 addr, u32 off, u32 or) >>> ); >>> } >>> >>> -/**************************************************************** >>> - * Helper functions >>> - ****************************************************************/ >>> - >>> -struct geode { >>> - u32 fb; >>> - u32 dc; >>> - u32 vp; >>> -}; >>> -struct geode geode VAR16; >>> +static u32 GeodeFB VAR16; >>> +static u32 GeodeDC VAR16; >>> +static u32 GeodeVP VAR16; >>> >>> static u32 geode_dc_read(int reg) >>> { >>> - u32 val = geode_mem_read(geode.dc + reg); >>> - dprintf(4, "%s(0x%08x) = 0x%08x\n", __func__, geode.dc + reg, val); >>> + u32 val = geode_mem_read(GET_GLOBAL(GeodeDC) + reg); >>> + dprintf(4, "%s(0x%08x) = 0x%08x\n" >>> + , __func__, GET_GLOBAL(GeodeDC) + reg, val); >>> return val; >>> } >>> >>> static void geode_dc_write(int reg, u32 val) >>> { >>> - dprintf(4, "%s(0x%08x, 0x%08x)\n", __func__, geode.dc + reg, val); >>> - geode_mem_mask(geode.dc + reg, ~0, val); >>> + dprintf(4, "%s(0x%08x, 0x%08x)\n" >>> + , __func__, GET_GLOBAL(GeodeDC) + reg, val); >>> + geode_mem_mask(GET_GLOBAL(GeodeDC) + reg, ~0, val); >>> } >>> >>> static void geode_dc_mask(int reg, u32 off, u32 on) >>> { >>> - dprintf(4, "%s(0x%08x, 0x%08x, 0x%08x)\n", __func__, geode.dc + reg, off, on); >>> - geode_mem_mask(geode.dc + reg, off, on); >>> + dprintf(4, "%s(0x%08x, 0x%08x, 0x%08x)\n" >>> + , __func__, GET_GLOBAL(GeodeDC) + reg, off, on); >>> + geode_mem_mask(GET_GLOBAL(GeodeDC) + reg, off, on); >>> } >>> >>> static u32 geode_vp_read(int reg) >>> { >>> - u32 val = geode_mem_read(geode.vp + reg); >>> - dprintf(4, "%s(0x%08x) = 0x%08x\n", __func__, geode.vp + reg, val); >>> + u32 val = geode_mem_read(GET_GLOBAL(GeodeVP) + reg); >>> + dprintf(4, "%s(0x%08x) = 0x%08x\n" >>> + , __func__, GET_GLOBAL(GeodeVP) + reg, val); >>> return val; >>> } >>> >>> static void geode_vp_write(int reg, u32 val) >>> { >>> - dprintf(4, "%s(0x%08x, 0x%08x)\n", __func__, geode.vp + reg, val); >>> - geode_mem_mask(geode.vp + reg, ~0, val); >>> + dprintf(4, "%s(0x%08x, 0x%08x)\n" >>> + , __func__, GET_GLOBAL(GeodeVP) + reg, val); >>> + geode_mem_mask(GET_GLOBAL(GeodeVP) + reg, ~0, val); >>> } >>> >>> static void geode_vp_mask(int reg, u32 off, u32 on) >>> { >>> - dprintf(4, "%s(0x%08x, 0x%08x, 0x%08x)\n", __func__, geode.vp + reg, off, on); >>> - geode_mem_mask(geode.vp + reg, off, on); >>> + dprintf(4, "%s(0x%08x, 0x%08x, 0x%08x)\n" >>> + , __func__, GET_GLOBAL(GeodeVP) + reg, off, on); >>> + geode_mem_mask(GET_GLOBAL(GeodeVP) + reg, off, on); >>> } >>> >>> +/**************************************************************** >>> + * Helper functions >>> + ****************************************************************/ >>> + >>> static int legacyio_check(void) >>> { >>> int ret=0; >>> @@ -199,10 +202,9 @@ static void dc_setup(void) >>> geode_dc_write(DC_CURS_ST_OFFSET, 0x0); >>> >>> /* read fb-bar from pci, then point dc to the fb base */ >>> - u32 dc_fb = geode_dc_read(DC_GLIU0_MEM_OFFSET); >>> - if (geode.fb != dc_fb) { >>> - geode_dc_write(DC_GLIU0_MEM_OFFSET, geode.fb); >>> - } >>> + u32 fb = GET_GLOBAL(GeodeFB); >>> + if (geode_dc_read(DC_GLIU0_MEM_OFFSET) != fb) >>> + geode_dc_write(DC_GLIU0_MEM_OFFSET, fb); >>> >>> geode_dc_mask(DC_DISPLAY_CFG, ~DC_CFG_MSK, DC_GDEN|DC_TRUP); >>> geode_dc_write(DC_GENERAL_CFG, DC_VGAE); >>> @@ -210,10 +212,10 @@ static void dc_setup(void) >>> geode_dc_write(DC_UNLOCK, DC_LOCK_LOCK); >>> >>> u32 fb_size = framebuffer_size(); // in byte >>> - dprintf(1, "%d KB of video memory at 0x%08x\n", fb_size / 1024, geode.fb); >>> + dprintf(1, "%d KB of video memory at 0x%08x\n", fb_size / 1024, fb); >>> >>> /* update VBE variables */ >>> - SET_VGA(VBE_framebuffer, geode.fb); >>> + SET_VGA(VBE_framebuffer, fb); >>> SET_VGA(VBE_total_memory, fb_size / 1024 / 64); // number of 64K blocks >>> } >>> >>> @@ -335,16 +337,16 @@ int geodevga_init(void) >>> if (GET_GLOBAL(VgaBDF) < 0) >>> // Device should be at 00:01.1 >>> SET_VGA(VgaBDF, pci_to_bdf(0, 1, 1)); >>> - >>> + >>> // setup geode struct which is used for register access >>> - geode.fb = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0); >>> - geode.dc = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_2); >>> - geode.vp = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3); >>> - >>> - dprintf(1, "fb addr: 0x%08x\n", geode.fb); >>> - dprintf(1, "dc addr: 0x%08x\n", geode.dc); >>> - dprintf(1, "vp addr: 0x%08x\n", geode.vp); >>> - >>> + SET_VGA(GeodeFB, pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)); >>> + SET_VGA(GeodeDC, pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_2)); >>> + SET_VGA(GeodeVP, pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3)); >>> + >>> + dprintf(1, "fb addr: 0x%08x\n", GET_GLOBAL(GeodeFB)); >>> + dprintf(1, "dc addr: 0x%08x\n", GET_GLOBAL(GeodeDC)); >>> + dprintf(1, "vp addr: 0x%08x\n", GET_GLOBAL(GeodeVP)); >>> + >>> vp_setup(); >>> dc_setup(); >>> >>> -- >>> 1.7.11.4 >>>

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Re: [SeaBIOS] [RFC PATCH v3 09/19] pc: Add dimm paravirt SRAT info
by Wen Congyang 27 Sep '12

27 Sep '12

At 09/21/2012 07:17 PM, Vasilis Liaskovitis Wrote: > The numa_fw_cfg paravirt interface is extended to include SRAT information for > all hotplug-able dimms. There are 3 words for each hotplug-able memory slot, > denoting start address, size and node proximity. The new info is appended after > existing numa info, so that the fw_cfg layout does not break. This information > is used by Seabios to build hotplug memory device objects at runtime. > nb_numa_nodes is set to 1 by default (not 0), so that we always pass srat info > to SeaBIOS. You forgot to set nb_numa_nodes to 1... Thanks Wen Congyang > > v1->v2: > Dimm SRAT info (#dimms) is appended at end of existing numa fw_cfg in order not > to break existing layout > Documentation of the new fwcfg layout is included in docs/specs/fwcfg.txt > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > docs/specs/fwcfg.txt | 28 ++++++++++++++++++++++++++++ > hw/pc.c | 14 ++++++++++++-- > 2 files changed, 40 insertions(+), 2 deletions(-) > create mode 100644 docs/specs/fwcfg.txt > > diff --git a/docs/specs/fwcfg.txt b/docs/specs/fwcfg.txt > new file mode 100644 > index 0000000..55f96d9 > --- /dev/null > +++ b/docs/specs/fwcfg.txt > @@ -0,0 +1,28 @@ > +QEMU<->BIOS Paravirt Documentation > +-------------------------------------- > + > +This document describes paravirt data structures passed from QEMU to BIOS. > + > +FW_CFG_NUMA paravirt info > +-------------------- > +The SRAT info passed from QEMU to BIOS has the following layout: > + > +----------------------------------------------------------------------------------------------- > +#nodes | cpu0_pxm | cpu1_pxm | ... | cpulast_pxm | node0_mem | node1_mem | ... | nodelast_mem > + > +----------------------------------------------------------------------------------------------- > +#dimms | dimm0_start | dimm0_sz | dimm0_pxm | ... | dimmlast_start | dimmlast_sz | dimmlast_pxm > + > +Entry 0 contains the number of numa nodes (nb_numa_nodes). > + > +Entries 1..max_cpus: The next max_cpus entries describe node proximity for each > +one of the vCPUs in the system. > + > +Entries max_cpus+1..max_cpus+nb_numa_nodes+1: The next nb_numa_nodes entries > +describe the memory size for each one of the NUMA nodes in the system. > + > +Entry max_cpus+nb_numa_nodes+1 contains the number of memory dimms (nb_hp_dimms) > + > +The last 3 * nb_hp_dimms entries are organized in triplets: Each triplet contains > +the physical address offset, size (in bytes), and node proximity for the > +respective dimm. > diff --git a/hw/pc.c b/hw/pc.c > index 2c9664d..f2604ae 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -598,6 +598,7 @@ static void *bochs_bios_init(void) > uint8_t *smbios_table; > size_t smbios_len; > uint64_t *numa_fw_cfg; > + uint64_t *hp_dimms_fw_cfg; > int i, j; > > register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); > @@ -632,8 +633,10 @@ static void *bochs_bios_init(void) > /* allocate memory for the NUMA channel: one (64bit) word for the number > * of nodes, one word for each VCPU->node and one word for each node to > * hold the amount of memory. > + * Finally one word for the number of hotplug memory slots and three words > + * for each hotplug memory slot (start address, size and node proximity). > */ > - numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); > + numa_fw_cfg = g_malloc0((2 + max_cpus + nb_numa_nodes + 3 * nb_hp_dimms) * 8); > numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); > for (i = 0; i < max_cpus; i++) { > for (j = 0; j < nb_numa_nodes; j++) { > @@ -646,8 +649,15 @@ static void *bochs_bios_init(void) > for (i = 0; i < nb_numa_nodes; i++) { > numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); > } > + > + numa_fw_cfg[1 + max_cpus + nb_numa_nodes] = cpu_to_le64(nb_hp_dimms); > + > + hp_dimms_fw_cfg = numa_fw_cfg + 2 + max_cpus + nb_numa_nodes; > + if (nb_hp_dimms) > + setup_fwcfg_hp_dimms(hp_dimms_fw_cfg); > + > fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, > - (1 + max_cpus + nb_numa_nodes) * 8); > + (2 + max_cpus + nb_numa_nodes + 3 * nb_hp_dimms) * 8); > > return fw_cfg; > }

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Re: [SeaBIOS] [RFC PATCH v3 08/19] pc: calculate dimm physical addresses and adjust memory map
by Vasilis Liaskovitis 24 Sep '12

24 Sep '12

On Sat, Sep 22, 2012 at 02:15:28PM +0000, Blue Swirl wrote: > > + > > +/* Function to configure memory offsets of hotpluggable dimms */ > > + > > +target_phys_addr_t pc_set_hp_memory_offset(uint64_t size) > > +{ > > + target_phys_addr_t ret; > > + > > + /* on first call, initialize ram_hp_offset */ > > + if (!ram_hp_offset) { > > + if (ram_size >= PCI_HOLE_START ) { > > + ram_hp_offset = 0x100000000LL + (ram_size - PCI_HOLE_START); > > + } else { > > + ram_hp_offset = ram_size; > > + } > > + } > > + > > + if (ram_hp_offset >= 0x100000000LL) { > > + ret = ram_hp_offset; > > + above_4g_hp_mem_size += size; > > + ram_hp_offset += size; > > + } > > + /* if dimm fits before pci hole, append it normally */ > > + else if (ram_hp_offset + size <= PCI_HOLE_START) { > > } else if ... > > > + ret = ram_hp_offset; > > + below_4g_hp_mem_size += size; > > + ram_hp_offset += size; > > + } > > + /* otherwise place it above 4GB */ > > + else { > > } else { > > > + ret = 0x100000000LL; > > + above_4g_hp_mem_size += size; > > + ram_hp_offset = 0x100000000LL + size; > > + } > > + > > + return ret; > > +} > > But the function and use of lots of global variables is ugly. The dimm > devices should be just created in piix_pci.c (i440fx) directly with > correct offsets and sizes, so all below_4g_mem_size etc. calculations > should be moved there. That would implement the PMC part of i440fx. > > For ISA PC, probably the board should create the DIMMs since there may > not be a memory controller. The >4G logic does not make sense there > anyway. What about moving the implementation to pc_piix.c? Initial RAM and pci windows are already calculated in pc_init1, and then passed to i440fx_init. The memory bus could be attached to i440fx for pci-enabled pc and to isabus-bridge for isa-pc (isa-pc not tested yet). Something like the following: --- hw/pc.h | 1 + hw/pc_piix.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/hw/pc.h b/hw/pc.h index e4db071..d6cc43b 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -10,6 +10,7 @@ #include "memory.h" #include "ioapic.h" +#define PCI_HOLE_START 0xe0000000 /* PC-style peripherals (also used by other machines). */ /* serial.c */ diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 88ff041..17db95a 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -43,6 +43,7 @@ #include "xen.h" #include "memory.h" #include "exec-memory.h" +#include "dimm.h" #ifdef CONFIG_XEN # include <xen/hvm/hvm_info_table.h> #endif @@ -52,6 +53,8 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; +static ram_addr_t below_4g_hp_mem_size = 0; +static ram_addr_t above_4g_hp_mem_size = 0; static void kvm_piix3_setup_irq_routing(bool pci_enabled) { @@ -117,6 +120,41 @@ static void ioapic_init(GSIState *gsi_state) } } +static target_phys_addr_t pc_set_hp_memory_offset(uint64_t size) +{ + target_phys_addr_t ret; + static ram_addr_t ram_hp_offset = 0; + + /* on first call, initialize ram_hp_offset */ + if (!ram_hp_offset) { + if (ram_size >= PCI_HOLE_START ) { + ram_hp_offset = 0x100000000LL + (ram_size - PCI_HOLE_START); + } else { + ram_hp_offset = ram_size; + } + } + + if (ram_hp_offset >= 0x100000000LL) { + ret = ram_hp_offset; + above_4g_hp_mem_size += size; + ram_hp_offset += size; + } + /* if dimm fits before pci hole, append it normally */ + else if (ram_hp_offset + size <= PCI_HOLE_START) { + ret = ram_hp_offset; + below_4g_hp_mem_size += size; + ram_hp_offset += size; + } + /* otherwise place it above 4GB */ + else { + ret = 0x100000000LL; + above_4g_hp_mem_size += size; + ram_hp_offset = 0x100000000LL + size; + } + + return ret; +} + /* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *system_io, @@ -155,9 +193,9 @@ static void pc_init1(MemoryRegion *system_memory, kvmclock_create(); } - if (ram_size >= 0xe0000000 ) { - above_4g_mem_size = ram_size - 0xe0000000; - below_4g_mem_size = 0xe0000000; + if (ram_size >= PCI_HOLE_START ) { + above_4g_mem_size = ram_size - PCI_HOLE_START; + below_4g_mem_size = PCI_HOLE_START; } else { above_4g_mem_size = 0; below_4g_mem_size = ram_size; @@ -172,6 +210,9 @@ static void pc_init1(MemoryRegion *system_memory, rom_memory = system_memory; } + /* adjust memory map for hotplug dimms */ + dimm_calc_offsets(pc_set_hp_memory_offset); + /* allocate ram and load rom/bios */ if (!xen_enabled()) { fw_cfg = pc_memory_init(system_memory, @@ -192,18 +233,22 @@ static void pc_init1(MemoryRegion *system_memory, if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, system_memory, system_io, ram_size, - below_4g_mem_size, - 0x100000000ULL - below_4g_mem_size, - 0x100000000ULL + above_4g_mem_size, + below_4g_mem_size + below_4g_hp_mem_size, + 0x100000000ULL - below_4g_mem_size + - below_4g_hp_mem_size, + 0x100000000ULL + above_4g_mem_size + + above_4g_hp_mem_size, (sizeof(target_phys_addr_t) == 4 ? 0 : ((uint64_t)1 << 62)), pci_memory, ram_memory); + main_memory_bus_create(object_resolve_path("i440fx", NULL)); } else { pci_bus = NULL; i440fx_state = NULL; isa_bus = isa_bus_new(NULL, system_io); no_hpet = 1; + main_memory_bus_create(object_resolve_path("isabus-bridge", NULL)); } isa_bus_irqs(isa_bus, gsi); -- 1.7.9

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Re: [SeaBIOS] [RFC PATCH v3 11/19] Implement qmp and hmp commands for notification lists
by Eric Blake 24 Sep '12

24 Sep '12

On 09/21/2012 05:17 AM, Vasilis Liaskovitis wrote: > Guest can respond to ACPI hotplug events e.g. with _EJ or _OST method. > This patch implements a tail queue to store guest notifications for memory > hot-add and hot-remove requests. > > Guest responses for memory hotplug command on a per-dimm basis can be detected > with the new hmp command "info memhp" or the new qmp command "query-memhp" Naming doesn't match the QMP code. > Examples: > > (qemu) device_add dimm,id=ram0 > > These notification items should probably be part of migration state (not yet > implemented). In the case of libvirt driving migration, you already said in 10/19 that libvirt has to start the destination with the populated=on|off fields correct for each dimm according to the state it was in at the time the host started the update. Can the host hot unplug memory after migration has started? > + > +## > +# @MemHpInfo: > +# > +# Information about status of a memory hotplug command > +# > +# @dimm: the Dimm associated with the result > +# > +# @result: the result of the hotplug command > +# > +# Since: 1.3 > +# > +## > +{ 'type': 'MemHpInfo', > + 'data': {'dimm': 'str', 'request': 'str', 'result': 'str'} } Should 'result' be a bool (true for success, false for still pending) or an enum, instead of a free-form string? Likewise, isn't 'request' going to be exactly one of two values (plug or unplug)? -- Eric Blake eblake(a)redhat.com +1-919-301-3266 Libvirt virtualization library http://libvirt.org

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Re: [SeaBIOS] [RFC PATCH v3 20/19] alternative: Use paravirt interface for pci windows
by Wen Congyang 24 Sep '12

24 Sep '12

At 09/21/2012 07:20 PM, Vasilis Liaskovitis Wrote: > Initialize the 32-bit and 64-bit pci starting offsets from values passed in by > the qemu paravirt interface QEMU_CFG_PCI_WINDOW. Qemu calculates the starting > offsets based on initial memory and hotplug-able dimms. This patch can't be applied if I apply the other patches for seabios. And I don't find this patch in your tree. Thanks Wen Congyang > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > src/paravirt.c | 6 ++++++ > src/paravirt.h | 2 ++ > src/pciinit.c | 5 ++--- > 3 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/src/paravirt.c b/src/paravirt.c > index 2a98d53..390ef30 100644 > --- a/src/paravirt.c > +++ b/src/paravirt.c > @@ -346,3 +346,9 @@ void qemu_cfg_romfile_setup(void) > dprintf(3, "Found fw_cfg file: %s (size=%d)\n", file->name, file->size); > } > } > + > +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start) > +{ > + qemu_cfg_read_entry(pcimem_start, QEMU_CFG_PCI_WINDOW, sizeof(u64)); > + qemu_cfg_read((u8*)(pcimem64_start), sizeof(u64)); > +} > diff --git a/src/paravirt.h b/src/paravirt.h > index a284c41..b53ff88 100644 > --- a/src/paravirt.h > +++ b/src/paravirt.h > @@ -35,6 +35,7 @@ static inline int kvm_para_available(void) > #define QEMU_CFG_BOOT_MENU 0x0e > #define QEMU_CFG_MAX_CPUS 0x0f > #define QEMU_CFG_FILE_DIR 0x19 > +#define QEMU_CFG_PCI_WINDOW 0x1a > #define QEMU_CFG_ARCH_LOCAL 0x8000 > #define QEMU_CFG_ACPI_TABLES (QEMU_CFG_ARCH_LOCAL + 0) > #define QEMU_CFG_SMBIOS_ENTRIES (QEMU_CFG_ARCH_LOCAL + 1) > @@ -65,5 +66,6 @@ struct e820_reservation { > u32 qemu_cfg_e820_entries(void); > void* qemu_cfg_e820_load_next(void *addr); > void qemu_cfg_romfile_setup(void); > +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start); > > #endif > diff --git a/src/pciinit.c b/src/pciinit.c > index 68f302a..64468a0 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -592,8 +592,7 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) > > static void pci_bios_map_devices(struct pci_bus *busses) > { > - pcimem_start = RamSize; > - > + qemu_cfg_get_pci_offsets(&pcimem_start, &pcimem64_start); > if (pci_bios_init_root_regions(busses)) { > struct pci_region r64_mem, r64_pref; > r64_mem.list = NULL; > @@ -611,7 +610,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) > u64 align_mem = pci_region_align(&r64_mem); > u64 align_pref = pci_region_align(&r64_pref); > > - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); > + r64_mem.base = ALIGN(pcimem64_start, align_mem); > r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); > pcimem64_start = r64_mem.base; > pcimem64_end = r64_pref.base + sum_pref;

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Re: [SeaBIOS] [RFC PATCH v3 06/19] Implement "-dimm" command line option
by Vasilis Liaskovitis 24 Sep '12

24 Sep '12

On Sat, Sep 22, 2012 at 01:46:57PM +0000, Blue Swirl wrote: > On Fri, Sep 21, 2012 at 11:17 AM, Vasilis Liaskovitis > <vasilis.liaskovitis(a)profitbricks.com> wrote: > > Example: > > "-dimm id=dimm0,size=512M,node=0,populated=off" > > There should not be a need to introduce a new top level option, > instead you should just use -device, like > -device dimm,base=0,id=dimm0,size=512M,node=0,populated=off > > That would also specify the start address. What is "base"? the start address? I think the start address should be calculated by the chipset / board, not by the user. The "-dimm" option is supposed to specify the dimm/memory layout, and not create any devices. If we don't want this new option, I have a question: A "-device/device_add" means we create a new qdev device at startup or as a hotplug operation respectively. So, the semantics of "-device dimm,id=dimm0,size=512M,node=0,populated=on" are clear to me. What does "-device dimm,populated=off" mean from a qdev perspective? There are 2 alternatives: - The device is created on the dimmbus, but is not used/populated yet. Than the activation/acpi-hotplug of the dimm may require a separate command (we used to have "dimm_add" in versions < 3). "device_add" handling always hotplugs a new qdev device, so this wouldn't fit this usecase, because the device already exists. In this case, the actual "acpi hotplug" operation is decoupled from qdev device creation. - The dimmdevice is not created when "-device dimm,populated=off" (this would require some ugly checking in normal -device argument handling). Only the dimm layout is saved. The hotplug is triggered from a normal device_add later. So in this case, the "acpi hotplug" happens at the same time as the qdev hotplug. Do you see a simpler alternative without introducing a new option? Using the "-dimm" option follows the second semantic and avoids changing the "-device" semantics. Dimm layout description is decoupled from dimmdevice creation, and qdev hotplug coincides with acpi hotplug. thanks, - Vasilis

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Re: [SeaBIOS] [RFC PATCH v3 19/19] Calculate pcimem_start and pcimem64_start from SRAT entries
by Wen Congyang 24 Sep '12

24 Sep '12

At 09/21/2012 07:17 PM, Vasilis Liaskovitis Wrote: > pcimem_start and pcimem64_start are adjusted from srat entries. For this reason, > paravirt info (NUMA SRAT entries and number of cpus) need to be read before pci_setup. > Imho, this is an ugly code change since SRAT bios tables and number of > cpus have to be read earlier. But the advantage is that no new paravirt interface > is introduced. Suggestions to make the code change cleaner are welcome. > > The alternative patch (will be sent as a reply to this patch) implements a > paravirt interface to read the starting values of pcimem_start and > pcimem64_start from QEMU. > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > src/acpi.c | 82 ++++++++++++++++++++++++++++++++++++++++---------------- > src/acpi.h | 3 ++ > src/pciinit.c | 6 +++- > src/post.c | 3 ++ > src/smp.c | 4 +++ > 5 files changed, 72 insertions(+), 26 deletions(-) > > diff --git a/src/acpi.c b/src/acpi.c > index 1223b52..9e99aa7 100644 > --- a/src/acpi.c > +++ b/src/acpi.c > @@ -428,7 +428,10 @@ encodeLen(u8 *ssdt_ptr, int length, int bytes) > #define MEM_OFFSET_END 63 > #define MEM_OFFSET_SIZE 79 > > -u64 nb_hp_memslots = 0; > +u64 nb_hp_memslots = 0, nb_numanodes; > +u64 *numa_data, *hp_memdata; > +u64 below_4g_hp_mem_size = 0; > +u64 above_4g_hp_mem_size = 0; > struct srat_memory_affinity *mem; > > #define SSDT_SIGNATURE 0x54445353 // SSDT > @@ -763,17 +766,7 @@ acpi_build_srat_memory(struct srat_memory_affinity *numamem, > static void * > build_srat(void) > { > - int nb_numa_nodes = qemu_cfg_get_numa_nodes(); > - > - u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes)); > - if (!numadata) { > - warn_noalloc(); > - return NULL; > - } > - > - qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes); > - > - qemu_cfg_get_numa_data(&nb_hp_memslots, 1); > + int nb_numa_nodes = nb_numanodes; > struct system_resource_affinity_table *srat; > int srat_size = sizeof(*srat) + > sizeof(struct srat_processor_affinity) * MaxCountCPUs + > @@ -782,7 +775,7 @@ build_srat(void) > srat = malloc_high(srat_size); > if (!srat) { > warn_noalloc(); > - free(numadata); > + free(numa_data); > return NULL; > } > > @@ -791,6 +784,7 @@ build_srat(void) > struct srat_processor_affinity *core = (void*)(srat + 1); > int i; > u64 curnode; > + u64 *numadata = numa_data; > > for (i = 0; i < MaxCountCPUs; ++i) { > core->type = SRAT_PROCESSOR; > @@ -847,15 +841,7 @@ build_srat(void) > mem = (void*)numamem; > > if (nb_hp_memslots) { > - u64 *hpmemdata = malloc_tmphigh(sizeof(u64) * (3 * nb_hp_memslots)); > - if (!hpmemdata) { > - warn_noalloc(); > - free(hpmemdata); > - free(numadata); > - return NULL; > - } > - > - qemu_cfg_get_numa_data(hpmemdata, 3 * nb_hp_memslots); > + u64 *hpmemdata = hp_memdata; > > for (i = 1; i < nb_hp_memslots + 1; ++i) { > mem_base = *hpmemdata++; > @@ -865,7 +851,7 @@ build_srat(void) > numamem++; > slots++; > } > - free(hpmemdata); > + free(hp_memdata); > } > > for (; slots < nb_numa_nodes + nb_hp_memslots + 2; slots++) { > @@ -875,10 +861,58 @@ build_srat(void) > > build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1); > > - free(numadata); > + free(numa_data); > return srat; > } > > +/* QEMU paravirt SRAT entries need to be read in before pci initilization */ > +void read_srat_early(void) > +{ > + int i; > + > + nb_numanodes = qemu_cfg_get_numa_nodes(); > + u64 *hpmemdata; > + u64 mem_len, mem_base; > + > + numa_data = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numanodes)); > + if (!numa_data) { > + warn_noalloc(); > + } > + > + qemu_cfg_get_numa_data(numa_data, MaxCountCPUs + nb_numanodes); > + qemu_cfg_get_numa_data(&nb_hp_memslots, 1); > + > + if (nb_hp_memslots) { > + hp_memdata = malloc_tmphigh(sizeof(u64) * (3 * nb_hp_memslots)); > + if (!hp_memdata) { > + warn_noalloc(); > + free(hp_memdata); > + free(numa_data); > + } > + > + qemu_cfg_get_numa_data(hp_memdata, 3 * nb_hp_memslots); > + hpmemdata = hp_memdata; > + > + for (i = 1; i < nb_hp_memslots + 1; ++i) { > + mem_base = *hpmemdata++; > + mem_len = *hpmemdata++; > + hpmemdata++; > + if (mem_base >= 0x100000000LL) { > + above_4g_hp_mem_size += mem_len; > + } > + /* if dimm fits before pci hole, append it normally */ > + else if (mem_base + mem_len <= BUILD_PCIMEM_START) { > + below_4g_hp_mem_size += mem_len; > + } > + /* otherwise place it above 4GB */ > + else { > + above_4g_hp_mem_size += mem_len; > + } > + } > + > + } > +} > + > static const struct pci_device_id acpi_find_tbl[] = { > /* PIIX4 Power Management device. */ > PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL), > diff --git a/src/acpi.h b/src/acpi.h > index cb21561..d29837f 100644 > --- a/src/acpi.h > +++ b/src/acpi.h > @@ -5,6 +5,9 @@ > > void acpi_bios_init(void); > u32 find_resume_vector(void); > +void read_srat_early(void); > +extern u64 below_4g_hp_mem_size; > +extern u64 above_4g_hp_mem_size; > > #define RSDP_SIGNATURE 0x2052545020445352LL // "RSD PTR " > > diff --git a/src/pciinit.c b/src/pciinit.c > index 31115ee..c5a4b24 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -12,6 +12,7 @@ > #include "ioport.h" // PORT_ATA1_CMD_BASE > #include "config.h" // CONFIG_* > #include "xen.h" // usingXen > +#include "acpi.h" > > #define PCI_DEVICE_MEM_MIN 0x1000 > #define PCI_BRIDGE_IO_MIN 0x1000 > @@ -597,7 +598,7 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) > > static void pci_bios_map_devices(struct pci_bus *busses) > { > - pcimem_start = RamSize; > + pcimem_start = RamSize + below_4g_hp_mem_size; > > if (pci_bios_init_root_regions(busses)) { > struct pci_region r64_mem, r64_pref; > @@ -616,7 +617,8 @@ static void pci_bios_map_devices(struct pci_bus *busses) > u64 align_mem = pci_region_align(&r64_mem); > u64 align_pref = pci_region_align(&r64_pref); > > - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); > + r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G + > + above_4g_hp_mem_size, align_mem); > r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); > pcimem64_start = r64_mem.base; > pcimem64_end = r64_pref.base + sum_pref; > diff --git a/src/post.c b/src/post.c > index 924b311..c37730b 100644 > --- a/src/post.c > +++ b/src/post.c > @@ -234,6 +234,9 @@ maininit(void) > // Initialize mtrr > mtrr_setup(); > > + smp_get_ncpus(); > + read_srat_early(); > + > // Initialize pci > pci_setup(); > smm_init(); > diff --git a/src/smp.c b/src/smp.c > index 4975412..3922776 100644 > --- a/src/smp.c > +++ b/src/smp.c > @@ -138,7 +138,11 @@ smp_probe(void) > > // Restore memory. > *(u64*)BUILD_AP_BOOT_ADDR = old; > +} > > +void > +smp_get_ncpus(void) You don't declare this function, and use it in another file. It will break building: src/post.c: In function ‘maininit’: src/post.c:237: warning: implicit declaration of function ‘smp_get_ncpus’ src/smp.c:144: note: previous definition of ‘smp_get_ncpus’ was here src/post.c:237: error: incompatible implicit declaration of function ‘smp_get_ncpus’ src/smp.c:144: note: previous definition of ‘smp_get_ncpus’ was here Thanks Wen Congyang > +{ > MaxCountCPUs = qemu_cfg_get_max_cpus(); > if (!MaxCountCPUs || MaxCountCPUs < CountCPUs) > MaxCountCPUs = CountCPUs;

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Re: [SeaBIOS] [RFC PATCH v3 05/19] Implement dimm device abstraction
by Wen Congyang 24 Sep '12

24 Sep '12

At 09/21/2012 07:17 PM, Vasilis Liaskovitis Wrote: > Each hotplug-able memory slot is a DimmDevice. All DimmDevices are attached > to a new bus called DimmBus. This bus is introduced so that we no longer > depend on hotplug-capability of main system bus (the main bus does not allow > hotplugging). The DimmBus should be attached to a chipset Device (i440fx in case > of the pc) > > A hot-add operation for a particular dimm: > - creates a new DimmDevice and attaches it to the DimmBus > - creates a new MemoryRegion of the given physical address offset, size and > node proximity, and attaches it to main system memory as a sub_region. > > A successful hot-remove operation detaches and frees the MemoryRegion from > system memory, and removes the DimmDevice from the DimmBus. > > Hotplug operations are done through normal device_add /device_del commands. > Also add properties to DimmDevice. > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > hw/dimm.c | 305 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > hw/dimm.h | 90 ++++++++++++++++++ > 2 files changed, 395 insertions(+), 0 deletions(-) > create mode 100644 hw/dimm.c > create mode 100644 hw/dimm.h > > diff --git a/hw/dimm.c b/hw/dimm.c > new file mode 100644 > index 0000000..288b997 > --- /dev/null > +++ b/hw/dimm.c > @@ -0,0 +1,305 @@ > +/* > + * Dimm device for Memory Hotplug > + * > + * Copyright ProfitBricks GmbH 2012 > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see <http://www.gnu.org/licenses/> > + */ > + > +#include "trace.h" > +#include "qdev.h" > +#include "dimm.h" > +#include <time.h> > +#include "../exec-memory.h" > +#include "qmp-commands.h" > + > +/* the system-wide memory bus. */ > +static DimmBus *main_memory_bus; > +/* the following list is used to hold dimm config info before machine > + * initialization. After machine init, the list is emptied and not used anymore.*/ > +static DimmConfiglist dimmconfig_list = QTAILQ_HEAD_INITIALIZER(dimmconfig_list); > + > +static void dimmbus_dev_print(Monitor *mon, DeviceState *dev, int indent); > +static char *dimmbus_get_fw_dev_path(DeviceState *dev); > + > +static Property dimm_properties[] = { > + DEFINE_PROP_UINT64("start", DimmDevice, start, 0), > + DEFINE_PROP_UINT64("size", DimmDevice, size, DEFAULT_DIMMSIZE), > + DEFINE_PROP_UINT32("node", DimmDevice, node, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void dimmbus_dev_print(Monitor *mon, DeviceState *dev, int indent) > +{ > +} > + > +static char *dimmbus_get_fw_dev_path(DeviceState *dev) > +{ > + char path[40]; > + > + snprintf(path, sizeof(path), "%s", qdev_fw_name(dev)); > + return strdup(path); > +} > + > +static void dimm_bus_class_init(ObjectClass *klass, void *data) > +{ > + BusClass *k = BUS_CLASS(klass); > + > + k->print_dev = dimmbus_dev_print; > + k->get_fw_dev_path = dimmbus_get_fw_dev_path; > +} > + > +static void dimm_bus_initfn(Object *obj) > +{ > + DimmConfig *dimm_cfg, *next_dimm_cfg; > + DimmBus *bus = DIMM_BUS(obj); > + QTAILQ_INIT(&bus->dimmconfig_list); > + QTAILQ_INIT(&bus->dimmlist); > + > + QTAILQ_FOREACH_SAFE(dimm_cfg, &dimmconfig_list, nextdimmcfg, next_dimm_cfg) { > + QTAILQ_REMOVE(&dimmconfig_list, dimm_cfg, nextdimmcfg); > + QTAILQ_INSERT_TAIL(&bus->dimmconfig_list, dimm_cfg, nextdimmcfg); > + } > +} > + > +static const TypeInfo dimm_bus_info = { > + .name = TYPE_DIMM_BUS, > + .parent = TYPE_BUS, > + .instance_size = sizeof(DimmBus), > + .instance_init = dimm_bus_initfn, > + .class_init = dimm_bus_class_init, > +}; > + > +void main_memory_bus_create(Object *parent) > +{ > + main_memory_bus = g_malloc0(dimm_bus_info.instance_size); > + main_memory_bus->qbus.glib_allocated = true; > + qbus_create_inplace(&main_memory_bus->qbus, TYPE_DIMM_BUS, DEVICE(parent), > + "membus"); > +} > + > +static void dimm_populate(DimmDevice *s) > +{ > + DeviceState *dev= (DeviceState*)s; > + MemoryRegion *new = NULL; > + > + new = g_malloc(sizeof(MemoryRegion)); > + memory_region_init_ram(new, dev->id, s->size); > + vmstate_register_ram_global(new); > + memory_region_add_subregion(get_system_memory(), s->start, new); > + s->mr = new; > +} > + > +static void dimm_depopulate(DimmDevice *s) > +{ > + assert(s); > + vmstate_unregister_ram(s->mr, NULL); > + memory_region_del_subregion(get_system_memory(), s->mr); > + memory_region_destroy(s->mr); > + s->mr = NULL; > +} > + > +void dimm_config_create(char *id, uint64_t size, uint64_t node, uint32_t > + dimm_idx, uint32_t populated) > +{ > + DimmConfig *dimm_cfg; > + dimm_cfg = (DimmConfig*) g_malloc0(sizeof(DimmConfig)); > + dimm_cfg->name = id; > + dimm_cfg->idx = dimm_idx; > + dimm_cfg->start = 0; > + dimm_cfg->size = size; > + dimm_cfg->node = node; > + dimm_cfg->populated = populated; > + > + QTAILQ_INSERT_TAIL(&dimmconfig_list, dimm_cfg, nextdimmcfg); > +} > + > +void dimm_bus_hotplug(dimm_hotplug_fn hotplug, DeviceState *qdev) > +{ > + DimmBus *bus = main_memory_bus; > + bus->qbus.allow_hotplug = 1; > + bus->dimm_hotplug_qdev = qdev; > + bus->dimm_hotplug = hotplug; > +} > + > +static void dimm_plug_device(DimmDevice *slot) > +{ > + DimmBus *bus = main_memory_bus; > + > + dimm_populate(slot); > + if (bus->dimm_hotplug) > + bus->dimm_hotplug(bus->dimm_hotplug_qdev, slot, 1); > +} > + > +static int dimm_unplug_device(DeviceState *qdev) > +{ > + DimmBus *bus = main_memory_bus; > + > + if (bus->dimm_hotplug) > + bus->dimm_hotplug(bus->dimm_hotplug_qdev, DIMM(qdev), 0); > + return 1; > +} > + > +static DimmConfig *dimmcfg_find_from_name(const char *name) > +{ > + DimmConfig *slot; > + DimmBus *bus = main_memory_bus; > + > + QTAILQ_FOREACH(slot, &bus->dimmconfig_list, nextdimmcfg) { > + if (!strcmp(slot->name, name)) { > + return slot; > + } > + } > + return NULL; > +} > + > +static DimmDevice *dimm_find_from_idx(uint32_t idx) > +{ > + DimmDevice *slot; > + DimmBus *bus = main_memory_bus; > + > + QTAILQ_FOREACH(slot, &bus->dimmlist, nextdimm) { > + if (slot->idx == idx) { > + return slot; > + } > + } > + return NULL; > +} > + > +/* used to create a dimm device, only on incoming migration of a hotplugged > + * RAMBlock > + */ > +int dimm_add(char *id) > +{ > + DimmConfig *slotcfg = NULL; > + QemuOpts *devopts; > + char buf[256]; > + > + if (!id) { > + fprintf(stderr, "ERROR %s invalid id\n",__FUNCTION__); > + return 1; > + } > + > + slotcfg = dimmcfg_find_from_name(id); > + > + if (!slotcfg) { > + fprintf(stderr, "%s no slot %s found\n", __FUNCTION__, id); > + return 1; > + } > + > + devopts = qemu_opts_create(qemu_find_opts("device"), id, 0, NULL); > + qemu_opt_set(devopts, "driver", "dimm"); > + > + snprintf(buf, sizeof(buf), "%lu", slotcfg->size); > + qemu_opt_set(devopts, "size", buf); > + snprintf(buf, sizeof(buf), "%u", slotcfg->node); > + qemu_opt_set(devopts, "node", buf); > + qdev_device_add(devopts); > + > + return 0; > +} > + > +/* used to calculate physical address offsets for all dimms */ > +void dimm_calc_offsets(dimm_calcoffset_fn calcfn) > +{ > + DimmConfig *slot; > + QTAILQ_FOREACH(slot, &dimmconfig_list, nextdimmcfg) { > + if (!slot->start) { > + slot->start = calcfn(slot->size); > + } > + } > +} > + > +void setup_fwcfg_hp_dimms(uint64_t *fw_cfg_slots) > +{ > + DimmConfig *slot; > + > + QTAILQ_FOREACH(slot, &dimmconfig_list, nextdimmcfg) { > + assert(slot->start); > + fw_cfg_slots[3 * slot->idx] = cpu_to_le64(slot->start); > + fw_cfg_slots[3 * slot->idx + 1] = cpu_to_le64(slot->size); > + fw_cfg_slots[3 * slot->idx + 2] = cpu_to_le64(slot->node); > + } > +} > + > +void dimm_notify(uint32_t idx, uint32_t event) > +{ > + DimmBus *bus = main_memory_bus; > + DimmDevice *s; > + s = dimm_find_from_idx(idx); > + assert(s != NULL); > + > + switch(event) { > + case DIMM_REMOVE_SUCCESS: > + dimm_depopulate(s); > + qdev_simple_unplug_cb((DeviceState*)s); > + QTAILQ_REMOVE(&bus->dimmlist, s, nextdimm); > + break; > + default: > + break; > + } > +} > + > +static int dimm_init(DeviceState *s) > +{ > + DimmBus *bus = main_memory_bus; > + DimmDevice *slot; > + DimmConfig *slotcfg; > + > + slot = DIMM(s); > + slot->mr = NULL; > + > + slotcfg = dimmcfg_find_from_name(s->id); > + > + if (!slotcfg) { > + fprintf(stderr, "%s no config for slot %s found\n", > + __FUNCTION__, s->id); > + return 1; > + } > + > + slot->idx = slotcfg->idx; > + assert(slotcfg->start); > + slot->start = slotcfg->start; > + slot->size = slotcfg->size; > + slot->node = slotcfg->node; > + > + QTAILQ_INSERT_TAIL(&bus->dimmlist, slot, nextdimm); > + dimm_plug_device(slot); > + > + return 0; > +} > + > + > +static void dimm_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->props = dimm_properties; > + dc->unplug = dimm_unplug_device; > + dc->init = dimm_init; > +} > + > +static TypeInfo dimm_info = { > + .name = TYPE_DIMM, > + .parent = TYPE_DEVICE, > + .instance_size = sizeof(DimmDevice), > + .class_init = dimm_class_init, > +}; > + > +static void dimm_register_types(void) > +{ > + type_register_static(&dimm_bus_info); > + type_register_static(&dimm_info); > +} > + > +type_init(dimm_register_types) > diff --git a/hw/dimm.h b/hw/dimm.h > new file mode 100644 > index 0000000..5e991a6 > --- /dev/null > +++ b/hw/dimm.h > @@ -0,0 +1,90 @@ > +#ifndef QEMU_DIMM_H > +#define QEMU_DIMM_H > + > +#include "qemu-common.h" > +#include "memory.h" > +#include "sysbus.h" > +#include "qapi-types.h" > +#include "qemu-queue.h" > +#include "cpus.h" > +#define MAX_DIMMS 255 > +#define DIMM_BITMAP_BYTES (MAX_DIMMS + 7) / 8 > +#define DEFAULT_DIMMSIZE 1024*1024*1024 > + > +typedef enum { > + DIMM_REMOVE_SUCCESS = 0, > + DIMM_REMOVE_FAIL = 1, > + DIMM_ADD_SUCCESS = 2, > + DIMM_ADD_FAIL = 3 > +} dimm_hp_result_code; > + > +#define TYPE_DIMM "dimm" > +#define DIMM(obj) \ > + OBJECT_CHECK(DimmDevice, (obj), TYPE_DIMM) > +#define DIMM_CLASS(klass) \ > + OBJECT_CLASS_CHECK(DimmDeviceClass, (klass), TYPE_DIMM) > +#define DIMM_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(DimmDeviceClass, (obj), TYPE_DIMM) > + > +typedef struct DimmDevice DimmDevice; > +typedef QTAILQ_HEAD(DimmConfiglist, DimmConfig) DimmConfiglist; > + > +typedef struct DimmDeviceClass { > + DeviceClass parent_class; > + > + int (*init)(DimmDevice *dev); > +} DimmDeviceClass; > + > +typedef struct DimmDevice { typedef is unnecessay here, and it will break building: CC hmp.o In file included from /home/wency/source/qemu/hw/acpi_piix4.c:32: /home/wency/source/qemu/hw/dimm.h:54: error: redefinition of typedef ‘DimmDevice’ /home/wency/source/qemu/hw/dimm.h:36: note: previous declaration of ‘DimmDevice’ was here make[1]: *** [hw/acpi_piix4.o] Error 1 make[1]: *** Waiting for unfinished jobs.... CC audio/audio.o make: *** [subdir-libhw64] Error 2 make: *** Waiting for unfinished jobs.... Thanks Wen Congyang > + DeviceState qdev; > + uint32_t idx; /* index in memory hotplug register/bitmap */ > + ram_addr_t start; /* starting physical address */ > + ram_addr_t size; > + uint32_t node; /* numa node proximity */ > + MemoryRegion *mr; /* MemoryRegion for this slot. !NULL only if populated */ > + QTAILQ_ENTRY (DimmDevice) nextdimm; > +} DimmDevice; > + > +typedef struct DimmConfig > +{ > + const char *name; > + uint32_t idx; /* index in memory hotplug register/bitmap */ > + ram_addr_t start; /* starting physical address */ > + ram_addr_t size; > + uint32_t node; /* numa node proximity */ > + uint32_t populated; /* 1 means device has been hotplugged. Default is 0. */ > + QTAILQ_ENTRY (DimmConfig) nextdimmcfg; > +} DimmConfig; > + > +typedef int (*dimm_hotplug_fn)(DeviceState *qdev, DimmDevice *dev, int add); > +typedef target_phys_addr_t (*dimm_calcoffset_fn)(uint64_t size); > + > +#define TYPE_DIMM_BUS "dimmbus" > +#define DIMM_BUS(obj) OBJECT_CHECK(DimmBus, (obj), TYPE_DIMM_BUS) > + > +typedef struct DimmBus { > + BusState qbus; > + DeviceState *dimm_hotplug_qdev; > + dimm_hotplug_fn dimm_hotplug; > + dimm_calcoffset_fn dimm_calcoffset; > + DimmConfiglist dimmconfig_list; > + QTAILQ_HEAD(Dimmlist, DimmDevice) dimmlist; > +} DimmBus; > + > +struct dimm_hp_result { > + const char *dimmname; > + dimm_hp_result_code ret; > + QTAILQ_ENTRY (dimm_hp_result) next; > +}; > + > +void dimm_calc_offsets(dimm_calcoffset_fn calcfn); > +void dimm_notify(uint32_t idx, uint32_t event); > +void dimm_bus_hotplug(dimm_hotplug_fn hotplug, DeviceState *qdev); > +void setup_fwcfg_hp_dimms(uint64_t *fw_cfg_slots); > +int dimm_add(char *id); > +void main_memory_bus_create(Object *parent); > +void dimm_config_create(char *id, uint64_t size, uint64_t node, > + uint32_t dimm_idx, uint32_t populated); > + > + > +#endif

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[PATCH v2 0/2] Add IPMI support to SEABIOS
by minyard＠acm.org 24 Sep '12

24 Sep '12

This is a resend of basically the same code as before, to get things rolling again. -corey

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