SeaBIOS March 2013

seabios@seabios.org

41 participants
83 discussions

[PATCHv3] acpi: make default DSDT optional
by Michael S. Tsirkin 18 Mar '13

18 Mar '13

Since commit f7e4dd6c18ccfbaf6cd2f5eaaed2b77cabc8a406 QEMU loads its own copy of DSDT, so let's not build in PIIX. This makes building in the DSDT an option, default to on (built-in). For the builds bundled with qemu (where we _know_ qemu is new enougth that it actually works) we can flip the switch to 'n' (via roms/config.seabios). This way we save some space in the rom file and make it easy to avoid shipping dead code in qemu. At some point we might be able to switch it off by default and then maybe remove altogether. With CONFIG_ACPI_DSDT = y Total size: 127348 Fixed: 58892 Free: 3724 (used 97.2% of 128KiB rom) With CONFIG_ACPI_DSDT = n Total size: 122844 Fixed: 58884 Free: 8228 (used 93.7% of 128KiB rom) Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- Changes from v2: - fixed and extended the commit log addressing comments by Gerd, Laszlo, Paul. No functional changes. Changes from v1: - default the new option to y to reduce disruption to existing users src/Kconfig | 6 ++++++ src/acpi.c | 7 ++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 3141069..655ab1c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -387,6 +387,12 @@ menu "BIOS Tables" default y help Support generation of ACPI tables. + config ACPI_DSDT + bool "Include default ACPI DSDT" + default y + depends on ACPI + help + Include default DSDT ACPI table in BIOS. endmenu source vgasrc/Kconfig diff --git a/src/acpi.c b/src/acpi.c index 119d1c1..69dd3aa 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -202,7 +202,11 @@ struct srat_memory_affinity u32 reserved3[2]; } PACKED; +#ifdef CONFIG_ACPI_DSDT #include "acpi-dsdt.hex" +#else +static u8 AmlCode[1]; +#endif static void build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev) @@ -826,7 +830,8 @@ acpi_setup(void) break; } } - if (fadt && !fadt->dsdt) { + + if (fadt && !fadt->dsdt && CONFIG_ACPI_DSDT) { /* default DSDT */ void *dsdt = malloc_high(sizeof(AmlCode)); if (!dsdt) { -- MST

4 6

VGA Option ROM not set up correctly when loaded by coreboot and not SeaBIOS
by Paul Menzel 18 Mar '13

18 Mar '13

Dear SeaBIOS, using the AMD/ATI based ASRock E350M1 [1] with coreboot and SeaBIOS 1.7.2.1 as a payload and GRUB 2 (1.99-27 from Debian Sid/unstable) on the hard drive, letting coreboot load the VGA Option ROM and disabling »Option ROMs« in the menu »BIOS interfaces« config OPTIONROMS bool "Option ROMS" default y # I set it to n. help Support finding and running option roms during POST. I only see »AMD Wrestler …« printed to the screen (from the VGA Option ROM loaded by coreboot I guess) and I neither see the SeaBIOS header(?) with version nor the bootmenu. GRUB 2 does not show its (terminal) menu either and just shows funny, colorful characters covering the whole screen. Linux is able to print something to the screen, but Linux’ Radeon driver complains too that it does not find the BIOS ROM and kernel mode setting (KMS) is disabled. [ 0.000000] Linux version 3.2.0-4-686-pae (debian-kernel(a)lists.debian.org) (gcc version 4.6.3 (Debian 4.6.3-15) ) #1 SMP Debian 3.2.39-2 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009fc00 (usable) [ 0.000000] BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 00000000c7fe0000 (usable) [ 0.000000] BIOS-e820: 00000000c7fe0000 - 00000000e0000000 (reserved) [ 0.000000] BIOS-e820: 00000000f8000000 - 00000000f9000000 (reserved) [ 0.000000] BIOS-e820: 0000000100000000 - 000000021efffc00 (usable) […] [ 23.180795] calling radeon_init+0x0/0x1000 [radeon] @ 496 [ 23.180809] [drm] radeon kernel modesetting enabled. [ 23.190273] calling patch_realtek_init+0x0/0x1000 [snd_hda_codec_realtek] @ 685 [ 23.190292] initcall patch_realtek_init+0x0/0x1000 [snd_hda_codec_realtek] returned 0 after 1 usecs [ 23.190780] hda_codec: ALC892: SKU not ready 0x00000100 [ 23.194435] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:14.2/input/input5 [ 23.203623] input: HDA ATI SB Headphone as /devices/pci0000:00/0000:00:14.2/sound/card1/input6 [ 23.204868] initcall alsa_card_azx_init+0x0/0x1000 [snd_hda_intel] returned 0 after 240511 usecs [ 23.215517] radeon 0000:00:01.0: setting latency timer to 64 [ 23.215535] [drm] initializing kernel modesetting (PALM 0x1002:0x9802 0x1002:0x9802). [ 23.215606] [drm] register mmio base: 0xF0000000 [ 23.215609] [drm] register mmio size: 262144 [ 23.215689] radeon 0000:00:01.0: Invalid ROM contents [ 23.215887] [drm:radeon_get_bios] *ERROR* Unable to locate a BIOS ROM [ 23.216062] radeon 0000:00:01.0: Fatal error during GPU init [ 23.216187] [drm] radeon: finishing device. [ 23.216191] [TTM] Memory type 2 has not been initialized [ 23.217253] radeon 0000:00:01.0: no bo for sa manager [ 23.217382] vga_switcheroo: disabled [ 23.217781] radeon: probe of 0000:00:01.0 failed with error -22 [ 23.218165] initcall radeon_init+0x0/0x1000 [radeon] returned 0 after 36383 usecs […] Thanks, Paul [1] http://www.coreboot.org/ASRock_E350M1 [2] http://www.coreboot.org/SeaBIOS

2 1

VM won't start since 76e58028d28e78431f9de3cee0b3c88d807fa39d
by Michael S. Tsirkin 18 Mar '13

18 Mar '13

With seabios built from source, and latest qemu, VMs hang during boot for me. Bisect points at this commit: 76e58028d28e78431f9de3cee0b3c88d807fa39d Reverting this helps. Guest is stuck quite late, after 'switching root' message, so this could be just an OS visible change that it can't handle. Didn't try debugging more yet. -- MST

4 9

Minimal config for booting GRUB2 from SATA drive
by Paul Menzel 18 Mar '13

18 Mar '13

Dear SeaBIOS folks, I am using coreboot on the ASRock E350M1 [1] with a SATA hard drive, I want to boot from using the GRUB2 bootloader. For now I’d like to use SeaBIOS 1.7.2.1 for jumping to the hard drive and execute(?) GRUB2. Using the default config file created by `make menuconfig` and selecting a coreboot build and serial debug, everything works fine. As I am using Debian GNU/Linux I do not need any BIOS calls provided by SeaBIOS and want to disable as much as possible too. So I disabled most stuff, but could not boot from the hard drive. # # Automatically generated make config: don't edit # SeaBIOS Configuration # Thu Mar 14 12:14:21 2013 # # # General Features # CONFIG_COREBOOT=y # CONFIG_QEMU is not set CONFIG_THREADS=y # CONFIG_THREAD_OPTIONROMS is not set CONFIG_RELOCATE_INIT=y CONFIG_BOOTMENU=y CONFIG_BOOTSPLASH=y CONFIG_BOOTORDER=y CONFIG_COREBOOT_FLASH=y CONFIG_LZMA=y # CONFIG_FLASH_FLOPPY is not set # # Hardware support # CONFIG_ATA=y # CONFIG_ATA_DMA is not set # CONFIG_ATA_PIO32 is not set CONFIG_AHCI=y # CONFIG_MEGASAS is not set # CONFIG_FLOPPY is not set CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y CONFIG_USB_EHCI=y CONFIG_USB_MSC=y # CONFIG_USB_UAS is not set CONFIG_USB_HUB=y CONFIG_SERIAL=y # CONFIG_LPT is not set # # BIOS interfaces # CONFIG_DRIVES=y CONFIG_CDROM_BOOT=y CONFIG_CDROM_EMU=y # CONFIG_PCIBIOS is not set # CONFIG_APMBIOS is not set # CONFIG_PNPBIOS is not set CONFIG_OPTIONROMS=y # CONFIG_OPTIONROMS_DEPLOYED is not set # CONFIG_PMM is not set CONFIG_BOOT=y # CONFIG_KEYBOARD is not set # CONFIG_MOUSE is not set CONFIG_S3_RESUME=y # CONFIG_VGAHOOKS is not set # CONFIG_DISABLE_A20 is not set # # VGA ROM # CONFIG_NO_VGABIOS=y # CONFIG_VGA_GEODEGX2 is not set # CONFIG_VGA_GEODELX is not set # CONFIG_BUILD_VGABIOS is not set # # Debugging # CONFIG_DEBUG_LEVEL=2 CONFIG_DEBUG_SERIAL=y CONFIG_DEBUG_SERIAL_PORT=0x3f8 But SeaBIOS hangs at `Scan for option roms`. (`readserial.py` was used for capturing the log.) 01.081: Got a payload 01.081: Loading segment from rom address 0xffc9cc78 01.081: code (compression=0) 01.081: New segment dstaddr 0xec220 memsize 0x13de0 srcaddr 0xffc9ccb0 filesize 0x13de0 01.081: (cleaned up) New segment addr 0xec220 size 0x13de0 offset 0xffc9ccb0 filesize 0x13de0 01.081: Loading segment from rom address 0xffc9cc94 01.081: Entry Point 0x00000000 01.081: Loading Segment: addr: 0x00000000000ec220 memsz: 0x0000000000013de0 filesz: 0x0000000000013de0 01.081: lb: [0x0000000000200000, 0x0000000000360000) 01.081: Post relocation: addr: 0x00000000000ec220 memsz: 0x0000000000013de0 filesz: 0x0000000000013de0 01.081: it's not compressed! 01.104: [ 0x000ec220, 00100000, 0x00100000) <- ffc9ccb0 01.104: dest 000ec220, end 00100000, bouncebuffer c7d20000 01.104: Loaded segments 01.104: Jumping to boot code at fcdef 01.104: entry = 0x000fcdef 01.104: lb_start = 0x00200000 01.104: lb_size = 0x00160000 01.104: adjust = 0xc7c80000 01.104: buffer = 0xc7d20000 01.104: elf_boot_notes = 0x0026f008 01.105: adjusted_boot_notes = 0xc7eef008 01.107: Start bios (version rel-1.7.2.1-2-g0c4a0cf-20130314_121519-mye350m1) 01.107: Found mainboard ASROCK E350M1 01.107: Ram Size=0xc7fe0000 (0x000000011efffc00 high) 01.107: Relocating low data from 0x000ec9c0 to 0x000ef7a0 (size 2137) 01.107: Relocating init from 0x000ed219 to 0xc7fc7720 (size 34739) 01.107: Found CBFS header at 0xfffffbf0 01.109: CPU Mhz=1601 01.109: Found 23 PCI devices (max PCI bus is 01) 01.119: Found 2 cpu(s) max supported 2 cpu(s) 01.119: Copying PIR from 0xc7fe0400 to 0x000fe020 01.119: Copying MPTABLE from 0xc7fe1400/c7fe1410 to 0x000fdf10 01.120: Copying ACPI RSDP from 0xc7fe2400 to 0x000fdef0 01.120: Copying SMBIOS entry point from 0xc7fed800 to 0x000fded0 01.120: Scan for VGA option rom 01.139: Running option rom at c000:0003 01.193: Turning on vga text mode console 01.252: SeaBIOS (version rel-1.7.2.1-2-g0c4a0cf-20130314_121519-mye350m1) 01.252: EHCI init on dev 00:12.2 (regs=0xf004b420) 01.252: /c7fc5000\ Start thread 01.252: /c7fc4000\ Start thread 01.252: /c7fc3000\ Start thread 01.252: /c7fc2000\ Start thread 01.252: /c7fc1000\ Start thread 01.252: /c7fc0000\ Start thread 01.252: EHCI init on dev 00:13.2 (regs=0xf004b520) 01.253: /c7fbf000\ Start thread 01.252: /c7fbe000\ Start thread 01.253: /c7fbd000\ Start thread 01.253: /c7fbc000\ Start thread 01.253: /c7fbb000\ Start thread 01.253: /c7fba000\ Start thread 01.253: OHCI init on dev 00:14.5 (regs=0xf004a000) 01.253: /c7fb9000\ Start thread 01.253: Found 1 serial ports 01.253: AHCI controller at 11.0, iobase f004b000, irq 0 01.253: AHCI: cap 0xf332ff05, ports_impl 0x3f 01.253: /c7fb7000\ Start thread 01.253: |c7fb7000| AHCI/0: probing 01.253: |c7fb7000| AHCI/0: link up 01.253: /c7fb6000\ Start thread 01.253: |c7fb6000| AHCI/1: probing 01.253: /c7fb4000\ Start thread 01.253: |c7fb4000| AHCI/2: probing 01.253: /c7fb3000\ Start thread 01.253: |c7fb3000| AHCI/3: probing 01.253: /c7fb1000\ Start thread 01.253: |c7fb1000| AHCI/4: probing 01.253: /c7fb0000\ Start thread 01.253: |c7fb0000| AHCI/5: probing 01.253: \c7fc4000/ End thread 01.253: \c7fc3000/ End thread 01.253: \c7fc2000/ End thread 01.253: \c7fc1000/ End thread 01.253: |c7fc0000| OHCI init on dev 00:12.0 (regs=0xf0048000) 01.253: /c7fc4000\ Start thread 01.253: \c7fc0000/ End thread 01.253: \c7fbe000/ End thread 01.253: \c7fbd000/ End thread 01.253: \c7fbc000/ End thread 01.253: \c7fbb000/ End thread 01.253: \c7fba000/ End thread 01.253: |c7fb6000| AHCI/1: link down 01.253: |c7fb4000| AHCI/2: link down 01.253: |c7fb3000| AHCI/3: link down 01.253: |c7fb1000| AHCI/4: link down 01.253: |c7fb0000| AHCI/5: link down 01.253: /c7fc3000\ Start thread 01.253: \c7fc3000/ End thread 01.253: /c7fc3000\ Start thread 01.253: \c7fc3000/ End thread 01.253: \c7fb6000/ End thread 01.253: \c7fb4000/ End thread 01.253: \c7fb3000/ End thread 01.253: \c7fb1000/ End thread 01.253: \c7fb0000/ End thread 01.253: \c7fc5000/ End thread 01.253: \c7fbf000/ End thread 01.253: \c7fb9000/ End thread 01.258: /c7fc5000\ Start thread 01.258: \c7fc5000/ End thread 01.258: /c7fc5000\ Start thread 01.258: /c7fc3000\ Start thread 01.258: /c7fc2000\ Start thread 01.258: \c7fc2000/ End thread 01.258: /c7fc2000\ Start thread 01.258: \c7fc2000/ End thread 01.294: \c7fc5000/ End thread 01.331: \c7fc3000/ End thread 01.332: \c7fc4000/ End thread 10.223: |c7fb7000| AHCI/0: ... finished, status 0x51, ERROR 0x4 10.229: |c7fb7000| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0 10.229: |c7fb7000| AHCI/0: registering: "AHCI/0: WDC WD20EARS-60MVWB0 ATA-8 Hard-Disk (1863 GiBytes)" 10.229: \c7fb7000/ End thread 10.229: All threads complete. 10.229: Scan for option roms With the following change (mostly defaults), it works fine. $ diff -u .config-less .config-more --- .config-less 2013-03-14 12:14:21.650220263 +0100 +++ .config-more 2013-03-14 12:26:52.975960255 +0100 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # SeaBIOS Configuration -# Thu Mar 14 12:14:21 2013 +# Thu Mar 14 12:26:52 2013 # # @@ -13,11 +13,11 @@ # CONFIG_THREAD_OPTIONROMS is not set CONFIG_RELOCATE_INIT=y CONFIG_BOOTMENU=y -CONFIG_BOOTSPLASH=y +# CONFIG_BOOTSPLASH is not set CONFIG_BOOTORDER=y CONFIG_COREBOOT_FLASH=y CONFIG_LZMA=y -# CONFIG_FLASH_FLOPPY is not set +CONFIG_FLASH_FLOPPY=y The above differencese should not matter. # # Hardware support @@ -28,6 +28,7 @@ CONFIG_AHCI=y # CONFIG_MEGASAS is not set # CONFIG_FLOPPY is not set +CONFIG_PS2PORT=y CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y @@ -35,6 +36,8 @@ CONFIG_USB_MSC=y # CONFIG_USB_UAS is not set CONFIG_USB_HUB=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_MOUSE=y CONFIG_SERIAL=y # CONFIG_LPT is not set @@ -44,23 +47,27 @@ CONFIG_DRIVES=y CONFIG_CDROM_BOOT=y CONFIG_CDROM_EMU=y -# CONFIG_PCIBIOS is not set -# CONFIG_APMBIOS is not set -# CONFIG_PNPBIOS is not set +CONFIG_PCIBIOS=y +CONFIG_APMBIOS=y +CONFIG_PNPBIOS=y CONFIG_OPTIONROMS=y # CONFIG_OPTIONROMS_DEPLOYED is not set -# CONFIG_PMM is not set +CONFIG_PMM=y CONFIG_BOOT=y -# CONFIG_KEYBOARD is not set -# CONFIG_MOUSE is not set +CONFIG_KEYBOARD=y +CONFIG_KBD_CALL_INT15_4F=y +CONFIG_MOUSE=y CONFIG_S3_RESUME=y -# CONFIG_VGAHOOKS is not set +CONFIG_VGAHOOKS=y # CONFIG_DISABLE_A20 is not set # # VGA ROM # CONFIG_NO_VGABIOS=y +# CONFIG_VGA_STANDARD_VGA is not set +# CONFIG_VGA_CIRRUS is not set +# CONFIG_VGA_BOCHS is not set # CONFIG_VGA_GEODEGX2 is not set # CONFIG_VGA_GEODELX is not set # CONFIG_BUILD_VGABIOS is not set Not sure, which change caused it, but SeaBIOS jumps to the hard drive correctly. 01.091: Got a payload 01.091: Loading segment from rom address 0xffc9cc78 01.091: code (compression=0) 01.091: New segment dstaddr 0xea2c0 memsize 0x15d40 srcaddr 0xffc9ccb0 filesize 0x15d40 01.091: (cleaned up) New segment addr 0xea2c0 size 0x15d40 offset 0xffc9ccb0 filesize 0x15d40 01.091: Loading segment from rom address 0xffc9cc94 01.091: Entry Point 0x00000000 01.091: Loading Segment: addr: 0x00000000000ea2c0 memsz: 0x0000000000015d40 filesz: 0x0000000000015d40 01.091: lb: [0x0000000000200000, 0x0000000000360000) 01.091: Post relocation: addr: 0x00000000000ea2c0 memsz: 0x0000000000015d40 filesz: 0x0000000000015d40 01.091: it's not compressed! 01.091: [ 0x000ea2c0, 00100000, 0x00100000) <- ffc9ccb0 01.091: dest 000ea2c0, end 00100000, bouncebuffer c7d20000 01.091: Loaded segments 01.091: Jumping to boot code at fc68b 01.091: entry = 0x000fc68b 01.091: lb_start = 0x00200000 01.091: lb_size = 0x00160000 01.091: adjust = 0xc7c80000 01.091: buffer = 0xc7d20000 01.091: elf_boot_notes = 0x0026f008 01.091: adjusted_boot_notes = 0xc7eef008 01.091: Start bios (version rel-1.7.2.1-2-g0c4a0cf-20130314_122745-mye350m1) 01.091: Found mainboard ASROCK E350M1 01.091: Ram Size=0xc7fe0000 (0x000000011efffc00 high) 01.090: Relocating low data from 0x000eaad0 to 0x000ef790 (size 2153) 01.090: Relocating init from 0x000eb339 to 0xc7fc8b30 (size 29615) 01.090: Found CBFS header at 0xfffffbf0 01.092: CPU Mhz=1602 01.093: Found 23 PCI devices (max PCI bus is 01) 01.102: Found 2 cpu(s) max supported 2 cpu(s) 01.102: Copying PIR from 0xc7fe0400 to 0x000fdbc0 01.103: Copying MPTABLE from 0xc7fe1400/c7fe1410 to 0x000fdab0 01.102: Copying ACPI RSDP from 0xc7fe2400 to 0x000fda90 01.103: Copying SMBIOS entry point from 0xc7fed800 to 0x000fda70 01.103: Scan for VGA option rom 01.121: Running option rom at c000:0003 01.170: Turning on vga text mode console 01.229: SeaBIOS (version rel-1.7.2.1-2-g0c4a0cf-20130314_122745-mye350m1) 01.230: EHCI init on dev 00:12.2 (regs=0xf004b420) 01.229: /c7fc6000\ Start thread 01.229: /c7fc5000\ Start thread 01.229: /c7fc4000\ Start thread 01.229: /c7fc3000\ Start thread 01.229: /c7fc2000\ Start thread 01.229: /c7fc1000\ Start thread 01.229: EHCI init on dev 00:13.2 (regs=0xf004b520) 01.229: /c7fc0000\ Start thread 01.229: /c7fbf000\ Start thread 01.229: /c7fbe000\ Start thread 01.229: /c7fbd000\ Start thread 01.229: /c7fbc000\ Start thread 01.229: /c7fbb000\ Start thread 01.229: OHCI init on dev 00:14.5 (regs=0xf004a000) 01.229: /c7fba000\ Start thread 01.229: /c7fb9000\ Start thread 01.232: Found 1 serial ports 01.232: AHCI controller at 11.0, iobase f004b000, irq 0 01.232: AHCI: cap 0xf332ff05, ports_impl 0x3f 01.232: /c7fb7000\ Start thread 01.233: |c7fb7000| AHCI/0: probing 01.233: |c7fb7000| AHCI/0: link up 01.233: /c7fb6000\ Start thread 01.232: |c7fb6000| AHCI/1: probing 01.232: /c7fb4000\ Start thread 01.232: |c7fb4000| AHCI/2: probing 01.233: /c7fb3000\ Start thread 01.233: |c7fb3000| AHCI/3: probing 01.232: /c7fb1000\ Start thread 01.232: |c7fb1000| AHCI/4: probing 01.233: /c7fb0000\ Start thread 01.233: |c7fb0000| AHCI/5: probing 01.233: \c7fc5000/ End thread 01.233: \c7fc4000/ End thread 01.233: \c7fc3000/ End thread 01.233: \c7fc2000/ End thread 01.233: |c7fc1000| OHCI init on dev 00:12.0 (regs=0xf0048000) 01.233: /c7fc5000\ Start thread 01.233: \c7fc1000/ End thread 01.233: \c7fbf000/ End thread 01.233: \c7fbe000/ End thread 01.233: \c7fbd000/ End thread 01.233: \c7fbc000/ End thread 01.233: \c7fbb000/ End thread 01.233: |c7fb6000| AHCI/1: link down 01.233: |c7fb4000| AHCI/2: link down 01.233: |c7fb3000| AHCI/3: link down 01.233: |c7fb1000| AHCI/4: link down 01.233: |c7fb0000| AHCI/5: link down 01.233: /c7fc4000\ Start thread 01.233: \c7fc4000/ End thread 01.233: /c7fc4000\ Start thread 01.234: \c7fc4000/ End thread 01.234: |c7fb9000| Got ps2 nak (status=51) 01.234: |c7fb9000| ps2 command 2ff failed (aux=0) 01.234: \c7fb9000/ End thread 01.234: \c7fb6000/ End thread 01.234: \c7fb4000/ End thread 01.234: \c7fb3000/ End thread 01.234: \c7fb1000/ End thread 01.233: \c7fb0000/ End thread 01.233: \c7fc6000/ End thread 01.234: \c7fc0000/ End thread 01.233: \c7fba000/ End thread 01.233: /c7fc6000\ Start thread 01.234: \c7fc6000/ End thread 01.234: /c7fc6000\ Start thread 01.233: /c7fc4000\ Start thread 01.234: /c7fc3000\ Start thread 01.234: \c7fc3000/ End thread 01.234: /c7fc3000\ Start thread 01.233: \c7fc3000/ End thread 01.270: |c7fc6000| usb_hid_init 0xc7fc7a50 01.271: |c7fc6000| USB mouse initialized 01.271: \c7fc6000/ End thread 01.301: |c7fc4000| usb_hid_init 0xc7fc7a50 01.302: |c7fc4000| USB keyboard initialized 01.302: \c7fc4000/ End thread 01.303: \c7fc5000/ End thread 10.203: |c7fb7000| AHCI/0: ... finished, status 0x51, ERROR 0x4 10.208: |c7fb7000| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0 10.208: |c7fb7000| AHCI/0: registering: "AHCI/0: WDC WD20EARS-60MVWB0 ATA-8 Hard-Disk (1863 GiBytes)" 10.208: \c7fb7000/ End thread 10.208: All threads complete. 10.209: Scan for option roms 10.209: 10.209: Press F12 for boot menu. 10.209: 10.282: Searching bootorder for: HALT 10.283: drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=-387938128 10.283: Space available for UMB: 000ce800-000ee000 10.283: Returned 57344 bytes of ZoneHigh 10.283: e820 map has 7 items: 10.283: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 10.283: 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 10.283: 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 10.283: 3: 0000000000100000 - 00000000c7fde000 = 1 RAM 10.283: 4: 00000000c7fde000 - 00000000e0000000 = 2 RESERVED 10.283: 5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED 10.283: 6: 0000000100000000 - 000000021efffc00 = 1 RAM 10.284: enter handle_19: 10.284: NULL 10.284: Booting from Hard Disk... 10.314: Booting from 0000:7c00 Any help on knowing what options I need or not is much appreciated. Thanks, Paul [1] http://www.coreboot.org/ASRock_E350M1

2 4

[PATCH] acpi: make default DSDT optional
by Michael S. Tsirkin 18 Mar '13

18 Mar '13

QEMU now loads its own copy of DSDT, so let's not build in PIIX. This leaves building in the DSDT an option, default to off. If no one complains for a while, we'll be able to remove this altogether. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- src/Kconfig | 5 +++++ src/acpi.c | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 3141069..3be07f4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -387,6 +387,11 @@ menu "BIOS Tables" default y help Support generation of ACPI tables. + config ACPI_DSDT + bool "Include default ACPI DSDT" + depends on ACPI + help + Include default DSDT ACPI table in BIOS. endmenu source vgasrc/Kconfig diff --git a/src/acpi.c b/src/acpi.c index 119d1c1..69dd3aa 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -202,7 +202,11 @@ struct srat_memory_affinity u32 reserved3[2]; } PACKED; +#ifdef CONFIG_ACPI_DSDT #include "acpi-dsdt.hex" +#else +static u8 AmlCode[1]; +#endif static void build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev) @@ -826,7 +830,8 @@ acpi_setup(void) break; } } - if (fadt && !fadt->dsdt) { + + if (fadt && !fadt->dsdt && CONFIG_ACPI_DSDT) { /* default DSDT */ void *dsdt = malloc_high(sizeof(AmlCode)); if (!dsdt) { -- MST

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[PATCH] README: update about how to use ACPI DSDT with qemu
by Hu Tao 17 Mar '13

17 Mar '13

Signed-off-by: Hu Tao <hutao(a)cn.fujitsu.com> --- README | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README b/README index c6462b7..6eec8a2 100644 --- a/README +++ b/README @@ -18,6 +18,11 @@ bios images and then overwrite the main bios image. For example: cp /usr/share/qemu/*.bin mybiosdir/ cp out/bios.bin mybiosdir/ +And optional, to test ACPI DSDT, one will need to copy the aml files. +For example: + +cp out/*.aml mybiosdir/ + Once this is setup, one can instruct qemu to use the newly created directory for rom images. For example: -- 1.8.1.4

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Way to configure debug level without rebuilt?
by Paul Menzel 15 Mar '13

15 Mar '13

Dear SeaBIOS folks, to save some time not having to rebuild SeaBIOS for different debug levels, is there an option to configure this using a file with the debug level value in CBFS for example? Or have I missed something? Thanks, Paul

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[PATCH 0/2][RFC] Remove BDAT from ACPI interface
by Kevin O'Connor 15 Mar '13

15 Mar '13

This patch changes SeaBIOS to pass the PCI regions via a dynamically updated SSDT instead of via the BDAT memory reference system. This change will likely make it easier to port the ACPI tables to QEMU. This patch has only been lightly tested. Gerd - I know you ran various tests when originally introducing the BDAT system. Do you recall what test cases you used? -Kevin Kevin O'Connor (2): Rename src/ssdt-susp.dsl to src/ssdt-misc.dsl. acpi: Eliminate BDAT parameter passing to DSDT code. Makefile | 2 +- src/acpi-dsdt-pci-crs.dsl | 61 +++++++++++++++++------------------------------ src/acpi.c | 47 +++++++++++++----------------------- src/acpi.h | 9 ------- src/ssdt-misc.dsl | 58 ++++++++++++++++++++++++++++++++++++++++++++ src/ssdt-susp.dsl | 38 ----------------------------- tools/acpi_extract.py | 17 ++++++++++++- 7 files changed, 114 insertions(+), 118 deletions(-) create mode 100644 src/ssdt-misc.dsl delete mode 100644 src/ssdt-susp.dsl -- 1.7.11.7

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[PATCH] Add pvevent device driver
by Hu Tao 14 Mar '13

14 Mar '13

pvevent device is used to notify host(qemu) when guest panic happens. ref: http://lists.nongnu.org/archive/html/qemu-devel/2013-03/msg02293.html Signed-off-by: Hu Tao <hutao(a)cn.fujitsu.com> --- src/acpi-dsdt-isa.dsl | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/acpi-dsdt-isa.dsl b/src/acpi-dsdt-isa.dsl index 23761db..d083245 100644 --- a/src/acpi-dsdt-isa.dsl +++ b/src/acpi-dsdt-isa.dsl @@ -99,4 +99,34 @@ Scope(\_SB.PCI0.ISA) { IRQNoFlags() { 3 } }) } + + Device(PEVT) { + Name(_HID, "MSFT0001") + OperationRegion(PEOR, SystemIO, 0x0505, 0x01) + Field(PEOR, ByteAcc, NoLock, Preserve) { + PEPT, 8, + } + + Method(_STA, 0, NotSerialized) { + Store(PEPT, Local0) + If (LEqual(Local0, Zero)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + + Method(RDPT, 0, NotSerialized) { + Store(PEPT, Local0) + Return (Local0) + } + + Method(WRPT, 1, NotSerialized) { + Store(Arg0, PEPT) + } + + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0505, 0x0505, 0x01, 0x01) + }) + } } -- 1.8.1.4

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[PATCH] Fix build-dep on some .dsl files
by Hu Tao 12 Mar '13

12 Mar '13

acpi-dsdt.dsl and q35-acpi-dsdt.dsl include some .dsl files, so the corresponding .hex must have build-dep on these files, too. Signed-off-by: Hu Tao <hutao(a)cn.fujitsu.com> --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 1ce2f79..188b8e4 100644 --- a/Makefile +++ b/Makefile @@ -221,6 +221,7 @@ $(OUT)%.hex: src/%.dsl ./tools/acpi_extract_preprocess.py ./tools/acpi_extract.p $(Q)cat $(OUT)$*.off > $@ $(OUT)acpi.o: $(OUT)acpi-dsdt.hex $(OUT)ssdt-proc.hex $(OUT)ssdt-pcihp.hex $(OUT)ssdt-susp.hex $(OUT)q35-acpi-dsdt.hex +$(OUT)acpi-dsdt.hex $(OUT)q35-acpi-dsdt.hex: src/acpi-dsdt-dbug.dsl src/acpi-dsdt-pci-crs.dsl src/acpi-dsdt-hpet.dsl src/acpi-dsdt-isa.dsl src/acpi-dsdt-cpu-hotplug.dsl ################ Kconfig rules -- 1.8.1.4

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SeaBIOS March 2013