January 2012 - SeaBIOS - mail.coreboot.org

by Peter Stuge

Fred . wrote: > Add to source tree. > bootsplash.bmp I'm afraid that's not likely. The file is 1.2 MB, which would grow the current repository size over 30%. I find that unacceptable for a bootsplash file that most will really notice or want. Recall the discussion when you first brought up the bootsplash topic. SeaBIOS as you may have experienced by now only runs for a few hundred milliseconds, and in fact running the VGA BIOS takes most of that time, so a bootsplash would only be visible for maybe a tenth of a second. Suggesting to add artificial delays would not be wise. Furthermore, if there is to be a bootsplash (which I for one don't hold for impossible) then it needs to be generated from the professional project logo (so far there is none) and preferably using scripted free and libre tools. In any case, I think all graphics should be stored outside the source tree, and be an optional addon. See e.g. what we do for the coreboot logo: http://coreboot.org/Logo //Peter

8 years, 1 month

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bootslash.bmp

by Fred .

Add to source tree. 640x480 bmp. bootsplash.bmp http://www.sendspace.com/file/istb8e

8 years, 1 month

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[PATCH 00/10] More vgabios work

by Kevin O'Connor

This round includes more vgabios porting and refactoring. At the end of this round, all cirrus functions should now be ported - Cirrus vgabios should be feature complete with the lgpl vgabios. -Kevin Kevin O'Connor (10): vgabios: Use stored total memory in cirrus code instead of recalculating. vgabios: Set cwidth/cheight/sstart in vgamode_s for cirrus/bochs. vgabios: Extract out current mode finding into new function. vgabios: Move BDA setting from driver code to common code. vgabios: Add support for vesa get/set window function. vgabios: Add support for vbe get/set line length function. vgabios: Add support for VBE get/set display start function. vgabios: Add VBE power management (10h) stub function. vgabios: Minor - pass display address to stdvga_set_cursor_pos(). vgabios: Move stdvga_set_mode() to stdvgamodes.c. vgasrc/bochsvga.c | 209 +++++++++++++++++++++------------- vgasrc/bochsvga.h | 8 +- vgasrc/clext.c | 317 +++++++++++++++++-------------------------------- vgasrc/clext.h | 8 +- vgasrc/stdvga.c | 183 +++++++++++------------------ vgasrc/stdvga.h | 29 ++--- vgasrc/stdvgaio.c | 1 + vgasrc/stdvgamodes.c | 123 +++++++++++++++++++ vgasrc/vbe.c | 131 ++++++++++++++++++--- vgasrc/vgabios.c | 66 +++++++++-- vgasrc/vgabios.h | 5 +- vgasrc/vgaentry.S | 5 + vgasrc/vgafb.c | 12 +- vgasrc/vgahw.h | 57 +++++++++- 14 files changed, 688 insertions(+), 466 deletions(-) -- 1.7.6.4

8 years, 1 month

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Re: [SeaBIOS] Concept logos

by Peter Stuge

Fred . wrote: > I drafted some concept logos. > Please provide feedback. > Perhaps we could have a vote? > > http://img585.imageshack.us/img585/3820/seabiosconceptlogos.png Sorry if this sounds harsh, but the only one I like is gear+waves. I think a "chip" is an ugly and boring shape :\ and the shark while a cool idea is probably difficult to make look nice while still keeping free of significant detail. It's important to keep the shape simple and elegant. The trident is a fun idea but a little bit too pointy, I guess it would also require too much detail to look good and still be really practical. Same for DNA. The gear+waves concept definately wins my vote. Thanks for taking this initiative! //Peter

8 years, 1 month

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Concept logos

by Fred .

I drafted some concept logos. Please provide feedback. Perhaps we could have a vote? http://img585.imageshack.us/img585/3820/seabiosconceptlogos.png

8 years, 1 month

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[RFC PATCH 0/4] vgabios runtime hardware detection

by Gerd Hoffmann

Hi, This adds runtime hardware detection to vgabios. Survived light (vga text mode) testing. The isa bits are completely untested as qemu -M isapc is foobar atm. Comments on the approach? cheers, Gerd Gerd Hoffmann (4): vga: move code to vgahw.c vga: add pci hardware detection vga: add isa hardware detection vga: adapt kconfig Makefile | 2 +- vgasrc/Kconfig | 61 ++++++++++++--------------- vgasrc/bochsvga.c | 7 +++ vgasrc/bochsvga.h | 1 + vgasrc/clext.c | 6 +++ vgasrc/clext.h | 1 + vgasrc/vgahw.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/vgahw.h | 52 +++++++++-------------- 8 files changed, 184 insertions(+), 66 deletions(-) create mode 100644 vgasrc/vgahw.c

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[RFC] vgabios over serial

by Rudolf Marek

Hi all, I guess it would be not very difficult to add a serial output to VGA BIOS and provide int16 serial input aka integrating the sgabios into seabios? Comments? Thanks Rudolf

8 years, 1 month

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Re: [SeaBIOS] Geode vga pci code

by Nils

>> I don't know if this is a bug but when i use the name >>"pci100b,0030.rom" >> for the vgabios it is still not loading it. >> It would be nice to be able to add the vgabios to cbfs via the >>existing >> coreboot kconfig option. > >Something's not right with the way the PCI device is configured. You >could try putting debug statements in is_pci_vga() to find out what. I fixed this problem. The PCI_COMMAND_IO bit was not set in the VGA PCI space. Thanks, Nils.

8 years, 1 month

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Re: [SeaBIOS] [PATCH v2 3/4] uq/master: Add CPU eject handling for acpi_piix4

by Jan Kiszka

On 2012-01-24 11:10, Vasilis Liaskovitis wrote: > Add stub functions for CPU eject callback. Define cpu_acpi_eject property and > enable eject callback only for pc-1.1 machine model. Just to get the idea: What is the plan and advantage of introducing a stub first? How much more is required to have some usable feature, even if its just a friction of the full support? > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > hw/acpi_piix4.c | 20 ++++++++++++++++++++ > hw/pc_piix.c | 8 ++++++++ > 2 files changed, 28 insertions(+), 0 deletions(-) > > diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c > index 96e1ce8..8475aa6 100644 > --- a/hw/acpi_piix4.c > +++ b/hw/acpi_piix4.c > @@ -40,6 +40,7 @@ > > #define GPE_BASE 0xafe0 > #define PROC_BASE 0xaf00 > +#define PROC_EJ_BASE 0xaf20 > #define GPE_LEN 4 > #define PCI_BASE 0xae00 > #define PCI_EJ_BASE 0xae08 > @@ -80,6 +81,8 @@ typedef struct PIIX4PMState { > struct gpe_regs gpe_cpu; > struct pci_status pci0_status; > uint32_t pci0_hotplug_enable; > + /* for cpu hotplug */ > + uint32_t cpu_acpi_eject; > } PIIX4PMState; > > static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); > @@ -424,6 +427,7 @@ static PCIDeviceInfo piix4_pm_info = { > .class_id = PCI_CLASS_BRIDGE_OTHER, > .qdev.props = (Property[]) { > DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), > + DEFINE_PROP_UINT32("cpu_acpi_eject", PIIX4PMState, cpu_acpi_eject, 0), > DEFINE_PROP_END_OF_LIST(), > } > }; > @@ -497,6 +501,17 @@ static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) > PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val); > } > > +static uint32_t cpuej_read(void *opaque, uint32_t addr) > +{ > + PIIX4_DPRINTF("cpuej read %x\n", addr); > + return 0; > +} > + > +static void cpuej_write(void *opaque, uint32_t addr, uint32_t val) > +{ > + PIIX4_DPRINTF("cpuej write %x <== %d\n", addr, val); > +} > + > static uint32_t pciej_read(void *opaque, uint32_t addr) > { > PIIX4_DPRINTF("pciej read %x\n", addr); > @@ -555,6 +570,11 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) > register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s); > register_ioport_read(PROC_BASE, 32, 1, gpe_readb, s); > > + if (s->cpu_acpi_eject) { > + register_ioport_write(PROC_EJ_BASE, 32, 1, cpuej_write, s); > + register_ioport_read(PROC_EJ_BASE, 32, 1, cpuej_read, s); > + } > + > register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); > register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); > > diff --git a/hw/pc_piix.c b/hw/pc_piix.c > index ac251c6..6d61567 100644 > --- a/hw/pc_piix.c > +++ b/hw/pc_piix.c > @@ -380,6 +380,14 @@ static QEMUMachine pc_machine_v1_1 = { > .desc = "Standard PC", > .init = pc_init_pci, > .max_cpus = 255, > + .compat_props = (GlobalProperty[]) { > + { > + .driver = "PIIX4_PM", > + .property = "cpu_acpi_eject", > + .value = stringify(1), Such things are usually handled the other way around: define no_cpu_acpi_eject and set it in all legacy machines. > + }, > + { /* end of list */ } > + }, > }; > > static QEMUMachine pc_machine_v1_0 = { Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux

8 years, 1 month

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[PATCH 4/4] uq/master: Add acpi cpu interface documentation

by Vasilis Liaskovitis

Add CPU acpi interface documentation. Move all ACPI documentation (CPU and PCI) to one file. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- docs/specs/acpi_hotplug.txt | 49 +++++++++++++++++++++++++++++++++++++++ docs/specs/acpi_pci_hotplug.txt | 37 ----------------------------- 2 files changed, 49 insertions(+), 37 deletions(-) create mode 100644 docs/specs/acpi_hotplug.txt delete mode 100644 docs/specs/acpi_pci_hotplug.txt diff --git a/docs/specs/acpi_hotplug.txt b/docs/specs/acpi_hotplug.txt new file mode 100644 index 0000000..2026bed --- /dev/null +++ b/docs/specs/acpi_hotplug.txt @@ -0,0 +1,49 @@ +QEMU<->ACPI BIOS PCI hotplug interface +-------------------------------------- + +QEMU supports PCI hotplug via ACPI, for PCI bus 0. This document +describes the interface between QEMU and the ACPI BIOS. + +ACPI GPE block (IO ports 0xafe0-0xafe3, byte access): +----------------------------------------- + +Generic ACPI GPE block. Bit 1 (GPE.1) used to notify PCI hotplug/eject +event to ACPI BIOS, via SCI interrupt. + +PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access): +--------------------------------------------------------------- +Slot injection notification pending. One bit per slot. + +Read by ACPI BIOS GPE.1 handler to notify OS of injection +events. + +PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access): +----------------------------------------------------- +Slot removal notification pending. One bit per slot. + +Read by ACPI BIOS GPE.1 handler to notify OS of removal +events. + +PCI device eject (IO port 0xae08-0xae0b, 4-byte access): +---------------------------------------- + +Used by ACPI BIOS _EJ0 method to request device removal. One bit per slot. +Reads return 0. + +PCI removability status (IO port 0xae0c-0xae0f, 4-byte access): +----------------------------------------------- + +Used by ACPI BIOS _RMV method to indicate removability status to OS. One +bit per slot. + +CPU hotplug notification pending (IO port 0xaf00-0xaf1f, 32-byte access): +--------------------------------------------------------------- +CPU hotplug notification pending. One bit per cpu. + +Read by ACPI BIOS GPE.2 handler to notify OS of injection +events. + +CPU eject (IO port 0xaf20-0xaf3f, 32-byte access): +---------------------------------------- + +Used by ACPI BIOS _EJ0 method to request cpu removal. One bit per cpu. diff --git a/docs/specs/acpi_pci_hotplug.txt b/docs/specs/acpi_pci_hotplug.txt deleted file mode 100644 index f0f74a7..0000000 --- a/docs/specs/acpi_pci_hotplug.txt +++ /dev/null @@ -1,37 +0,0 @@ -QEMU<->ACPI BIOS PCI hotplug interface --------------------------------------- - -QEMU supports PCI hotplug via ACPI, for PCI bus 0. This document -describes the interface between QEMU and the ACPI BIOS. - -ACPI GPE block (IO ports 0xafe0-0xafe3, byte access): ------------------------------------------ - -Generic ACPI GPE block. Bit 1 (GPE.1) used to notify PCI hotplug/eject -event to ACPI BIOS, via SCI interrupt. - -PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access): ---------------------------------------------------------------- -Slot injection notification pending. One bit per slot. - -Read by ACPI BIOS GPE.1 handler to notify OS of injection -events. - -PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access): ------------------------------------------------------ -Slot removal notification pending. One bit per slot. - -Read by ACPI BIOS GPE.1 handler to notify OS of removal -events. - -PCI device eject (IO port 0xae08-0xae0b, 4-byte access): ----------------------------------------- - -Used by ACPI BIOS _EJ0 method to request device removal. One bit per slot. -Reads return 0. - -PCI removability status (IO port 0xae0c-0xae0f, 4-byte access): ------------------------------------------------ - -Used by ACPI BIOS _RMV method to indicate removability status to OS. One -bit per slot. -- 1.7.7.3

8 years, 1 month

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SeaBIOS January 2012