coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Dmitry Torokhov (Code Review) 07 Sep '22

07 Sep '22

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Tim Van Patten. Dmitry Torokhov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 2: (1 comment) File Documentation/getting_started/devicetree.md: https://review.coreboot.org/c/coreboot/+/67385/comment/a6fe5a77_834eac21 PS2, Line 263: The linux kernel has great support for this method. > Isn't the issue that the kernel doesn't warn the user/developer that they have both wake sources ena […] I'd argue warning users about messed up firmware is not Linux kernel's task. Quite often users of the message can't do anything about it, and the device might not be running Linux at all... Can this be added to pre-upload/pre-commit checks? -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 22:49:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Tim Van Patten (Code Review) 07 Sep '22

07 Sep '22

Attention is currently required from: Raul Rangel, Tim Wawrzynczak. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 2: (2 comments) File Documentation/getting_started/devicetree.md: https://review.coreboot.org/c/coreboot/+/67385/comment/904cf581_9eeeba2b PS2, Line 96: When this entry is processed during ramstage, it will create a device in the : ACPI SSDT table (all devices in devicetrees end up in the SSDT table). Can ramstage be updated to detect when multiple wake sources are registered and generate an error/warning message? Or should (can?) `ACPI_IRQ_WAKE_LEVEL_LOW()` be removed? https://review.coreboot.org/c/coreboot/+/67385/comment/61d5509a_1fe6bbf0 PS2, Line 263: The linux kernel has great support for this method. Isn't the issue that the kernel doesn't warn the user/developer that they have both wake sources enabled? Windows may be going overboard by BSODing with that configuration, but silently allowing a config that is not advised and leads to subtle bugs isn't great either. In a perfect world, a warning message is output indicating that the same device is registering multiple wake sources, which may lead to undefined behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 22:36:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update devicetree setting
by Martin Roth (Code Review) 07 Sep '22

07 Sep '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67308 ) Change subject: mb/google/skyrim/var/winterhold: Update devicetree setting ...................................................................... mb/google/skyrim/var/winterhold: Update devicetree setting Initialize winterhold devicetree. BUG=b:241196632 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67308 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 192 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 7a56f93..1e46f2b 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -1,5 +1,178 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/mendocino - device domain 0 on end + device domain 0 on + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref xhci_1 on # XHCI1 controller + chip drivers/usb/acpi + device ref xhci_1_root_hub on # XHCI1 root hub + chip drivers/usb/acpi + device ref usb3_port3 on # USB 3.1 port3 + chip drivers/usb/hub + register "desc" = ""USB Hub"" + register "name" = ""VL822"" + register "port_count" = "4" + device usb 0.0 on # VL822 USB3 hub + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(2, 2)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_42)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_8)" + register "enable_delay_ms" = "20" + device usb 3.1 on end + end + end # VL822 USB3 hub + end + end # USB 3.1 port3 + end + chip drivers/usb/acpi + device ref usb2_port3 on # USB 2 port3 + chip drivers/usb/hub + register "desc" = ""USB Hub"" + register "name" = ""VL822"" + register "port_count" = "4" + device usb 0.0 on # VL822 USB2 hub + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + end # VL822 USB2 hub + end + end # USB 2 port3 + end + end # XHCI1 root hub + end + end # XHCI1 controller + end # Internal GPP Bridge 0 to Bus A + end # domain + + device ref i2c_0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "wake" = "GEVENT_20" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7863"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_40)" + register "generic.wake" = "GEVENT_20" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C0 + device ref i2c_1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_off_delay_ms" = "1" + register "generic.reset_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_delay_ms" = "180" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_3)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end + end # I2C1 + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "2" + register "probed" = "1" + device i2c 2a on end + end + end # I2C2 + + device ref uart_1 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" + register "wake" = "GEVENT_15" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "enable_delay_ms" = "3" + device generic 0 alias fpmcu on end + end + end # UART1 + end # chip soc/amd/mendocino -- To view, visit https://review.coreboot.org/c/coreboot/+/67308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Gerrit-Change-Number: 67308 Gerrit-PatchSet: 3 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update devicetree setting
by Martin Roth (Code Review) 07 Sep '22

07 Sep '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67308 ) Change subject: mb/google/skyrim/var/winterhold: Update devicetree setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Gerrit-Change-Number: 67308 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 22:09:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/brya: Invoke power cycle of FPMCU on startup
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66915 ) Change subject: mainboard/brya: Invoke power cycle of FPMCU on startup ...................................................................... Patch Set 14: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66915/comment/0579d005_742043ad PS14, Line 7: mainboard/brya nit: `mb/google/brya` https://review.coreboot.org/c/coreboot/+/66915/comment/49091c14_96cd91a5 PS14, Line 21: the power and reset appropriately and ensures the FPMCU is unpowered for >200ms on boot. 72 chars wide https://review.coreboot.org/c/coreboot/+/66915/comment/04c220f2_352d0262 PS14, Line 24: Finger Print FPMCU ? Patchset: PS14: Conflicts with master branch -- To view, visit https://review.coreboot.org/c/coreboot/+/66915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086 Gerrit-Change-Number: 66915 Gerrit-PatchSet: 14 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 21:40:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device: Clear lane error status
by Jonathan Zhang (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Wilson Chou, Marc Jones, Nico Huber, Ryback Hung, Johnny Lin, Tim Wawrzynczak, Paul Menzel, Shuming Chu (Shuming). Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67264 ) Change subject: device: Clear lane error status ...................................................................... Patch Set 5: (2 comments) Patchset: PS2: > Well, that's the only link training triggered by corebooot. If we want to do […] Wilson, let's add a code comment accordingly: Lane error status is cleared if PCIEXP_LANE_ERR_STAT_CLEAR is set. Lane error is normal during link training, so we need to clear it. At this moment, link has been used, but for a very short duration. File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/67264/comment/7677f6e4_4fb67bf0 PS5, Line 551: printk(BIOS_DEBUG, "%s: Clear Lane Error Status.\n", dev_path(dev)); > Would anyone ever be interested in the value it may have had before it gets cleared? Wilson, let's print the current value while we clear it. -- To view, visit https://review.coreboot.org/c/coreboot/+/67264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5 Gerrit-Change-Number: 67264 Gerrit-PatchSet: 5 Gerrit-Owner: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 21:37:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/smbus: SC16IS750 I2C to UART converter chip initialization
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Felix Singer, Ahamed Husni. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67342 ) Change subject: drivers/smbus: SC16IS750 I2C to UART converter chip initialization ...................................................................... Patch Set 6: (1 comment) File src/drivers/smbus/i2c_smbus_console.c: https://review.coreboot.org/c/coreboot/+/67342/comment/3e4caa35_3f87d0bd PS6, Line 10: #if (CONFIG(CONSOLE_I2C_SMBUS) && (ENV_ROMSTAGE || ENV_BOOTBLOCK)) : early_pch_init(); : #endif : #if (CONFIG(SC16IS750_INIT) && (ENV_ROMSTAGE || ENV_BOOTBLOCK)) : sc16is750_init(); : #endif I think you could refactor this like ``` if (ENV_ROMSTAGE || ENV_BOOTBLOCK) { if (CONFIG(CONSOLE_I2C_SMBUS)) early_pch_init(); if (CONFIG(SC16IS750_INIT)) sc16is750_init(); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/67342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib31188b8c0f9b0ce9454da984e630eca9101d145 Gerrit-Change-Number: 67342 Gerrit-PatchSet: 6 Gerrit-Owner: Ahamed Husni <ahamedhusni73(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Ahamed Husni <ahamedhusni73(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 21:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/console: attach smbus console driver
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Felix Singer, Ahamed Husni. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67341 ) Change subject: src/console: attach smbus console driver ...................................................................... Patch Set 4: (1 comment) File src/drivers/smbus/Makefile.inc: https://review.coreboot.org/c/coreboot/+/67341/comment/5d4c0576_ebdf5b39 PS4, Line 2: bootblock-y += i2c_smbus_console.c : romstage-y += i2c_smbus_console.c : ramstage-y += i2c_smbus_console.c why not `all-y += ... ` is there some reason not to use this in other stages? -- To view, visit https://review.coreboot.org/c/coreboot/+/67341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9bf64e59d529253bfdcdfa565bb2bb92975728 Gerrit-Change-Number: 67341 Gerrit-PatchSet: 4 Gerrit-Owner: Ahamed Husni <ahamedhusni73(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Ahamed Husni <ahamedhusni73(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 21:29:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add WWAN ACPI support
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67336 ) Change subject: mb/google/rex: Add WWAN ACPI support ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rex/variants/rex0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67336/comment/ad1a82a6_169ea4ff PS2, Line 232: # register "reset_delay_ms" = "1000" is this needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/67336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6 Gerrit-Change-Number: 67336 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 21:19:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Dmitry Torokhov (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Raul Rangel, Tim Wawrzynczak. Dmitry Torokhov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 21:16:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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