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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table
......................................................................
mb/google/brya/var/kinox: Modify fan speed/duty table
Modify fan speed/duty table follow "Duty table.xlsx".
BUG=b:244262869
TEST=Boot to ChromeOS. Using SDV system, enter duty vaule,and then
system feedback fan speed.
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458
---
M src/mainboard/google/brya/variants/kinox/overridetree.cb
1 file changed, 36 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/67307/4
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Ed Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66819 )
Change subject: Recently published Intel CedarIslandFSP binary contains PE images in FSP-M and FSP-S. This causes coreboot boot hang on DeltaLake servers.
......................................................................
Patch Set 1:
(11 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66819/comment/b4527454_48485638
PS1, Line 8: FSP-M and FSP-S. This causes coreboot boot hang on DeltaLake servers.
> You may also want to point to FSP spec that boot loader needs support PE image format.
I tried to search for PE and TE in the FSP spec but could not find the info in the spec anywhere. Do you have that information handy, else it may not exist in the spec to add as a reference?
https://review.coreboot.org/c/coreboot/+/66819/comment/8f1bc7f1_3b4c13f1
PS1, Line 10: The change required to add support for pe_relocate in fsp-relocate.c
> Suppose to add message stating that PE32 format support is added, but PE64 format support is left fo […]
Done
https://review.coreboot.org/c/coreboot/+/66819/comment/07965ace_edc9d6f5
PS1, Line 15: This code is tested with FSP version 33A for DeltaLake boot.
> You could add test descriptions after "TEST=".
Done
Patchset:
PS1:
Updated commit and responded to all comments
File src/commonlib/fsp_relocate.c:
https://review.coreboot.org/c/coreboot/+/66819/comment/82bcf849_79b94d83
PS1, Line 145: /* FSP_INFO_HEADER at first file in FV within first RAW section. */
> FSP_INFO_HEADER (is located) at
Done
https://review.coreboot.org/c/coreboot/+/66819/comment/43763486_43669537
PS1, Line 211: printk(FSP_DBG_LVL, "FSP InfoHdr Image Base is %x\n", image_base);
> Does it make sense to say "FSP PE32 InfoHdr Image Base is... […]
FspInfoHdr is for the entire FSP image, not just for PE. There is one per FSP.
https://review.coreboot.org/c/coreboot/+/66819/comment/c016799f_2e27bfc2
PS1, Line 242: printk(FSP_DBG_LVL, "%d Relocs for RVA %x\n", rnum, vaddr);
> Suggest to add a tab \t to make the debug message more clear.
Done
https://review.coreboot.org/c/coreboot/+/66819/comment/ecafd0a4_9cf83392
PS1, Line 249: printk(FSP_DBG_LVL, "reloc type %x offset %x aoff %x, base-0x%x\n",
> suggest to add two tabs \t\t
Done
https://review.coreboot.org/c/coreboot/+/66819/comment/e75d1740_10f9978d
PS1, Line 277: // printk(FSP_DBG_LVL, "FSP InfoHdr Image Base updated to %lx\n", new_addr);
> These comments could be deleted.
Done
https://review.coreboot.org/c/coreboot/+/66819/comment/5ce34ccf_800e369b
PS1, Line 650: printk(FSP_DBG_LVL, "PE image at offset %zx\n",
> PE32 image
Done
https://review.coreboot.org/c/coreboot/+/66819/comment/8088044a_52c5de40
PS1, Line 653: }
> Suggest catching the case where the type is neither EFI_SECTION_TE nor EFI_SECTION_PE32.
This suggestion does not work. It halts BIOS execution for some reason. Perhaps there are other sections that are not either of these and don't need relocation but we cannot return an error from this loop since we need to still calculate those offsets for the next one that might need relocation.
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Change subject: Recently published Intel CedarIslandFSP binary contains PE images in FSP-M and FSP-S. This causes coreboot boot hang on DeltaLake servers.
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158189):
https://review.coreboot.org/c/coreboot/+/66819/comment/4c1577db_f2e77d18
PS2, Line 6:
Possible long commit subject (prefer a maximum 65 characters)
File src/commonlib/fsp_relocate.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158189):
https://review.coreboot.org/c/coreboot/+/66819/comment/e1051fad_9e5e2e86
PS2, Line 223: roffset = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress);
line length of 103 exceeds 96 columns
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Hello Arthur Heymans, build bot (Jenkins), Furquan Shaikh, Subrata Banik, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Julian Schroeder, Nathaniel L Desimone, Felix Held, Isaac W Oram,
I'd like you to reexamine a change. Please visit
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Change subject: Recently published Intel CedarIslandFSP binary contains PE images in FSP-M and FSP-S. This causes coreboot boot hang on DeltaLake servers.
......................................................................
Recently published Intel CedarIslandFSP binary contains PE images in
FSP-M and FSP-S. This causes coreboot boot hang on DeltaLake servers.
The change required to add support for pe_relocate in fsp-relocate.c
I had to move a few functions to top of file as they need to be used
by pe_relocate but were placed below the te_relocate function. I chose
to place pe_relocate function next to te_relocate.
The code supports PE32 format, not PE64, at this time.
TEST=
This code is tested with FSP version 33A for DeltaLake boot.
Change-Id: I01e2c123d74f735a647b994aa66419c9796f193e
Signed-off-by: Eddie Sharma <aeddiesharma(a)fb.com>
---
M src/commonlib/fsp_relocate.c
1 file changed, 214 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/66819/2
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Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> adding julius werner, can you please quote the reason for not using gscvd on CR50 devices by default […]
GSC verification is a feature that will first roll out with Ti50. There is a Cr50 implementation but I believe(?) we ended up deciding not to use that. I think it was added to guybrush here before that decision was made, so taking it back out now seems reasonable.
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67336 )
Change subject: mb/google/rex: Add WWAN ACPI support
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67336/comment/c1498fb2_246361f3
PS2, Line 232: # register "reset_delay_ms" = "1000"
> is this needed?
IIRC, we need 10s wait for FW ready again like power on.
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Change subject: mb/google/rex: Set up MIPI cameras via ACPI
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67085/comment/26799110_ad4c86a9
PS15, Line 314: Controls
> clock control seems to be missed for UCAM. […]
UCAM uses its own clock while WCAM gets the clock from host.
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Change subject: mb/google/rex: Set up MIPI cameras via ACPI
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67085/comment/90da8c74_51c46221
PS15, Line 314: Controls
clock control seems to be missed for UCAM.
Don't we need to control clock control like WCAM?
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