coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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4674 discussions

[M] Change in coreboot[master]: mb/prodrive/hermes: Allow using the Intel iGPU as primary
by Angel Pons (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Christian Walter. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62649 ) Change subject: mb/prodrive/hermes: Allow using the Intel iGPU as primary ...................................................................... Patch Set 7: (3 comments) File src/mainboard/prodrive/hermes/mainboard.c: https://review.coreboot.org/c/coreboot/+/62649/comment/cabc7cb7_7eed5969 PS1, Line 262: internale_gfx > There's a typo, and enum type is unused anyway. […] Done https://review.coreboot.org/c/coreboot/+/62649/comment/365601d3_b4767b0e PS1, Line 280: mainboard_configure_internal_gfx > Why not call this from `mainboard_early()`? To answer myself: the right place to call this from is when entering BS_DEV_RESOURCES. https://review.coreboot.org/c/coreboot/+/62649/comment/60de5580_19077bbe PS1, Line 283: board_cfg > This can be NULL. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Gerrit-Change-Number: 62649 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 06 Sep 2022 19:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/apob: Add hashed APOB support
by Fred Reitberger (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67301 ) Change subject: soc/amd/common/block/apob: Add hashed APOB support ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67301/comment/78c65285_8b9f1e99 PS4, Line 15: chausie > I'm sure you could easily get one ;) […] The ABL will tell us exactly how big the APOB is in the header field. We reserve at least that much, probably rounded to the next biggest erasable block size (4k usually). It's likely there is space at the end for this, but until I can test on actual hardware it's only a guess. File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/67301/comment/56c8101a_fbe35792 PS4, Line 57: apob_header_ptr->size + MRC_HASH_SIZE > We know this via `CONFIG_PSP_APOB_DRAM_SIZE` don't we? The actual size for Mendocino looks to be 0x1db18 which is why we reserved 0x1e000 (120k). This leaves 1256 bytes free, of which the hash will use 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/67301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Gerrit-Change-Number: 67301 Gerrit-PatchSet: 5 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 19:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Test: Checkpatch should complain about having phase names
by Martin L Roth (Code Review) 06 Sep '22

06 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67383 ) Change subject: Test: Checkpatch should complain about having phase names ...................................................................... Test: Checkpatch should complain about having phase names 1: proto 2: evt 3: dvt 4: pvt 5: mp 6: random line Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I212df29a1cce3ae3e54c128a4bf44201c67a6318 --- A test_patch 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/67383/1 diff --git a/test_patch b/test_patch new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/test_patch -- To view, visit https://review.coreboot.org/c/coreboot/+/67383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212df29a1cce3ae3e54c128a4bf44201c67a6318 Gerrit-Change-Number: 67383 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src: De-conflict CALIBRATION_REGION definitions
by Martin L Roth (Code Review) 06 Sep '22

06 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67382 ) Change subject: src: De-conflict CALIBRATION_REGION definitions ...................................................................... src: De-conflict CALIBRATION_REGION definitions Change the name of the CALIBRATION_REGION definitions used in two separate locations. This conflict was causing an error for the lint-001-no-global-config-in-romstage test. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/common/memory.c 2 files changed, 24 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/67382/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index b9c0d2c..0a13a3d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -13,16 +13,16 @@ #include "early_init.h" /* This must be defined in chromeos.fmd in same name and size. */ -#define CALIBRATION_REGION "RW_DDR_TRAINING" -#define CALIBRATION_REGION_SIZE 0x2000 +#define CAL_REGION_RW_DDR_TRAINING "RW_DDR_TRAINING" +#define CAL_REGION_RW_DDR_TRAINING_SIZE 0x2000 -_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, - "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); +_Static_assert(sizeof(struct dramc_param) <= CAL_REGION_RW_DDR_TRAINING_SIZE, + "sizeof(struct dramc_param) exceeds " CAL_REGION_RW_DDR_TRAINING); static bool read_calibration_data_from_flash(struct dramc_param *dparam) { const size_t length = sizeof(*dparam); - size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + size_t ret = fmap_read_area(CAL_REGION_RW_DDR_TRAINING, dparam, length); printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n", __func__, ret, length); @@ -32,7 +32,7 @@ static bool write_calibration_data_to_flash(const struct dramc_param *dparam) { const size_t length = sizeof(*dparam); - size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + size_t ret = fmap_overwrite_area(CAL_REGION_RW_DDR_TRAINING, dparam, length); printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n", __func__, ret, length); diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 1771313..f3f784e 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -15,11 +15,11 @@ #include <timer.h> /* This must be defined in chromeos.fmd in same name and size. */ -#define CALIBRATION_REGION "RW_MRC_CACHE" -#define CALIBRATION_REGION_SIZE 0x2000 +#define CAL_REGION_RW_MRC_CACHE "RW_MRC_CACHE" +#define CAL_REGION_RW_MRC_CACHE_SIZE 0x2000 -_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, - "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); +_Static_assert(sizeof(struct dramc_param) <= CAL_REGION_RW_MRC_CACHE_SIZE, + "sizeof(struct dramc_param) exceeds " CAL_REGION_RW_MRC_CACHE); const char *get_dram_geometry_str(u32 ddr_geometry); const char *get_dram_type_str(u32 ddr_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/67382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 Gerrit-Change-Number: 67382 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/block/apob: Add hashed APOB support
by Raul Rangel (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67301 ) Change subject: soc/amd/common/block/apob: Add hashed APOB support ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67301/comment/f22ea7ab_95955ddf PS4, Line 15: chausie > I don't have a guybrush to test with. […] I'm sure you could easily get one ;) I suspect it won't. `PSP_APOB_DRAM_SIZE` is defined as 64K, and the `RW_MRC_CACHE` is defined as 64K as well. I'm not sure what `apob_header_ptr->size` actually contains though. If it was smaller then the 64K it might work. File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/67301/comment/78e93186_0c924fa8 PS4, Line 57: apob_header_ptr->size + MRC_HASH_SIZE > If this check fails, the device can still boot. The actual size is not known at compile time. […] We know this via `CONFIG_PSP_APOB_DRAM_SIZE` don't we? -- To view, visit https://review.coreboot.org/c/coreboot/+/67301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Gerrit-Change-Number: 67301 Gerrit-PatchSet: 5 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 18:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/acpi: Remove erroneous _PR0/_PR3
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Anil Kumar K, Cliff Huang, Subrata Banik, Selma Bensaid. Hello build bot (Jenkins), Anil Kumar K, Cliff Huang, Subrata Banik, Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67212 to look at the new patch set (#2). Change subject: mb/google/brya/acpi: Remove erroneous _PR0/_PR3 ...................................................................... mb/google/brya/acpi: Remove erroneous _PR0/_PR3 The Linux kernel runtime D3 framework expects a PCIe device to have a power resource in order to be properly power-manageable. The _PR0/_PR3 values were pointing at the PEG0 Device, which is not a PowerResource, so this must have confused the RTD3 framework and RTD3 was not functional. Removing the _PR0/_PR3 fixes the problem. BUG=b:243888246 TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control; sleep 10; echo on > /sys/bus/pci/devices/0000:01:00.0/power/control After this there are no longer errors seen in dmesg about failing to place the device into D0. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea --- M src/mainboard/google/brya/acpi/nvjt.asl M src/mainboard/google/brya/acpi/nvop.asl M src/mainboard/google/brya/acpi/power.asl 3 files changed, 32 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/67212/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea Gerrit-Change-Number: 67212 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/variants/skolas: Set power limit values
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Bora Guvendik, Selma Bensaid, Sumeet R Pawnikar, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67375 ) Change subject: mb/google/brya/variants/skolas: Set power limit values ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Gerrit-Change-Number: 67375 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 18:35:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Reka Norman, Andrey Petrov. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67334 ) Change subject: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Gerrit-Change-Number: 67334 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 18:33:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/hermes: Add libgfxinit support
by build bot (Jenkins) (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Christian Walter. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62648 ) Change subject: mb/prodrive/hermes: Add libgfxinit support ...................................................................... Patch Set 7: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158164): https://review.coreboot.org/c/coreboot/+/62648/comment/7fbbcc8b_04ae9ca3 PS7, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/62648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib71d06e1d83cd26b0fef37acc64f699c452c13dc Gerrit-Change-Number: 62648 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 06 Sep 2022 18:30:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: allocator_v4: Use memranges only for toplevel
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Bill XIE, Nico Huber, Eric Lai, Werner Zeh, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65420 ) Change subject: allocator_v4: Use memranges only for toplevel ...................................................................... Patch Set 8: Code-Review+2 (2 comments) Patchset: PS8: I think this needs a rebase now File src/device/resource_allocator_v4.c: https://review.coreboot.org/c/coreboot/+/65420/comment/9cc50639_8647ee0c PS7, Line 437: void assign_resource_cb(void *param, struct device *dev, struct resource *res) : { : /* We have to filter the same resources as update_bridge_resource(). */ : if (!res->size || !res->limit) : return; : : assign_resource(res, *(const resource_t *)param + res->base, dev); : } > More or less common practice in Ada ;) with very similar semantics, now that […] I think it's OK; I think we could probably actually this technique a little more if we so wanted, it's not terribly hard to understand as long as there is no use of what would look like captured variables. -- To view, visit https://review.coreboot.org/c/coreboot/+/65420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70c700318a85f6760f27597730bc9c9a86dbe6b3 Gerrit-Change-Number: 65420 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 18:30:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit September 2022