coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/amd/common/block/apob: Add hashed APOB support
by Martin Roth (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67301 ) Change subject: soc/amd/common/block/apob: Add hashed APOB support ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67301/comment/faaca76f_fe4ef7de PS4, Line 15: chausie > The ABL will tell us exactly how big the APOB is in the header field. […] I don't think there's a problem with getting this patch in before testing on guybrush. Since this needs to be enabled in the config, we just shouldn't push a patch enabling it for cezanne until then. -- To view, visit https://review.coreboot.org/c/coreboot/+/67301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Gerrit-Change-Number: 67301 Gerrit-PatchSet: 5 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 20:03:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade cmake and llvm
by build bot (Jenkins) (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67367 ) Change subject: crossgcc: Upgrade cmake and llvm ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158171): https://review.coreboot.org/c/coreboot/+/67367/comment/c789ae84_8d7e9b94 PS2, Line 12: Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Duplicate signature -- To view, visit https://review.coreboot.org/c/coreboot/+/67367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Gerrit-Change-Number: 67367 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 06 Sep 2022 19:10:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/prodrive/hermes: Allow using the Intel iGPU as primary
by Angel Pons (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Christian Walter. Angel Pons has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/62649 ) Change subject: mb/prodrive/hermes: Allow using the Intel iGPU as primary ...................................................................... mb/prodrive/hermes: Allow using the Intel iGPU as primary Configure the Intel iGPU as primary video adapter if enabled according to EEPROM settings. The default is to use the ASPEED BMC as primary video adapter, which only has a VGA output and the remote KVM output. TODO: Figure out why iGPU video stops working after booting Linux and doing a warm (no power cycle) reboot. TEST=Test that DP and HDMI outputs work in pre-OS and on Linux using the Poseidon piggy-back board, which has two DisplayPort outputs and one HDMI output from a LSPCON. Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/romstage.c 3 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/62649/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Gerrit-Change-Number: 62649 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: crossgcc: Upgrade cmake and llvm
by Elyes Haouas (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67367 to look at the new patch set (#2). Change subject: crossgcc: Upgrade cmake and llvm ...................................................................... crossgcc: Upgrade cmake and llvm Upgrade cmake to version 3.24.1 and llvm to version 15.0.0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-14.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-14.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.23.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.24.1.tar.gz.cksum D util/crossgcc/sum/compiler-rt-14.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum D util/crossgcc/sum/llvm-14.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum 11 files changed, 20 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/67367/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Gerrit-Change-Number: 67367 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/prodrive/hermes: Allow using the Intel iGPU as primary
by Angel Pons (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Christian Walter. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62649 ) Change subject: mb/prodrive/hermes: Allow using the Intel iGPU as primary ...................................................................... Patch Set 7: (3 comments) File src/mainboard/prodrive/hermes/mainboard.c: https://review.coreboot.org/c/coreboot/+/62649/comment/cabc7cb7_7eed5969 PS1, Line 262: internale_gfx > There's a typo, and enum type is unused anyway. […] Done https://review.coreboot.org/c/coreboot/+/62649/comment/365601d3_b4767b0e PS1, Line 280: mainboard_configure_internal_gfx > Why not call this from `mainboard_early()`? To answer myself: the right place to call this from is when entering BS_DEV_RESOURCES. https://review.coreboot.org/c/coreboot/+/62649/comment/60de5580_19077bbe PS1, Line 283: board_cfg > This can be NULL. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Gerrit-Change-Number: 62649 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 06 Sep 2022 19:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/apob: Add hashed APOB support
by Fred Reitberger (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67301 ) Change subject: soc/amd/common/block/apob: Add hashed APOB support ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67301/comment/78c65285_8b9f1e99 PS4, Line 15: chausie > I'm sure you could easily get one ;) […] The ABL will tell us exactly how big the APOB is in the header field. We reserve at least that much, probably rounded to the next biggest erasable block size (4k usually). It's likely there is space at the end for this, but until I can test on actual hardware it's only a guess. File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/67301/comment/56c8101a_fbe35792 PS4, Line 57: apob_header_ptr->size + MRC_HASH_SIZE > We know this via `CONFIG_PSP_APOB_DRAM_SIZE` don't we? The actual size for Mendocino looks to be 0x1db18 which is why we reserved 0x1e000 (120k). This leaves 1256 bytes free, of which the hash will use 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/67301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Gerrit-Change-Number: 67301 Gerrit-PatchSet: 5 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 19:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Test: Checkpatch should complain about having phase names
by Martin L Roth (Code Review) 06 Sep '22

06 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67383 ) Change subject: Test: Checkpatch should complain about having phase names ...................................................................... Test: Checkpatch should complain about having phase names 1: proto 2: evt 3: dvt 4: pvt 5: mp 6: random line Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I212df29a1cce3ae3e54c128a4bf44201c67a6318 --- A test_patch 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/67383/1 diff --git a/test_patch b/test_patch new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/test_patch -- To view, visit https://review.coreboot.org/c/coreboot/+/67383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212df29a1cce3ae3e54c128a4bf44201c67a6318 Gerrit-Change-Number: 67383 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src: De-conflict CALIBRATION_REGION definitions
by Martin L Roth (Code Review) 06 Sep '22

06 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67382 ) Change subject: src: De-conflict CALIBRATION_REGION definitions ...................................................................... src: De-conflict CALIBRATION_REGION definitions Change the name of the CALIBRATION_REGION definitions used in two separate locations. This conflict was causing an error for the lint-001-no-global-config-in-romstage test. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/common/memory.c 2 files changed, 24 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/67382/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index b9c0d2c..0a13a3d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -13,16 +13,16 @@ #include "early_init.h" /* This must be defined in chromeos.fmd in same name and size. */ -#define CALIBRATION_REGION "RW_DDR_TRAINING" -#define CALIBRATION_REGION_SIZE 0x2000 +#define CAL_REGION_RW_DDR_TRAINING "RW_DDR_TRAINING" +#define CAL_REGION_RW_DDR_TRAINING_SIZE 0x2000 -_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, - "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); +_Static_assert(sizeof(struct dramc_param) <= CAL_REGION_RW_DDR_TRAINING_SIZE, + "sizeof(struct dramc_param) exceeds " CAL_REGION_RW_DDR_TRAINING); static bool read_calibration_data_from_flash(struct dramc_param *dparam) { const size_t length = sizeof(*dparam); - size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + size_t ret = fmap_read_area(CAL_REGION_RW_DDR_TRAINING, dparam, length); printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n", __func__, ret, length); @@ -32,7 +32,7 @@ static bool write_calibration_data_to_flash(const struct dramc_param *dparam) { const size_t length = sizeof(*dparam); - size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + size_t ret = fmap_overwrite_area(CAL_REGION_RW_DDR_TRAINING, dparam, length); printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n", __func__, ret, length); diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 1771313..f3f784e 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -15,11 +15,11 @@ #include <timer.h> /* This must be defined in chromeos.fmd in same name and size. */ -#define CALIBRATION_REGION "RW_MRC_CACHE" -#define CALIBRATION_REGION_SIZE 0x2000 +#define CAL_REGION_RW_MRC_CACHE "RW_MRC_CACHE" +#define CAL_REGION_RW_MRC_CACHE_SIZE 0x2000 -_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, - "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); +_Static_assert(sizeof(struct dramc_param) <= CAL_REGION_RW_MRC_CACHE_SIZE, + "sizeof(struct dramc_param) exceeds " CAL_REGION_RW_MRC_CACHE); const char *get_dram_geometry_str(u32 ddr_geometry); const char *get_dram_type_str(u32 ddr_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/67382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 Gerrit-Change-Number: 67382 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/block/apob: Add hashed APOB support
by Raul Rangel (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67301 ) Change subject: soc/amd/common/block/apob: Add hashed APOB support ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67301/comment/f22ea7ab_95955ddf PS4, Line 15: chausie > I don't have a guybrush to test with. […] I'm sure you could easily get one ;) I suspect it won't. `PSP_APOB_DRAM_SIZE` is defined as 64K, and the `RW_MRC_CACHE` is defined as 64K as well. I'm not sure what `apob_header_ptr->size` actually contains though. If it was smaller then the 64K it might work. File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/67301/comment/78e93186_0c924fa8 PS4, Line 57: apob_header_ptr->size + MRC_HASH_SIZE > If this check fails, the device can still boot. The actual size is not known at compile time. […] We know this via `CONFIG_PSP_APOB_DRAM_SIZE` don't we? -- To view, visit https://review.coreboot.org/c/coreboot/+/67301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Gerrit-Change-Number: 67301 Gerrit-PatchSet: 5 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 18:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/acpi: Remove erroneous _PR0/_PR3
by Tim Wawrzynczak (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Anil Kumar K, Cliff Huang, Subrata Banik, Selma Bensaid. Hello build bot (Jenkins), Anil Kumar K, Cliff Huang, Subrata Banik, Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67212 to look at the new patch set (#2). Change subject: mb/google/brya/acpi: Remove erroneous _PR0/_PR3 ...................................................................... mb/google/brya/acpi: Remove erroneous _PR0/_PR3 The Linux kernel runtime D3 framework expects a PCIe device to have a power resource in order to be properly power-manageable. The _PR0/_PR3 values were pointing at the PEG0 Device, which is not a PowerResource, so this must have confused the RTD3 framework and RTD3 was not functional. Removing the _PR0/_PR3 fixes the problem. BUG=b:243888246 TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control; sleep 10; echo on > /sys/bus/pci/devices/0000:01:00.0/power/control After this there are no longer errors seen in dmesg about failing to place the device into D0. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea --- M src/mainboard/google/brya/acpi/nvjt.asl M src/mainboard/google/brya/acpi/nvop.asl M src/mainboard/google/brya/acpi/power.asl 3 files changed, 32 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/67212/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea Gerrit-Change-Number: 67212 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2022