coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

1 participants
4678 discussions

[S] Change in coreboot[master]: mb/prodrive/atlas: Configure Acoustic noise mitigation
by Lean Sheng Tan (Code Review) 06 Sep '22

06 Sep '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67380 ) Change subject: mb/prodrive/atlas: Configure Acoustic noise mitigation ...................................................................... mb/prodrive/atlas: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8 --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/67380/1 diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 0a85541..d458dfa 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -22,6 +22,13 @@ [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + # USB configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" -- To view, visit https://review.coreboot.org/c/coreboot/+/67380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8 Gerrit-Change-Number: 67380 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: util/lint/lint-stable-019-header-files: add test
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67351 ) Change subject: util/lint/lint-stable-019-header-files: add test ...................................................................... util/lint/lint-stable-019-header-files: add test Add a test to make sure that the linter fails correctly. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/lint-stable-019-header-files 1 file changed, 37 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/util/lint/lint-stable-019-header-files b/util/lint/lint-stable-019-header-files index 6495d15..f73e0e7 100755 --- a/util/lint/lint-stable-019-header-files +++ b/util/lint/lint-stable-019-header-files @@ -11,6 +11,28 @@ HEADER_FILES="k\?config rules compiler" +TESTFILE1="src/lib/version.c" +TESTFILE2="src/lib/string.c" +TESTFILE3="src/lib/malloc.c" +TESTFILE4="src/lib/hardwaremain.c" +EXPECTED_FAILURES=4 + +# Configure to make sure tests fail +if [ "$1" = "--test" ]; then + sed -i.bak "s|^.*SPDX-License-Identifier.*|&\n\n#include <config.h>\n|" "${TESTFILE1}" + sed -i.bak "s|^.*SPDX-License-Identifier.*|&\n\n#include \"kconfig.h\"\n|" "${TESTFILE2}" + sed -i.bak "s|^.*SPDX-License-Identifier.*|&\n\n#include \"compiler.h\"\n|" "${TESTFILE3}" + sed -i.bak "s|^.*SPDX-License-Identifier.*|&\n\n#include <rules.h>\n|" "${TESTFILE4}" + echo "Expect ${EXPECTED_FAILURES} failures." + exit 0 +elif [ "$1" = "--reset" ]; then + mv "${TESTFILE1}.bak" "${TESTFILE1}" + mv "${TESTFILE2}.bak" "${TESTFILE2}" + mv "${TESTFILE3}.bak" "${TESTFILE3}" + mv "${TESTFILE4}.bak" "${TESTFILE4}" + exit 0 +fi + # Use git grep if the code is in a git repo, otherwise use grep. if [ -n "$(command -v git)" ] && \ [ "$(git rev-parse --is-inside-work-tree 2>/dev/null)" = "true" ] -- To view, visit https://review.coreboot.org/c/coreboot/+/67351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc Gerrit-Change-Number: 67351 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: util/lint: Add rules.h & compiler.h to 019-header-files linter
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67350 ) Change subject: util/lint: Add rules.h & compiler.h to 019-header-files linter ...................................................................... util/lint: Add rules.h & compiler.h to 019-header-files linter The rules.h & compiler.h includes were removed in previous commits, so add the checks to keep them out to the linter. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/lint-stable-019-header-files 1 file changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/util/lint/lint-stable-019-header-files b/util/lint/lint-stable-019-header-files index c839dc5..6495d15 100755 --- a/util/lint/lint-stable-019-header-files +++ b/util/lint/lint-stable-019-header-files @@ -9,8 +9,7 @@ INCLUDED_DIRS='^src/' EXCLUDED_FILES='src/include/kconfig.h' -# TODO: Add rules when those patches are complete -HEADER_FILES="k*config" +HEADER_FILES="k\?config rules compiler" # Use git grep if the code is in a git repo, otherwise use grep. if [ -n "$(command -v git)" ] && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/67350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d Gerrit-Change-Number: 67350 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/soc/intel: remove force-included header compiler.h from file
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67349 ) Change subject: src/soc/intel: remove force-included header compiler.h from file ...................................................................... src/soc/intel: remove force-included header compiler.h from file The header file `compiler.h` is automatically included in the build by the top level makefile using the command: `-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`. Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/scs/early_mmc.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index caee7d9..4e76533 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -5,7 +5,6 @@ #include <commonlib/storage/sd_mmc.h> #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> -#include <compiler.h> #include <console/console.h> #include <device/pci.h> #include <intelblocks/mmc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/67349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Gerrit-Change-Number: 67349 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src: remove force-included header rules.h from individual files
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67348 ) Change subject: src: remove force-included header rules.h from individual files ...................................................................... src: remove force-included header rules.h from individual files The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/arm/armv7/cpu.S M src/arch/arm/include/arch/header.ld M src/arch/arm64/include/arch/header.ld M src/arch/riscv/include/arch/header.ld M src/arch/x86/assembly_entry.S M src/arch/x86/include/arch/header.ld M src/include/cbfs_glue.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/nvidia/tegra210/memlayout.ld 9 files changed, 20 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index bc3ebd9..3459fc6 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -6,7 +6,6 @@ */ #include <arch/asm.h> -#include <rules.h> /* * Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0] diff --git a/src/arch/arm/include/arch/header.ld b/src/arch/arm/include/arch/header.ld index cb69ba3..b1e1f9d 100644 --- a/src/arch/arm/include/arch/header.ld +++ b/src/arch/arm/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index 4f37176..c6d48e7 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index d814772..ddb618c 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_ARCH(riscv) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 6e73027..79d6e19 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 4e78ae7..5b380fa 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - PHDRS { to_load PT_LOAD; diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h index 652cf1b..d4fe367 100644 --- a/src/include/cbfs_glue.h +++ b/src/include/cbfs_glue.h @@ -6,7 +6,6 @@ #include <commonlib/region.h> #include <console/console.h> #include <security/vboot/misc.h> -#include <rules.h> /* * This flag prevents linking hashing functions into stages where they're not required. We don't diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 1c905a4..552ba15 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#include <rules.h> #include <intelblocks/msr.h> .section .init, "ax", @progbits diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index 42f2164..d9d7070 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <memlayout.h> -#include <rules.h> #include <arch/header.ld> -- To view, visit https://review.coreboot.org/c/coreboot/+/67348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Gerrit-Change-Number: 67348 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/hp/z220_series: Add configs for integrated XHCI
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67089 ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/hp/z220_series: Add configs for integrated XHCI ...................................................................... mb/hp/z220_series: Add configs for integrated XHCI Without these, all SuperSpeed ports are wired to EHCI #2. "superspeed_capable_ports" and "xhci_switchable_ports" should fit both CMT and SFF variants, while "xhci_overcurrent_mapping" should be consistent with the first 4 elements of mainboard_usb_ports[]. With this commit, SuperSpeed devices plugged in SuperSpeed ports are wired to the XHCI on my own Z220 SFF. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/hp/z220_series/devicetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index ea8fad9..bcacf71 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -33,6 +33,9 @@ register "sata_interface_speed_support" = "0x3" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x0000000f" device pci 14.0 on end # xHCI device pci 16.0 on end # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Gerrit-Change-Number: 67089 Gerrit-PatchSet: 10 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: configs/config.prodrive_hermes: Fix typo
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67343 ) Change subject: configs/config.prodrive_hermes: Fix typo ...................................................................... configs/config.prodrive_hermes: Fix typo Remove extra 'o' in "Tech*o*nologies". Change-Id: Icf24e00fb895a670ea798f64a79035d858ec0d4f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67343 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M configs/config.prodrive_hermes 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/configs/config.prodrive_hermes b/configs/config.prodrive_hermes index 35c617c..ce8d687 100644 --- a/configs/config.prodrive_hermes +++ b/configs/config.prodrive_hermes @@ -1,7 +1,7 @@ # Settings used by Prodrive to build coreboot for the Hermes CONFIG_VENDOR_PRODRIVE=y CONFIG_BOARD_PRODRIVE_HERMES=y -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Techonologies B.V." +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Technologies B.V." CONFIG_POST_IO=y CONFIG_USE_LEGACY_8254_TIMER=y CONFIG_HERMES_USES_SPS_FIRMWARE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/67343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf24e00fb895a670ea798f64a79035d858ec0d4f Gerrit-Change-Number: 67343 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: util/amdfwtool: Add options to separate signed firmwares
by Karthik Ramasubramanian (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59866 ) Change subject: util/amdfwtool: Add options to separate signed firmwares ...................................................................... Patch Set 7: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/59866/comment/c4bab72e_78333313 PS2, Line 825: pspdir->entries[count].addr = fw_table[i].addr_signed; : bytes = fw_table[i].file_size; > Address and size are filled in the psp directory entry. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Gerrit-Change-Number: 59866 Gerrit-PatchSet: 7 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 17:51:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim: Enable amdfw separation
by Karthik Ramasubramanian (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Nien, Martin Roth, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67261 to look at the new patch set (#4). Change subject: mb/google/skyrim: Enable amdfw separation ...................................................................... mb/google/skyrim: Enable amdfw separation Select the config to separate the AMDFW binary from the verified boot section. BUG=b:203597980 TEST=Build Skyrim BIOS image and boot to OS with PSP verstage passing the hash table and PSP verifying the binaries against the hash table. Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/chromeos.fmd 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/67261/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/67261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d Gerrit-Change-Number: 67261 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table
by Karthik Ramasubramanian (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Karthik Ramasubramanian has uploaded a new patch set (#5) to the change originally created by Kangheui Won. ( https://review.coreboot.org/c/coreboot/+/60291 ) Change subject: soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table ...................................................................... soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table Copy AMD PSP fw hash table into memory, then pass it to the PSP. The PSP will use this hash to verify it's the correct firmware bundled with coreboot build and not replaced. BUG=b:203597980 TEST=Build Skyrim BIOS image with the hash table and boot to OS after PSP verified the binaries against the hash table. Change-Id: I84bea97c89620d0388b27891a898ffde77052239 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/mendocino/psp_verstage/chipset.c 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/60291/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/60291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bea97c89620d0388b27891a898ffde77052239 Gerrit-Change-Number: 60291 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2022