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Change subject: mb/google/skyrim/var/winterhold: Add gpio override settings
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Patch Set 6: Code-Review+2
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Change subject: soc/amd/common/block/apob: Add hashed APOB support
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Patch Set 4: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67301/comment/db1c388c_8993512a
PS4, Line 15: chausie
Can you try it on a guybrush device?
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/67301/comment/e203a733_f248556b
PS4, Line 57: apob_header_ptr->size + MRC_HASH_SIZE
You could probably do this as a `_Static_assert` above
https://review.coreboot.org/c/coreboot/+/67301/comment/dd58bcc8_c1dc8df4
PS4, Line 195: xxh64
I wonder if coreboot has an existing has function. I know vboot has sha2*, but now sure if that's easy to use.
https://review.coreboot.org/c/coreboot/+/67301/comment/e9176f71_7ab090ed
PS4, Line 214: !update_needed &&
You can probably skip this part since `apob_rom` will be `NULL` if `update_needed == true`
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Change subject: drivers/smbus: SC16IS750 I2C to UART converter chip initialization
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Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67342/comment/eb16c546_d9eca97d
PS5, Line 7: drivers/smbus: SC16IS750 I2C to UART converter chip initialization
Please make it a statement [1]. Maybe:
> Support SC16IS750 I2C to UART converter chip
[1]: https://cbea.ms/git-commit/
File src/drivers/smbus/sc16is750_init.c:
https://review.coreboot.org/c/coreboot/+/67342/comment/b1fd6736_76aeb275
PS5, Line 4:
Mention the datasheet name and revision somewhere?
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Change subject: mb/google/zork: Enable AC wake
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Will this be a full wake or a dark resume? […]
This will be handled as a dark resume (followed by an immediate suspend) because AC plug/unplug are not categorized as input device events. Verified on DUT.
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Change subject: drivers/smbus: smbus console driver
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Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67339/comment/b92b33fb_6ff22c73
PS1, Line 7: drivers/smbus: smbus console driver
Please make that a statement by adding a verb in imperative mood [1].
[1]: https://cbea.ms/git-commit/
Patchset:
PS1:
Nice work!
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/67339/comment/ec5d8b9e_51985c1f
PS1, Line 305: Send coreboot debug output to the SMBus
Please add a dot/period at the end.
https://review.coreboot.org/c/coreboot/+/67339/comment/db283ade_77b7717e
PS1, Line 307: The output can be read with an I2C slave device connected the SMBus.
Please refer to some documentation, or elaborate.
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Change subject: soc/amd/common/block/apob: Add hashed APOB support
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/67301/comment/2007723a_47dafe2f
PS2, Line 22: RW_MRC_HASH
> Done. […]
Missed the last comment - if we want to store it in the GSC, that should be a new patch
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Change subject: soc/amd/common/block/apob: Add hashed APOB support
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/67301/comment/080f0eab_85e4c676
PS2, Line 22: RW_MRC_HASH
> Okay, I'll give that a test and see if I can simplify this even more. […]
Done. Set the hash to the last 8 bytes of the MRC_CACHE and the ABL loaded the APOB_NV without error.
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