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Change subject: soc/amd: Recalculate the field power in PSS table entry
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/soc/amd/cezanne/acpi.c:
https://review.coreboot.org/c/coreboot/+/67050/comment/9c452843_d99138c3
PS2, Line 198: power_in_mw
> Please vote should we change code or keep it as it is in AGESA. […]
I'm fine with keeping the code to match AGESA. Raul?
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Change subject: /: Update and rewrite README.md
......................................................................
Patch Set 2: Code-Review+1
(5 comments)
File README.md:
https://review.coreboot.org/c/coreboot/+/67119/comment/f2dd755a_cd0cccc1
PS2, Line 4: replacing the proprietary
: BIOS (firmware)
how about: replacing the proprietary firmware (BIOS/UEFI) ...
https://review.coreboot.org/c/coreboot/+/67119/comment/c5c45ea7_817ea799
PS2, Line 7: a different executable, referred to in coreboot as the payload.
perhaps add something like: Most often, the primary function of the payload is to boot the operating system (OS)
https://review.coreboot.org/c/coreboot/+/67119/comment/13795e99_4170dd21
PS2, Line 10: can scale from
perhaps: can be scaled down to
https://review.coreboot.org/c/coreboot/+/67119/comment/c8cd4c8a_bac5f30e
PS2, Line 24: `git clone https://review.coreboot.org/coreboot.git`.
mention the github mirror as an alternative?
https://review.coreboot.org/c/coreboot/+/67119/comment/b074a68a_bfc22e32
PS2, Line 68: become unavailable in the future.
perhaps add a note that releases are simply snapshots / no guarantee of stability
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Change subject: soc/amd/mendocino: Add svc_set_fw_hash_table
......................................................................
Patch Set 2: Code-Review+2
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Change subject: bd82x6x/early_pch: enable smbus in bootblock stage
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67340/comment/45488ea4_7f091500
PS2, Line 8:
Can you add the reason why.
File src/southbridge/intel/bd82x6x/early_pch.c:
https://review.coreboot.org/c/coreboot/+/67340/comment/2d48193b_c8c33cde
PS2, Line 316: ENV_RAMINIT
no need to use the pre-processor:
`if (ENV_RAMINIT || (CONFIG(CONSOLE_I2C_SMBUS) && (ENV_RAMINIT || ENV_INITIAL_STAGE))`
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Change subject: drivers/smbus: smbus console driver
......................................................................
Patch Set 1:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67339/comment/db1a29cb_e5ed6494
PS1, Line 8:
Can you add a description explaining what you are adding and why.
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/67339/comment/6e5823de_dc6252b4
PS1, Line 314: 0x48
This is specific to the hardware you are using. Maybe add a comment in the `help` explaining why this default is used.
https://review.coreboot.org/c/coreboot/+/67339/comment/013e20e1_37dd10e5
PS1, Line 315: CONSOLE_I2C_SMBUS
No need for the depends if it's in the `if` block
File src/drivers/smbus/i2c_smbus_console.c:
https://review.coreboot.org/c/coreboot/+/67339/comment/67bcd384_e35807b9
PS1, Line 16: (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE))
Don't we want console in all stages?
https://review.coreboot.org/c/coreboot/+/67339/comment/1f2933b8_30fe3c15
PS1, Line 17: do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, \
> Avoid unnecessary line continuations
Please fix.
File src/include/console/i2c_smbus.h:
https://review.coreboot.org/c/coreboot/+/67339/comment/a380a1bc_dd64fc7a
PS1, Line 15:
newline
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Change subject: mb/google/guybrush: enable display backlight in ramstage
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/67246/comment/18cf170d_2807f80f
PS1, Line 141: PAD_GPO
> The pin seems to be in the S5 domain, so it should retain its value
looking at the original bug, it seemed that some SKUs were having issues with the backlight being restored at min value coming out of Si0x, and using ACPI to set the backlight was part of the workaround. I'm unable to reproduce that problem on Dewatt though.
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Hello build bot (Jenkins), Jason Nien, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/67376
to look at the new patch set (#2).
Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
guybrush: remove RO_GSCVD area from FMAP
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com>
Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945
---
M src/mainboard/google/guybrush/chromeos.fmd
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/67376/2
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Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158134):
https://review.coreboot.org/c/coreboot/+/67376/comment/dff5e755_88f1d9ce
PS1, Line 9: This area relates to storing of AP RO verification information.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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